[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineSink to NPM (PR #115434)
Akshat Oke via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Nov 7 23:20:33 PST 2024
https://github.com/optimisan created https://github.com/llvm/llvm-project/pull/115434
Targets can set the EnableSinkAndFold option in CGPassBuilderOptions for
the NPM pipeline in buildCodeGenPipeline(... &Opts, ...)
>From 0f0ccc515bab4e2c8adfc5278bd6613464756e86 Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Wed, 30 Oct 2024 04:56:54 +0000
Subject: [PATCH] [CodeGen][NewPM] Port MachineSink to NPM
Targets can set the EnableSinkAndFold option in CGPassBuilderOptions for
the NPM pipeline in buildCodeGenPipeline(... &Opts, ...)
---
llvm/include/llvm/CodeGen/MachineSink.h | 26 ++++
llvm/include/llvm/CodeGen/Passes.h | 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 3 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +-
.../include/llvm/Target/CGPassBuilderOption.h | 1 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/MachineSink.cpp | 127 ++++++++++++------
llvm/lib/CodeGen/TargetPassConfig.cpp | 4 +-
llvm/lib/Passes/PassBuilder.cpp | 6 +
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 2 +-
llvm/test/CodeGen/AArch64/loop-sink.mir | 1 +
.../sink-and-fold-preserve-debugloc.mir | 2 +
...e-sink-temporal-divergence-swdev407790.mir | 2 +
.../CodeGen/ARM/machine-sink-multidef.mir | 2 +
.../Hexagon/machine-sink-float-usr.mir | 2 +
.../PowerPC/sink-down-more-instructions-1.mir | 2 +
.../CodeGen/RISCV/MachineSink-implicit-x0.mir | 1 +
.../CodeGen/SystemZ/machinesink-dead-cc.mir | 3 +
.../CodeGen/X86/machinesink-debug-inv-0.mir | 3 +
.../DebugInfo/MIR/X86/sink-leaves-undef.mir | 1 +
21 files changed, 155 insertions(+), 48 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/MachineSink.h
diff --git a/llvm/include/llvm/CodeGen/MachineSink.h b/llvm/include/llvm/CodeGen/MachineSink.h
new file mode 100644
index 00000000000000..b5bb59619c0474
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineSink.h
@@ -0,0 +1,26 @@
+//===- MachineSink.h --------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINESINK_H
+#define LLVM_CODEGEN_MACHINESINK_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class MachineSinkingPass : public PassInfoMixin<MachineSinkingPass> {
+ bool EnableSinkAndFold;
+
+public:
+ MachineSinkingPass(bool EnableSinkAndFold = false)
+ : EnableSinkAndFold(EnableSinkAndFold) {}
+ PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
+};
+
+} // namespace llvm
+#endif // LLVM_CODEGEN_MACHINESINK_H
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 72054ab1d3c21a..708abc86530516 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -349,7 +349,7 @@ namespace llvm {
extern char &EarlyMachineLICMID;
/// MachineSinking - This pass performs sinking on machine instructions.
- extern char &MachineSinkingID;
+ extern char &MachineSinkingLegacyID;
/// MachineCopyPropagation - This pass performs copy propagation on
/// machine instructions.
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 598498f8597b6a..66bb0d10ed4bc6 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -208,7 +208,7 @@ void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
void initializeMachineSchedulerPass(PassRegistry &);
-void initializeMachineSinkingPass(PassRegistry &);
+void initializeMachineSinkingLegacyPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
void initializeMachineUniformityAnalysisPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 9e95625fd1d881..2332bb7d8fcbcf 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -48,6 +48,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -1028,7 +1029,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineSSAOptimization(
addPass(EarlyMachineLICMPass());
addPass(MachineCSEPass());
- addPass(MachineSinkingPass());
+ addPass(MachineSinkingPass(Opt.EnableSinkAndFold));
addPass(PeepholeOptimizerPass());
// Clean-up the dead code that may have been generated by peephole
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bbd10c14e99491..041fe9c4e706d0 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -171,6 +171,13 @@ MACHINE_FUNCTION_PASS("verify<machine-trace-metrics>", MachineTraceMetricsVerifi
#define MACHINE_FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, \
PARAMS)
#endif
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "machine-sink", "MachineSinkingPass",
+ [](bool EnableSinkAndFold) {
+ return MachineSinkingPass(EnableSinkAndFold);
+ },
+ parseMachineSinkingPassOptions, "enable-sink-fold")
+
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"regallocfast", "RegAllocFast",
[](RegAllocFastPassOptions Opts) { return RegAllocFastPass(Opts); },
@@ -178,6 +185,7 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved from
@@ -233,7 +241,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitter
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
-DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h
index 8ab6d63a00056a..77f81902388179 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -32,6 +32,7 @@ struct CGPassBuilderOption {
bool EnableImplicitNullChecks = false;
bool EnableBlockPlacementStats = false;
bool EnableMachineFunctionSplitter = false;
+ bool EnableSinkAndFold = false;
bool MISchedPostRA = false;
bool EarlyLiveIntervals = false;
bool GCEmptyBlocks = false;
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index adddb8daaa0e91..b6881c339ff15e 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
initializeMachineSchedulerPass(Registry);
- initializeMachineSinkingPass(Registry);
+ initializeMachineSinkingLegacyPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
initializeMachineVerifierLegacyPassPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a0e09398602e9e..c06cc82cd569ac 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/MapVector.h"
@@ -36,6 +37,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -44,6 +46,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/LLVMContext.h"
@@ -115,7 +118,7 @@ STATISTIC(NumPostRACopySink, "Number of copies sunk after RA");
namespace {
-class MachineSinking : public MachineFunctionPass {
+class MachineSinking {
const TargetSubtargetInfo *STI = nullptr;
const TargetInstrInfo *TII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -127,6 +130,8 @@ class MachineSinking : public MachineFunctionPass {
const MachineBranchProbabilityInfo *MBPI = nullptr;
AliasAnalysis *AA = nullptr;
RegisterClassInfo RegClassInfo;
+ Pass *LegacyPass;
+ MachineFunctionAnalysisManager *MFAM;
// Remember which edges have been considered for breaking.
SmallSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>, 8>
@@ -182,29 +187,14 @@ class MachineSinking : public MachineFunctionPass {
bool EnableSinkAndFold;
public:
- static char ID; // Pass identification
+ MachineSinking(Pass *LegacyPass, MachineFunctionAnalysisManager *MFAM,
+ bool EnableSinkAndFold)
+ : LegacyPass(LegacyPass), MFAM(MFAM),
+ EnableSinkAndFold(EnableSinkAndFold) {}
- MachineSinking() : MachineFunctionPass(ID) {
- initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- MachineFunctionPass::getAnalysisUsage(AU);
- AU.addRequired<AAResultsWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<MachinePostDominatorTreeWrapperPass>();
- AU.addRequired<MachineCycleInfoWrapperPass>();
- AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
- AU.addPreserved<MachineCycleInfoWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- if (UseBlockFreqInfo)
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addRequired<TargetPassConfig>();
- }
+ bool run(MachineFunction &MF);
- void releaseMemory() override {
+ void releaseMemory() {
CEBCandidates.clear();
CEMergeCandidates.clear();
}
@@ -276,20 +266,45 @@ class MachineSinking : public MachineFunctionPass {
const MachineBasicBlock &MBB);
};
+class MachineSinkingLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ MachineSinkingLegacy() : MachineFunctionPass(ID) {
+ initializeMachineSinkingLegacyPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<MachinePostDominatorTreeWrapperPass>();
+ AU.addRequired<MachineCycleInfoWrapperPass>();
+ AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
+ AU.addPreserved<MachineCycleInfoWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ if (UseBlockFreqInfo)
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<TargetPassConfig>();
+ }
+};
+
} // end anonymous namespace
-char MachineSinking::ID = 0;
+char MachineSinkingLegacy::ID = 0;
-char &llvm::MachineSinkingID = MachineSinking::ID;
+char &llvm::MachineSinkingLegacyID = MachineSinkingLegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
- false)
+INITIALIZE_PASS_BEGIN(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking",
+ false, false)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
- false)
+INITIALIZE_PASS_END(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking",
+ false, false)
/// Return true if a target defined block prologue instruction interferes
/// with a sink candidate.
@@ -709,27 +724,57 @@ void MachineSinking::FindCycleSinkCandidates(
}
}
-bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+MachineSinkingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getFunction().hasOptNone())
+ return PreservedAnalyses::all();
+
+ MachineSinking Impl(nullptr, &MFAM, EnableSinkAndFold);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserve<MachineCycleAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+}
+
+bool MachineSinkingLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
+ bool EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+
+ MachineSinking Impl(this, nullptr, EnableSinkAndFold);
+ return Impl.run(MF);
+}
+
+#define GET_ANALYSIS(ANALYSIS, INFIX, GETTER) \
+ ((LegacyPass) \
+ ? &LegacyPass->getAnalysis<ANALYSIS##INFIX##WrapperPass>().GETTER() \
+ : &MFAM->getResult<ANALYSIS##Analysis>(MF))
+
+bool MachineSinking::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n");
STI = &MF.getSubtarget();
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
MRI = &MF.getRegInfo();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- PDT = &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
- CI = &getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
- MBFI = UseBlockFreqInfo
- ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
- : nullptr;
- MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ DT = GET_ANALYSIS(MachineDominatorTree, , getDomTree);
+ PDT = GET_ANALYSIS(MachinePostDominatorTree, , getPostDomTree);
+ CI = GET_ANALYSIS(MachineCycle, Info, getCycleInfo);
+ MBFI = UseBlockFreqInfo ? GET_ANALYSIS(MachineBlockFrequency, Info, getMBFI)
+ : nullptr;
+ MBPI = GET_ANALYSIS(MachineBranchProbability, Info, getMBPI);
+ AA = (LegacyPass)
+ ? &LegacyPass->getAnalysis<AAResultsWrapperPass>().getAAResults()
+ : &MFAM->getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager()
+ .getResult<AAManager>(MF.getFunction());
RegClassInfo.runOnMachineFunction(MF);
- TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
@@ -745,7 +790,8 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
// If we have anything we marked as toSplit, split it now.
for (const auto &Pair : ToSplit) {
- auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
+ auto NewSucc =
+ Pair.first->SplitCriticalEdge(Pair.second, LegacyPass, MFAM, nullptr);
if (NewSucc != nullptr) {
LLVM_DEBUG(dbgs() << " *** Splitting critical edge: "
<< printMBBReference(*Pair.first) << " -- "
@@ -804,6 +850,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
MRI->clearKillFlags(I);
RegsToClearKillFlags.clear();
+ releaseMemory();
return EverMadeChange;
}
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 782ed6062191ce..be71488e39458d 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -317,7 +317,7 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID,
if (StandardID == &MachineLICMID)
return applyDisable(TargetID, DisablePostRAMachineLICM);
- if (StandardID == &MachineSinkingID)
+ if (StandardID == &MachineSinkingLegacyID)
return applyDisable(TargetID, DisableMachineSink);
if (StandardID == &PostRAMachineSinkingID)
@@ -1304,7 +1304,7 @@ void TargetPassConfig::addMachineSSAOptimization() {
addPass(&EarlyMachineLICMID);
addPass(&MachineCSELegacyID);
- addPass(&MachineSinkingID);
+ addPass(&MachineSinkingLegacyID);
addPass(&PeepholeOptimizerID);
// Clean-up the dead code that may have been generated by peephole
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index bd670c0b13df1d..b7a2c881d495c3 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -114,6 +114,7 @@
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
@@ -1277,6 +1278,11 @@ Expected<RealtimeSanitizerOptions> parseRtSanPassOptions(StringRef Params) {
return Result;
}
+Expected<bool> parseMachineSinkingPassOptions(StringRef Params) {
+ return PassBuilder::parseSinglePassOption(Params, "enable-sink-fold",
+ "MachineSinkingPass");
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index a5a147da8da1c5..20c86362ded2a6 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -492,7 +492,7 @@ void NVPTXPassConfig::addMachineSSAOptimization() {
addPass(&EarlyMachineLICMID);
addPass(&MachineCSELegacyID);
- addPass(&MachineSinkingID);
+ addPass(&MachineSinkingLegacyID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
addPass(&PeepholeOptimizerID);
diff --git a/llvm/test/CodeGen/AArch64/loop-sink.mir b/llvm/test/CodeGen/AArch64/loop-sink.mir
index 36d39ffbadc29a..de81d99369394b 100644
--- a/llvm/test/CodeGen/AArch64/loop-sink.mir
+++ b/llvm/test/CodeGen/AArch64/loop-sink.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=machine-sink -sink-insts-to-avoid-spills -aarch64-enable-sink-fold=true %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes="machine-sink<enable-sink-fold>" -sink-insts-to-avoid-spills %s -o - 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
index be5737d297b290..f146c4436bbfa8 100644
--- a/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
@@ -1,4 +1,6 @@
# RUN: llc %s -run-pass=machine-sink --aarch64-enable-sink-fold=true -o - | FileCheck %s
+
+# RUN: llc %s -passes="machine-sink<enable-sink-fold>" -o - | FileCheck %s
--- |
target triple = "aarch64-linux"
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
index 329f2967121603..7ef6d37ddc1832 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -passes=machine-sink -o - %s | FileCheck %s
+
---
name: machine-sink-temporal-divergence
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/machine-sink-multidef.mir b/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
index 737ca824265d6b..485e659a53ab6b 100644
--- a/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
+++ b/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -run-pass=machine-sink -mtriple=arm-none-eabi | FileCheck %s
+# RUN: llc %s -o - -passes=machine-sink -mtriple=arm-none-eabi | FileCheck %s
+
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "arm-none-unknown-eabi"
diff --git a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
index 45621d98da3ef6..480b704f44af71 100644
--- a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
+++ b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
@@ -1,5 +1,7 @@
# RUN: llc -march=hexagon -run-pass machine-sink -o - %s | FileCheck %s
+# RUN: llc -march=hexagon -passes machine-sink -o - %s | FileCheck %s
+
# Test that MachineSink does not sink F2_conv_w2sf.
# CHECK: name:{{.*}} main
# CHECK: J2_call @feclearexcept
diff --git a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
index fe50d05ab93a5f..ee16a8c69afb74 100644
--- a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
+++ b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
@@ -2,6 +2,8 @@
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \
# RUN: -run-pass=machine-sink | FileCheck %s
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \
+# RUN: -passes=machine-sink | FileCheck %s
--- |
; ModuleID = 'sink-down-more-instructions-1.ll'
source_filename = "sink-down-more-instructions-1.c"
diff --git a/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir b/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
index ef006fca60a401..8f5c763e950209 100644
--- a/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
+++ b/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=riscv32 %s -run-pass=machine-sink -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 %s -passes=machine-sink -o - | FileCheck %s
# Verify that sinking of '%20:gpr = LUI 1, implicit $x0' is not inhibited by
# the implicit use of '$x0'.
diff --git a/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir b/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
index 8516cc9114c764..7b62c0b49b816a 100644
--- a/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
+++ b/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
@@ -1,6 +1,9 @@
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -run-pass=machine-sink %s -o - \
# RUN: -verify-machineinstrs | FileCheck %s
#
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -passes=machine-sink %s -o - \
+# RUN: -verify-machineinstrs | FileCheck %s
+#
# Test that the AGHIK can be sunk into %bb.4. It has a def of CC, but it is dead.
--- |
diff --git a/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir b/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
index 643c557db77f7a..20207311e66cd8 100644
--- a/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
+++ b/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
@@ -2,6 +2,9 @@
# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=machine-sink %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=mir-debugify,machine-sink,mir-strip-debug %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -passes=machine-sink %s -o - | FileCheck %s
+# TODO: add test with mir-debugify once it is ported
+
# Verify that machine-sink pass is debug invariant wrt to given input. Since
# the pass examines MemOperands the IR is required for the original bug to
# trigger.
diff --git a/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir b/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
index 73a571dbf150f1..b7df7983073e80 100644
--- a/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
+++ b/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
@@ -1,4 +1,5 @@
# RUN: llc %s -o - -run-pass=machine-sink -mtriple=x86_64-- | FileCheck %s
+# RUN: llc %s -o - -passes=machine-sink -mtriple=x86_64-- | FileCheck %s
# This is a copy of test/CodeGen/X86/MachineSink-DbgValue.ll, where we
# additionally test that when the MOV32rm defining %0 is sunk, it leaves
# an 'undef' DBG_VALUE behind to terminate earlier location ranges.
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