[llvm-branch-commits] [llvm] 1bb79e8 - Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)"

[via llvm-branch-commits]

Author: dyung
Date: 2024-11-07T13:01:31-05:00
New Revision: 1bb79e8f60fa990228be1af9168c92755dd9ed96

URL: https://github.com/llvm/llvm-project/commit/1bb79e8f60fa990228be1af9168c92755dd9ed96
DIFF: https://github.com/llvm/llvm-project/commit/1bb79e8f60fa990228be1af9168c92755dd9ed96.diff

LOG: Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)"

This reverts commit 21835ee28d47037137ea5a73ba466211b3e1a2d1.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

Removed: 
    llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 2ddcd5a799cb10..1e43d2727a00da 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -694,22 +694,22 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
     const llvm::MachineFunction &MF)
     : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
       MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
-      GDSSize(MFI.getGDSSize()), DynLDSAlign(MFI.getDynLDSAlign()),
-      IsEntryFunction(MFI.isEntryFunction()),
+      GDSSize(MFI.getGDSSize()),
+      DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
       NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
       Occupancy(MFI.getOccupancy()),
-      NumPhysicalVGPRSpillLanes(MFI.getNumPhysicalVGPRSpillLanes()),
       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
       BytesInStackArgArea(MFI.getBytesInStackArgArea()),
       ReturnsVoid(MFI.returnsVoid()),
       ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
-      PSInputAddr(MFI.getPSInputAddr()), PSInputEnable(MFI.getPSInputEnable()),
+      PSInputAddr(MFI.getPSInputAddr()),
+      PSInputEnable(MFI.getPSInputEnable()),
       Mode(MFI.getMode()) {
   for (Register Reg : MFI.getSGPRSpillPhysVGPRs())
     SpillPhysVGPRS.push_back(regToString(Reg, TRI));
@@ -754,7 +754,6 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
   BytesInStackArgArea = YamlMFI.BytesInStackArgArea;
   ReturnsVoid = YamlMFI.ReturnsVoid;
-  NumPhysicalVGPRSpillLanes = YamlMFI.NumPhysicalVGPRSpillLanes;
 
   if (YamlMFI.ScavengeFI) {
     auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());

diff  --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index db4aefadaee3e5..018322eaa18665 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -275,7 +275,6 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
   // TODO: 10 may be a better default since it's the maximum.
   unsigned Occupancy = 0;
 
-  unsigned NumPhysicalVGPRSpillLanes = 0;
   SmallVector<StringValue, 2> SpillPhysVGPRS;
   SmallVector<StringValue> WWMReservedRegs;
 
@@ -338,8 +337,6 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
     YamlIO.mapOptional("highBitsOf32BitAddress",
                        MFI.HighBitsOf32BitAddress, 0u);
     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
-    YamlIO.mapOptional("numPhysicalVGPRSpillLanes",
-                       MFI.NumPhysicalVGPRSpillLanes);
     YamlIO.mapOptional("spillPhysVGPRs", MFI.SpillPhysVGPRS);
     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
@@ -617,10 +614,6 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
   ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
   ArrayRef<Register> getSGPRSpillPhysVGPRs() const { return SpillPhysVGPRs; }
 
-  unsigned getNumPhysicalVGPRSpillLanes() const {
-    return NumPhysicalVGPRSpillLanes;
-  }
-
   const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
   const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll b/llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll
deleted file mode 100644
index a211427c5e0c17..00000000000000
--- a/llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa --stop-after=prologepilog -o - %s | FileCheck %s
-
-; Spill the PC SGPR30_31 and FP to physical VGPR
-
-define void @test() #0 {
-; CHECK: machineFunctionInfo
-; CHECK: numPhysicalVGPRSpillLanes: 3
-entry:
-  %call = call i32 @ext_func()
-  ret void
-}
-
-declare i32 @ext_func();
-
-attributes #0 = { nounwind "amdgpu-num-vgpr"="41" "amdgpu-num-sgpr"="34" }