[llvm-branch-commits] [llvm] AMDGPU: Default to selecting frame indexes to SGPRs (PR #115060)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Nov 6 09:13:43 PST 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/115060
>From bbf5b1403252a7a7c8b3d0a8f785a5a96795584d Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 26 Jul 2024 18:39:08 +0400
Subject: [PATCH] AMDGPU: Default to selecting frame indexes to SGPRs
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 5 +-
.../CodeGen/AMDGPU/amdgpu.private-memory.ll | 5 +-
.../CodeGen/AMDGPU/captured-frame-index.ll | 72 +-
llvm/test/CodeGen/AMDGPU/commute-compares.ll | 4 +-
llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll | 122 ++-
llvm/test/CodeGen/AMDGPU/flat-scratch.ll | 155 +--
.../CodeGen/AMDGPU/frame-index-elimination.ll | 47 +-
.../AMDGPU/global_atomics_scan_fmax.ll | 72 +-
.../AMDGPU/global_atomics_scan_fmin.ll | 72 +-
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 24 +-
.../kernel-vgpr-spill-mubuf-with-voffset.ll | 14 +-
.../CodeGen/AMDGPU/large-alloca-compute.ll | 2 +-
.../local-stack-alloc-block-sp-reference.ll | 90 +-
.../materialize-frame-index-sgpr.gfx10.ll | 244 +++--
.../AMDGPU/materialize-frame-index-sgpr.ll | 891 ++++++++----------
.../test/CodeGen/AMDGPU/memcpy-fixed-align.ll | 8 +-
.../AMDGPU/required-export-priority.ll | 4 +-
llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 14 +-
llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 27 +-
19 files changed, 884 insertions(+), 988 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 52df38c352cf53..5f4cca0645b0ef 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2175,8 +2175,11 @@ foreach vt = [i32, p3, p5, p6, p2] in {
>;
}
+// FIXME: The register bank of the frame index should depend on the
+// users, and transitive users of the add. We may require an
+// unnecessary copy from SGPR to VGPR.
def : GCNPat <
- (p5 frameindex:$fi),
+ (VGPRImm<(p5 frameindex)>:$fi),
(V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi)))
>;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
index 5889af70a8f092..c1a957dec3e867 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
@@ -364,9 +364,10 @@ entry:
; FUNC-LABEL: ptrtoint:
; SI-NOT: ds_write
+; SI: s_add_i32 [[S_ADD_OFFSET:s[0-9]+]], s{{[0-9]+}}, 5
; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
-; SI: v_add_{{[iu]}}32_e32 [[ADD_OFFSET:v[0-9]+]], vcc, 5,
-; SI: buffer_load_dword v{{[0-9]+}}, [[ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ;
+; SI: v_mov_b32_e32 [[V_ADD_OFFSET:v[0-9]+]], [[S_ADD_OFFSET]]
+; SI: buffer_load_dword v{{[0-9]+}}, [[V_ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ;
define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], addrspace(5)
%tmp0 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a
diff --git a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
index ca0c669056ee33..2ec4c074a892dc 100644
--- a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
+++ b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
@@ -147,19 +147,14 @@ define amdgpu_kernel void @stored_fi_to_global_2_small_objects(ptr addrspace(1)
; GCN-LABEL: {{^}}kernel_stored_fi_to_global_huge_frame_offset:
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
-; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
-; FIXME: Re-initialize
-; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}}
+; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
-; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]
-
+; GCN-DAG: v_mov_b32_e32 [[V_BASE_1_OFF:v[0-9]+]], 0x4000{{$}}
+; GCN: buffer_store_dword [[K]], [[V_BASE_1_OFF]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
-; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
-; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
-
-; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
+; GCN: buffer_store_dword [[V_BASE_1_OFF]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @kernel_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
%tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32], addrspace(5)
@@ -171,20 +166,20 @@ define amdgpu_kernel void @kernel_stored_fi_to_global_huge_frame_offset(ptr addr
ret void
}
+; FIXME: Shift of SP repeated twice
; GCN-LABEL: {{^}}func_stored_fi_to_global_huge_frame_offset:
-; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
+; GCN-DAG: v_lshr_b32_e64 [[FI_TMP_0:v[0-9]+]], s32, 6
+; GCN-DAG: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:4{{$}}
-; GCN: v_lshr_b32_e64 [[FI_TMP:v[0-9]+]], s32, 6
-; GCN: v_add_i32_e32 [[BASE_0_1:v[0-9]+]], vcc, 4, [[FI_TMP]]{{$}}
+; GCN-DAG: v_add_i32_e32 [[FI_0:v[0-9]+]], vcc, 0x4000, [[FI_TMP_0]]{{$}}
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
-; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]
-; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
-; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
-
-; GCN: buffer_store_dword [[BASE_1_OFF_2]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
+; GCN: buffer_store_dword [[K]], [[FI_0]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
+; GCN: v_lshr_b32_e64 [[FI_TMP_1:v[0-9]+]], s32, 6
+; GCN: v_add_i32_e32 [[BASE_0_1:v[0-9]+]], vcc, 60, [[FI_TMP_1]]{{$}}
+; GCN: buffer_store_dword [[BASE_0_1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
define void @func_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
%tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32], addrspace(5)
@@ -217,9 +212,9 @@ entry:
ret void
}
-; FIXME: This is broken, and the sgpr input just gets replaced with a VGPR
; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_sgpr:
-; GCN: v_lshr_b32_e64 [[FI:v[0-9]+]], s32, 6
+; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
+; GCN-NOT: [[FI]]
; GCN: ; use [[FI]]
define void @func_alloca_offset0__use_asm_sgpr() {
%alloca = alloca i32, addrspace(5)
@@ -238,9 +233,9 @@ define void @func_alloca_offset0__use_asm_vgpr() {
}
; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_phys_sgpr:
-; GCN: s_lshr_b32 s8, s32, 6
+; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; use s8
+; GCN-NEXT: ; use [[FI]]
define void @func_alloca_offset0__use_asm_phys_sgpr() {
%alloca = alloca i32, addrspace(5)
call void asm sideeffect "; use $0", "{s8}"(ptr addrspace(5) %alloca)
@@ -258,12 +253,11 @@ define void @func_alloca_offset0__use_asm_phys_vgpr() {
}
; GCN-LABEL: {{^}}func_alloca_offset_use_asm_sgpr:
-; GCN: v_lshr_b32_e64 [[FI0_TMP0:v[0-9]+]], s32, 6
-; GCN-NEXT: v_add_i32_e32 [[FI0:v[0-9]+]], vcc, 16, [[FI0_TMP0]]
+; GCN: s_lshr_b32 [[FI0_TMP0:s[0-9]+]], s32, 6
+; GCN-NEXT: s_add_i32 [[FI0:s[0-9]+]], [[FI0_TMP0]], 16
-; GCN: v_lshr_b32_e64 [[TMP:v[0-9]+]], s32, 6
-; GCN-NEXT: s_movk_i32 vcc_lo, 0x4010
-; GCN-NEXT: v_add_i32_e32 [[TMP]], vcc, vcc_lo, [[TMP]]
+; GCN: s_lshr_b32 [[TMP:s[0-9]+]], s32, 6
+; GCN-NEXT: s_addk_i32 [[TMP]], 0x4010
; GCN-NEXT: ;;#ASMSTART
; GCN: ; use [[TMP]]
define void @func_alloca_offset_use_asm_sgpr() {
@@ -274,19 +268,17 @@ define void @func_alloca_offset_use_asm_sgpr() {
ret void
}
-; FIXME: Shouldn't need to materialize constant
; GCN-LABEL: {{^}}func_alloca_offset_use_asm_vgpr:
-; GCN: v_lshr_b32_e64 [[FI0_TMP:v[0-9]+]], s32, 6
-; GCN-NEXT: v_add_i32_e32 [[FI0:v[0-9]+]], vcc, 16, [[FI0_TMP]]
+; GCN: s_lshr_b32 [[S_FI:s[0-9]+]], s32, 6
+; GCN: v_lshr_b32_e64 [[V_FI:v[0-9]+]], s32, 6
+; GCN: s_movk_i32 vcc_lo, 0x4010
+; GCN: s_add_i32 [[S_FI]], [[S_FI]], 16
; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; use [[FI0]]
+; GCN-NEXT: ; use [[S_FI]]
; GCN-NEXT: ;;#ASMEND
-
-; GCN: v_lshr_b32_e64 [[FI1_TMP:v[0-9]+]], s32, 6
-; GCN-NEXT: s_movk_i32 vcc_lo, 0x4010
-; GCN-NEXT: v_add_i32_e32 [[FI1:v[0-9]+]], vcc, vcc_lo, [[FI1_TMP]]
+; GCN-NEXT: v_add_i32_e32 [[V_FI:v[0-9]+]], vcc, vcc_lo, [[V_FI]]
; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; use [[FI1]]
+; GCN-NEXT: ; use [[V_FI]]
; GCN-NEXT: ;;#ASMEND
define void @func_alloca_offset_use_asm_vgpr() {
%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
@@ -296,17 +288,15 @@ define void @func_alloca_offset_use_asm_vgpr() {
ret void
}
-; FIXME: Using VGPR for SGPR input
; GCN-LABEL: {{^}}kernel_alloca_offset_use_asm_sgpr:
-; GCN: v_mov_b32_e32 v0, 16
+; GCN: s_mov_b32 [[FI0:s[0-9]+]], 16
; GCN-NOT: v0
; GCN: ;;#ASMSTART
-; GCN-NEXT: ; use v0
+; GCN-NEXT: ; use [[FI0]]
; GCN-NEXT: ;;#ASMEND
-
-; GCN: v_mov_b32_e32 v0, 0x4010
+; GCN: s_movk_i32 [[FI1:s[0-9]+]], 0x4010
; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; use v0
+; GCN-NEXT: ; use [[FI1]]
; GCN-NEXT: ;;#ASMEND
define amdgpu_kernel void @kernel_alloca_offset_use_asm_sgpr() {
%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares.ll b/llvm/test/CodeGen/AMDGPU/commute-compares.ll
index d94e75c8c8e223..d36dcc247331c7 100644
--- a/llvm/test/CodeGen/AMDGPU/commute-compares.ll
+++ b/llvm/test/CodeGen/AMDGPU/commute-compares.ll
@@ -699,8 +699,8 @@ define amdgpu_kernel void @commute_uno_2.0_f64(ptr addrspace(1) %out, ptr addrsp
; GCN-LABEL: {{^}}commute_frameindex:
; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
-; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
-; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]]
+; GCN: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
+; GCN: v_cmp_eq_u32_e32 vcc, [[FI]], v{{[0-9]+}}
define amdgpu_kernel void @commute_frameindex(ptr addrspace(1) nocapture %out) #0 {
entry:
%stack0 = alloca i32, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
index 9d9d5b239a12c8..c145ce06f9dd21 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
@@ -15,18 +15,16 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -145,18 +143,17 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
+; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -282,18 +279,17 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v2
+; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -419,19 +415,17 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -556,14 +550,13 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
-; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
@@ -698,14 +691,13 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
-; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v2
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
@@ -840,19 +832,17 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
+; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
+; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
@@ -977,14 +967,13 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
-; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
@@ -1119,17 +1108,16 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[2:3], 0x24
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
-; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
-; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
-; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
-; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
+; GFX940-SDAG-NEXT: v_mov_b32_e32 v3, s0
+; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v3
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
+; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:2 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index 105174d7c9b3b7..0c1d3b25463038 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -4688,13 +4688,13 @@ define amdgpu_ps void @large_offset() {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], off, s0 offset:3024 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v0, 16
+; GFX9-NEXT: s_mov_b32 s0, 16
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ; use s0
; GFX9-NEXT: ;;#ASMEND
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x810
+; GFX9-NEXT: s_movk_i32 s0, 0x810
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; use v0
+; GFX9-NEXT: ; use s0
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_endpgm
;
@@ -4705,27 +4705,29 @@ define amdgpu_ps void @large_offset() {
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_movk_i32 s0, 0xbd0
+; GFX10-NEXT: s_movk_i32 s0, 0x810
+; GFX10-NEXT: s_add_i32 s1, s0, 0x3c0
; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: v_mov_b32_e32 v2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, v0
-; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s0
+; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s1
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: scratch_load_dwordx4 v[0:3], off, s0 glc dlc
+; GFX10-NEXT: scratch_load_dwordx4 v[0:3], off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v0, 16
-; GFX10-NEXT: v_mov_b32_e32 v1, 0x810
+; GFX10-NEXT: s_mov_b32 s1, 16
; GFX10-NEXT: ;;#ASMSTART
-; GFX10-NEXT: ; use v0
+; GFX10-NEXT: ; use s1
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: ;;#ASMSTART
-; GFX10-NEXT: ; use v1
+; GFX10-NEXT: ; use s0
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: large_offset:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_mov_b32 s0, 16
+; GFX11-NEXT: s_movk_i32 s1, 0x810
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v1, v0
; GFX11-NEXT: v_mov_b32_e32 v2, v0
@@ -4734,18 +4736,19 @@ define amdgpu_ps void @large_offset() {
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_load_b128 v[0:3], off, off offset:3024 glc dlc
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0x810
; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use v0
+; GFX11-NEXT: ; use s0
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use v1
+; GFX11-NEXT: ; use s1
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: large_offset:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-NEXT: s_mov_b32 s0, 0
+; GFX12-NEXT: s_movk_i32 s1, 0x800
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
; GFX12-NEXT: v_mov_b32_e32 v3, v0
@@ -4753,12 +4756,11 @@ define amdgpu_ps void @large_offset() {
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: scratch_load_b128 v[0:3], off, off offset:3008 scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x800
; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use v0
+; GFX12-NEXT: ; use s0
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use v1
+; GFX12-NEXT: ; use s1
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: s_endpgm
;
@@ -4780,13 +4782,13 @@ define amdgpu_ps void @large_offset() {
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, s0 offset:3024 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 16
+; GFX9-PAL-NEXT: s_mov_b32 s0, 16
; GFX9-PAL-NEXT: ;;#ASMSTART
-; GFX9-PAL-NEXT: ; use v0
+; GFX9-PAL-NEXT: ; use s0
; GFX9-PAL-NEXT: ;;#ASMEND
-; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 0x810
+; GFX9-PAL-NEXT: s_movk_i32 s0, 0x810
; GFX9-PAL-NEXT: ;;#ASMSTART
-; GFX9-PAL-NEXT: ; use v0
+; GFX9-PAL-NEXT: ; use s0
; GFX9-PAL-NEXT: ;;#ASMEND
; GFX9-PAL-NEXT: s_endpgm
;
@@ -4800,49 +4802,82 @@ define amdgpu_ps void @large_offset() {
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: scratch_load_dwordx4 v[0:3], off, off offset:3024 sc0 sc1
; GFX940-NEXT: s_waitcnt vmcnt(0)
-; GFX940-NEXT: v_mov_b32_e32 v0, 16
+; GFX940-NEXT: s_mov_b32 s0, 16
; GFX940-NEXT: ;;#ASMSTART
-; GFX940-NEXT: ; use v0
+; GFX940-NEXT: ; use s0
; GFX940-NEXT: ;;#ASMEND
-; GFX940-NEXT: v_mov_b32_e32 v0, 0x810
+; GFX940-NEXT: s_movk_i32 s0, 0x810
; GFX940-NEXT: ;;#ASMSTART
-; GFX940-NEXT: ; use v0
+; GFX940-NEXT: ; use s0
; GFX940-NEXT: ;;#ASMEND
; GFX940-NEXT: s_endpgm
;
-; GFX10-PAL-LABEL: large_offset:
-; GFX10-PAL: ; %bb.0: ; %bb
-; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
-; GFX10-PAL-NEXT: s_mov_b32 s2, s0
-; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX10-PAL-NEXT: s_add_u32 s2, s2, s0
-; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
-; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
-; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
-; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-PAL-NEXT: s_movk_i32 s0, 0xbd0
-; GFX10-PAL-NEXT: v_mov_b32_e32 v1, v0
-; GFX10-PAL-NEXT: v_mov_b32_e32 v2, v0
-; GFX10-PAL-NEXT: v_mov_b32_e32 v3, v0
-; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0
-; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, s0 glc dlc
-; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 16
-; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x810
-; GFX10-PAL-NEXT: ;;#ASMSTART
-; GFX10-PAL-NEXT: ; use v0
-; GFX10-PAL-NEXT: ;;#ASMEND
-; GFX10-PAL-NEXT: ;;#ASMSTART
-; GFX10-PAL-NEXT: ; use v1
-; GFX10-PAL-NEXT: ;;#ASMEND
-; GFX10-PAL-NEXT: s_endpgm
+; GFX1010-PAL-LABEL: large_offset:
+; GFX1010-PAL: ; %bb.0: ; %bb
+; GFX1010-PAL-NEXT: s_getpc_b64 s[2:3]
+; GFX1010-PAL-NEXT: s_mov_b32 s2, s0
+; GFX1010-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX1010-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1010-PAL-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX1010-PAL-NEXT: s_add_u32 s2, s2, s0
+; GFX1010-PAL-NEXT: s_addc_u32 s3, s3, 0
+; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX1010-PAL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1010-PAL-NEXT: s_movk_i32 s0, 0x810
+; GFX1010-PAL-NEXT: s_add_i32 s1, s0, 0x3c0
+; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, v0
+; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, v0
+; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, v0
+; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1
+; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, s1 glc dlc
+; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-PAL-NEXT: s_mov_b32 s1, 16
+; GFX1010-PAL-NEXT: ;;#ASMSTART
+; GFX1010-PAL-NEXT: ; use s1
+; GFX1010-PAL-NEXT: ;;#ASMEND
+; GFX1010-PAL-NEXT: ;;#ASMSTART
+; GFX1010-PAL-NEXT: ; use s0
+; GFX1010-PAL-NEXT: ;;#ASMEND
+; GFX1010-PAL-NEXT: s_endpgm
+;
+; GFX1030-PAL-LABEL: large_offset:
+; GFX1030-PAL: ; %bb.0: ; %bb
+; GFX1030-PAL-NEXT: s_getpc_b64 s[2:3]
+; GFX1030-PAL-NEXT: s_mov_b32 s2, s0
+; GFX1030-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX1030-PAL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1030-PAL-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX1030-PAL-NEXT: s_add_u32 s2, s2, s0
+; GFX1030-PAL-NEXT: s_addc_u32 s3, s3, 0
+; GFX1030-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX1030-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX1030-PAL-NEXT: v_mov_b32_e32 v0, 0
+; GFX1030-PAL-NEXT: s_movk_i32 s0, 0x810
+; GFX1030-PAL-NEXT: s_add_i32 s1, s0, 0x3c0
+; GFX1030-PAL-NEXT: v_mov_b32_e32 v1, v0
+; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, v0
+; GFX1030-PAL-NEXT: v_mov_b32_e32 v3, v0
+; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1
+; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1030-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, s1 glc dlc
+; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
+; GFX1030-PAL-NEXT: s_mov_b32 s1, 16
+; GFX1030-PAL-NEXT: ;;#ASMSTART
+; GFX1030-PAL-NEXT: ; use s1
+; GFX1030-PAL-NEXT: ;;#ASMEND
+; GFX1030-PAL-NEXT: ;;#ASMSTART
+; GFX1030-PAL-NEXT: ; use s0
+; GFX1030-PAL-NEXT: ;;#ASMEND
+; GFX1030-PAL-NEXT: s_endpgm
;
; GFX11-PAL-LABEL: large_offset:
; GFX11-PAL: ; %bb.0: ; %bb
; GFX11-PAL-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PAL-NEXT: s_mov_b32 s0, 16
+; GFX11-PAL-NEXT: s_movk_i32 s1, 0x810
; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-PAL-NEXT: v_mov_b32_e32 v1, v0
; GFX11-PAL-NEXT: v_mov_b32_e32 v2, v0
@@ -4851,18 +4886,19 @@ define amdgpu_ps void @large_offset() {
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-PAL-NEXT: scratch_load_b128 v[0:3], off, off offset:3024 glc dlc
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-PAL-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0x810
; GFX11-PAL-NEXT: ;;#ASMSTART
-; GFX11-PAL-NEXT: ; use v0
+; GFX11-PAL-NEXT: ; use s0
; GFX11-PAL-NEXT: ;;#ASMEND
; GFX11-PAL-NEXT: ;;#ASMSTART
-; GFX11-PAL-NEXT: ; use v1
+; GFX11-PAL-NEXT: ; use s1
; GFX11-PAL-NEXT: ;;#ASMEND
; GFX11-PAL-NEXT: s_endpgm
;
; GFX12-PAL-LABEL: large_offset:
; GFX12-PAL: ; %bb.0: ; %bb
; GFX12-PAL-NEXT: v_mov_b32_e32 v0, 0
+; GFX12-PAL-NEXT: s_mov_b32 s0, 0
+; GFX12-PAL-NEXT: s_movk_i32 s1, 0x800
; GFX12-PAL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-PAL-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0
; GFX12-PAL-NEXT: v_mov_b32_e32 v3, v0
@@ -4870,12 +4906,11 @@ define amdgpu_ps void @large_offset() {
; GFX12-PAL-NEXT: s_wait_storecnt 0x0
; GFX12-PAL-NEXT: scratch_load_b128 v[0:3], off, off offset:3008 scope:SCOPE_SYS
; GFX12-PAL-NEXT: s_wait_loadcnt 0x0
-; GFX12-PAL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x800
; GFX12-PAL-NEXT: ;;#ASMSTART
-; GFX12-PAL-NEXT: ; use v0
+; GFX12-PAL-NEXT: ; use s0
; GFX12-PAL-NEXT: ;;#ASMEND
; GFX12-PAL-NEXT: ;;#ASMSTART
-; GFX12-PAL-NEXT: ; use v1
+; GFX12-PAL-NEXT: ; use s1
; GFX12-PAL-NEXT: ;;#ASMEND
; GFX12-PAL-NEXT: s_endpgm
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index e3cd8028422ddb..c11b7d67a8a214 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -82,13 +82,13 @@ define void @func_add_constant_to_fi_i32() #0 {
; vgpr
; GCN-LABEL: {{^}}func_other_fi_user_i32:
+; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
+; MUBUF: s_mul_i32 [[MUL:s[0-9]+]], [[SCALED]], 9
+; MUBUF: v_mov_b32_e32 v0, [[MUL]]
-; CI: v_lshr_b32_e64 v0, s32, 6
+; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], s32, 9
+; GFX9-FLATSCR: v_mov_b32_e32 v0, [[MUL]]
-; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
-; GFX9-FLATSCR: v_mov_b32_e32 v0, s32
-
-; GCN-NEXT: v_mul_lo_u32 v0, v0, 9
; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0
define void @func_other_fi_user_i32() #0 {
@@ -126,8 +126,7 @@ define void @func_load_private_arg_i32_ptr(ptr addrspace(5) %ptr) #0 {
; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
; GFX9-MUBUF-NEXT: v_or_b32_e32 v0, 4, [[SHIFT]]
-; GFX9-FLATSCR: v_mov_b32_e32 [[SP:v[0-9]+]], s32
-; GFX9-FLATSCR-NEXT: v_or_b32_e32 v0, 4, [[SP]]
+; GFX9-FLATSCR: v_or_b32_e64 v0, s32, 4
; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0
@@ -190,17 +189,16 @@ ret:
; Added offset can't be used with VOP3 add
; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32:
-; CI-DAG: s_movk_i32 [[K:s[0-9]+|vcc_lo|vcc_hi]], 0x200
-; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s32, 6
-; CI: v_add_i32_e32 [[VZ:v[0-9]+]], vcc, [[K]], [[SCALED]]
+; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
+; MUBUF: s_addk_i32 [[SCALED]], 0x200
-; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
-; GFX9-MUBUF: v_add_u32_e32 [[VZ:v[0-9]+]], 0x200, [[SCALED]]
+; MUBUF: s_mul_i32 [[Z:s[0-9]+]], [[SCALED]], 9
+; MUBUF: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
-; GFX9-FLATSCR-DAG: s_add_i32 [[SZ:[^,]+]], s32, 0x200
-; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[SZ]]
+; GFX9-FLATSCR: s_add_i32 [[SZ:[^,]+]], s32, 0x200
+; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], [[SZ]], 9
+; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[MUL]]
-; GCN: v_mul_lo_u32 [[VZ]], [[VZ]], 9
; GCN: ds_write_b32 v0, [[VZ]]
define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
%alloca0 = alloca [128 x i32], align 4, addrspace(5)
@@ -215,17 +213,15 @@ define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live:
-; CI-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x200
-; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s32, 6
-; CI: v_add_i32_e64 [[VZ:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
-
-; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
-; GFX9-MUBUF: v_add_u32_e32 [[VZ:v[0-9]+]], 0x200, [[SCALED]]
+; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
+; MUBUF: s_addk_i32 [[SCALED]], 0x200
+; MUBUF: s_mul_i32 [[Z:s[0-9]+]], [[SCALED]], 9
+; MUBUF: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
-; GFX9-FLATSCR-DAG: s_add_i32 [[SZ:[^,]+]], s32, 0x200
-; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[SZ]]
+; GFX9-FLATSCR: s_add_i32 [[SZ:[^,]+]], s32, 0x200
+; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], [[SZ]], 9
+; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[MUL]]
-; GCN: v_mul_lo_u32 [[VZ]], [[VZ]], 9
; GCN: ds_write_b32 v0, [[VZ]]
define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
%alloca0 = alloca [128 x i32], align 4, addrspace(5)
@@ -284,8 +280,7 @@ bb5:
; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
; GFX9-MUBUF-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
-; GFX9-FLATSCR: v_mov_b32_e32 [[SP:v[0-9]+]], s32
-; GFX9-FLATSCR-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SP]]
+; GFX9-FLATSCR: v_or_b32_e64 [[PTR:v[0-9]+]], s32, 4
; GCN: ds_write_b32 v{{[0-9]+}}, [[PTR]]
define void @alloca_ptr_nonentry_block(i32 %arg0) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index 8e7181a0cf4495..251aeed9194378 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -4211,20 +4211,20 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1064-NEXT: s_movk_i32 s32, 0x800
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX1064-NEXT: v_mov_b32_e32 v3, 0
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX1064-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064-NEXT: v_mov_b32_e32 v3, 0x7ff80000
; GFX1064-NEXT: s_mov_b64 s[0:1], exec
; GFX1064-NEXT: .LBB7_1: ; %ComputeLoop
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_ff1_i32_b64 s4, s[0:1]
-; GFX1064-NEXT: v_max_f64 v[2:3], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX1064-NEXT: v_readlane_b32 s3, v1, s4
; GFX1064-NEXT: v_readlane_b32 s2, v0, s4
; GFX1064-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1064-NEXT: s_lshl_b64 s[2:3], 1, s4
; GFX1064-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: v_max_f64 v[3:4], v[2:3], v[4:5]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[4:5]
; GFX1064-NEXT: s_cbranch_scc1 .LBB7_1
; GFX1064-NEXT: ; %bb.2: ; %ComputeEnd
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
@@ -4236,26 +4236,26 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1064-NEXT: ; %bb.3:
; GFX1064-NEXT: s_load_dwordx2 s[42:43], s[34:35], 0x24
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: v_max_f64 v[41:42], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[41:42], v[2:3], v[2:3]
; GFX1064-NEXT: s_mov_b64 s[44:45], 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: global_load_dwordx2 v[1:2], v0, s[42:43]
+; GFX1064-NEXT: global_load_dwordx2 v[4:5], v0, s[42:43]
; GFX1064-NEXT: .LBB7_4: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_waitcnt vmcnt(0)
-; GFX1064-NEXT: v_max_f64 v[3:4], v[1:2], v[1:2]
+; GFX1064-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX1064-NEXT: s_add_u32 s8, s34, 44
; GFX1064-NEXT: s_addc_u32 s9, s35, 0
; GFX1064-NEXT: s_getpc_b64 s[0:1]
; GFX1064-NEXT: s_add_u32 s0, s0, __atomic_compare_exchange at gotpcrel32@lo+4
; GFX1064-NEXT: s_addc_u32 s1, s1, __atomic_compare_exchange at gotpcrel32@hi+12
-; GFX1064-NEXT: buffer_store_dword v2, off, s[48:51], 0 offset:4
-; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0
+; GFX1064-NEXT: buffer_store_dword v5, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0
; GFX1064-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX1064-NEXT: v_mov_b32_e32 v31, v40
-; GFX1064-NEXT: v_mov_b32_e32 v0, 8
-; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, s42
+; GFX1064-NEXT: v_mov_b32_e32 v3, s43
+; GFX1064-NEXT: v_mov_b32_e32 v4, 0
; GFX1064-NEXT: v_mov_b32_e32 v5, 8
; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: v_mov_b32_e32 v7, 0
@@ -4266,16 +4266,16 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1064-NEXT: s_mov_b32 s13, s40
; GFX1064-NEXT: s_mov_b32 s14, s33
; GFX1064-NEXT: s_mov_b64 s[2:3], s[50:51]
-; GFX1064-NEXT: v_max_f64 v[3:4], v[3:4], v[41:42]
-; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0 offset:12
-; GFX1064-NEXT: buffer_store_dword v3, off, s[48:51], 0 offset:8
-; GFX1064-NEXT: v_mov_b32_e32 v3, s43
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0
+; GFX1064-NEXT: v_max_f64 v[0:1], v[0:1], v[41:42]
+; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0 offset:12
+; GFX1064-NEXT: buffer_store_dword v0, off, s[48:51], 0 offset:8
+; GFX1064-NEXT: v_mov_b32_e32 v0, 8
+; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: buffer_load_dword v1, off, s[48:51], 0
-; GFX1064-NEXT: buffer_load_dword v2, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_load_dword v4, off, s[48:51], 0
+; GFX1064-NEXT: buffer_load_dword v5, off, s[48:51], 0 offset:4
; GFX1064-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX1064-NEXT: s_or_b64 s[44:45], vcc, s[44:45]
@@ -7696,20 +7696,20 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1064-NEXT: s_movk_i32 s32, 0x800
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX1064-NEXT: v_mov_b32_e32 v3, 0
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX1064-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064-NEXT: v_mov_b32_e32 v3, 0x7ff80000
; GFX1064-NEXT: s_mov_b64 s[0:1], exec
; GFX1064-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_ff1_i32_b64 s4, s[0:1]
-; GFX1064-NEXT: v_max_f64 v[2:3], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX1064-NEXT: v_readlane_b32 s3, v1, s4
; GFX1064-NEXT: v_readlane_b32 s2, v0, s4
; GFX1064-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1064-NEXT: s_lshl_b64 s[2:3], 1, s4
; GFX1064-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: v_max_f64 v[3:4], v[2:3], v[4:5]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[4:5]
; GFX1064-NEXT: s_cbranch_scc1 .LBB11_1
; GFX1064-NEXT: ; %bb.2: ; %ComputeEnd
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
@@ -7721,26 +7721,26 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1064-NEXT: ; %bb.3:
; GFX1064-NEXT: s_load_dwordx2 s[42:43], s[34:35], 0x24
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: v_max_f64 v[41:42], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[41:42], v[2:3], v[2:3]
; GFX1064-NEXT: s_mov_b64 s[44:45], 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: global_load_dwordx2 v[1:2], v0, s[42:43]
+; GFX1064-NEXT: global_load_dwordx2 v[4:5], v0, s[42:43]
; GFX1064-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_waitcnt vmcnt(0)
-; GFX1064-NEXT: v_max_f64 v[3:4], v[1:2], v[1:2]
+; GFX1064-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX1064-NEXT: s_add_u32 s8, s34, 44
; GFX1064-NEXT: s_addc_u32 s9, s35, 0
; GFX1064-NEXT: s_getpc_b64 s[0:1]
; GFX1064-NEXT: s_add_u32 s0, s0, __atomic_compare_exchange at gotpcrel32@lo+4
; GFX1064-NEXT: s_addc_u32 s1, s1, __atomic_compare_exchange at gotpcrel32@hi+12
-; GFX1064-NEXT: buffer_store_dword v2, off, s[48:51], 0 offset:4
-; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0
+; GFX1064-NEXT: buffer_store_dword v5, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0
; GFX1064-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX1064-NEXT: v_mov_b32_e32 v31, v40
-; GFX1064-NEXT: v_mov_b32_e32 v0, 8
-; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, s42
+; GFX1064-NEXT: v_mov_b32_e32 v3, s43
+; GFX1064-NEXT: v_mov_b32_e32 v4, 0
; GFX1064-NEXT: v_mov_b32_e32 v5, 8
; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: v_mov_b32_e32 v7, 0
@@ -7751,16 +7751,16 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1064-NEXT: s_mov_b32 s13, s40
; GFX1064-NEXT: s_mov_b32 s14, s33
; GFX1064-NEXT: s_mov_b64 s[2:3], s[50:51]
-; GFX1064-NEXT: v_max_f64 v[3:4], v[3:4], v[41:42]
-; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0 offset:12
-; GFX1064-NEXT: buffer_store_dword v3, off, s[48:51], 0 offset:8
-; GFX1064-NEXT: v_mov_b32_e32 v3, s43
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0
+; GFX1064-NEXT: v_max_f64 v[0:1], v[0:1], v[41:42]
+; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0 offset:12
+; GFX1064-NEXT: buffer_store_dword v0, off, s[48:51], 0 offset:8
+; GFX1064-NEXT: v_mov_b32_e32 v0, 8
+; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: buffer_load_dword v1, off, s[48:51], 0
-; GFX1064-NEXT: buffer_load_dword v2, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_load_dword v4, off, s[48:51], 0
+; GFX1064-NEXT: buffer_load_dword v5, off, s[48:51], 0 offset:4
; GFX1064-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX1064-NEXT: s_or_b64 s[44:45], vcc, s[44:45]
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index b95b52168625dd..22ed5ab78884f8 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -4211,20 +4211,20 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1064-NEXT: s_movk_i32 s32, 0x800
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX1064-NEXT: v_mov_b32_e32 v3, 0
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX1064-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064-NEXT: v_mov_b32_e32 v3, 0x7ff80000
; GFX1064-NEXT: s_mov_b64 s[0:1], exec
; GFX1064-NEXT: .LBB7_1: ; %ComputeLoop
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_ff1_i32_b64 s4, s[0:1]
-; GFX1064-NEXT: v_max_f64 v[2:3], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX1064-NEXT: v_readlane_b32 s3, v1, s4
; GFX1064-NEXT: v_readlane_b32 s2, v0, s4
; GFX1064-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1064-NEXT: s_lshl_b64 s[2:3], 1, s4
; GFX1064-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: v_min_f64 v[3:4], v[2:3], v[4:5]
+; GFX1064-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
; GFX1064-NEXT: s_cbranch_scc1 .LBB7_1
; GFX1064-NEXT: ; %bb.2: ; %ComputeEnd
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
@@ -4236,26 +4236,26 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1064-NEXT: ; %bb.3:
; GFX1064-NEXT: s_load_dwordx2 s[42:43], s[34:35], 0x24
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: v_max_f64 v[41:42], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[41:42], v[2:3], v[2:3]
; GFX1064-NEXT: s_mov_b64 s[44:45], 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: global_load_dwordx2 v[1:2], v0, s[42:43]
+; GFX1064-NEXT: global_load_dwordx2 v[4:5], v0, s[42:43]
; GFX1064-NEXT: .LBB7_4: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_waitcnt vmcnt(0)
-; GFX1064-NEXT: v_max_f64 v[3:4], v[1:2], v[1:2]
+; GFX1064-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX1064-NEXT: s_add_u32 s8, s34, 44
; GFX1064-NEXT: s_addc_u32 s9, s35, 0
; GFX1064-NEXT: s_getpc_b64 s[0:1]
; GFX1064-NEXT: s_add_u32 s0, s0, __atomic_compare_exchange at gotpcrel32@lo+4
; GFX1064-NEXT: s_addc_u32 s1, s1, __atomic_compare_exchange at gotpcrel32@hi+12
-; GFX1064-NEXT: buffer_store_dword v2, off, s[48:51], 0 offset:4
-; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0
+; GFX1064-NEXT: buffer_store_dword v5, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0
; GFX1064-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX1064-NEXT: v_mov_b32_e32 v31, v40
-; GFX1064-NEXT: v_mov_b32_e32 v0, 8
-; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, s42
+; GFX1064-NEXT: v_mov_b32_e32 v3, s43
+; GFX1064-NEXT: v_mov_b32_e32 v4, 0
; GFX1064-NEXT: v_mov_b32_e32 v5, 8
; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: v_mov_b32_e32 v7, 0
@@ -4266,16 +4266,16 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1064-NEXT: s_mov_b32 s13, s40
; GFX1064-NEXT: s_mov_b32 s14, s33
; GFX1064-NEXT: s_mov_b64 s[2:3], s[50:51]
-; GFX1064-NEXT: v_min_f64 v[3:4], v[3:4], v[41:42]
-; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0 offset:12
-; GFX1064-NEXT: buffer_store_dword v3, off, s[48:51], 0 offset:8
-; GFX1064-NEXT: v_mov_b32_e32 v3, s43
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0
+; GFX1064-NEXT: v_min_f64 v[0:1], v[0:1], v[41:42]
+; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0 offset:12
+; GFX1064-NEXT: buffer_store_dword v0, off, s[48:51], 0 offset:8
+; GFX1064-NEXT: v_mov_b32_e32 v0, 8
+; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: buffer_load_dword v1, off, s[48:51], 0
-; GFX1064-NEXT: buffer_load_dword v2, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_load_dword v4, off, s[48:51], 0
+; GFX1064-NEXT: buffer_load_dword v5, off, s[48:51], 0 offset:4
; GFX1064-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX1064-NEXT: s_or_b64 s[44:45], vcc, s[44:45]
@@ -7696,20 +7696,20 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1064-NEXT: s_movk_i32 s32, 0x800
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
-; GFX1064-NEXT: v_mov_b32_e32 v3, 0
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0x7ff80000
+; GFX1064-NEXT: v_mov_b32_e32 v2, 0
+; GFX1064-NEXT: v_mov_b32_e32 v3, 0x7ff80000
; GFX1064-NEXT: s_mov_b64 s[0:1], exec
; GFX1064-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_ff1_i32_b64 s4, s[0:1]
-; GFX1064-NEXT: v_max_f64 v[2:3], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
; GFX1064-NEXT: v_readlane_b32 s3, v1, s4
; GFX1064-NEXT: v_readlane_b32 s2, v0, s4
; GFX1064-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1064-NEXT: s_lshl_b64 s[2:3], 1, s4
; GFX1064-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: v_min_f64 v[3:4], v[2:3], v[4:5]
+; GFX1064-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
; GFX1064-NEXT: s_cbranch_scc1 .LBB11_1
; GFX1064-NEXT: ; %bb.2: ; %ComputeEnd
; GFX1064-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
@@ -7721,26 +7721,26 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1064-NEXT: ; %bb.3:
; GFX1064-NEXT: s_load_dwordx2 s[42:43], s[34:35], 0x24
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: v_max_f64 v[41:42], v[3:4], v[3:4]
+; GFX1064-NEXT: v_max_f64 v[41:42], v[2:3], v[2:3]
; GFX1064-NEXT: s_mov_b64 s[44:45], 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: global_load_dwordx2 v[1:2], v0, s[42:43]
+; GFX1064-NEXT: global_load_dwordx2 v[4:5], v0, s[42:43]
; GFX1064-NEXT: .LBB11_4: ; %atomicrmw.start
; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1064-NEXT: s_waitcnt vmcnt(0)
-; GFX1064-NEXT: v_max_f64 v[3:4], v[1:2], v[1:2]
+; GFX1064-NEXT: v_max_f64 v[0:1], v[4:5], v[4:5]
; GFX1064-NEXT: s_add_u32 s8, s34, 44
; GFX1064-NEXT: s_addc_u32 s9, s35, 0
; GFX1064-NEXT: s_getpc_b64 s[0:1]
; GFX1064-NEXT: s_add_u32 s0, s0, __atomic_compare_exchange at gotpcrel32@lo+4
; GFX1064-NEXT: s_addc_u32 s1, s1, __atomic_compare_exchange at gotpcrel32@hi+12
-; GFX1064-NEXT: buffer_store_dword v2, off, s[48:51], 0 offset:4
-; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0
+; GFX1064-NEXT: buffer_store_dword v5, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0
; GFX1064-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; GFX1064-NEXT: v_mov_b32_e32 v31, v40
-; GFX1064-NEXT: v_mov_b32_e32 v0, 8
-; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: v_mov_b32_e32 v2, s42
+; GFX1064-NEXT: v_mov_b32_e32 v3, s43
+; GFX1064-NEXT: v_mov_b32_e32 v4, 0
; GFX1064-NEXT: v_mov_b32_e32 v5, 8
; GFX1064-NEXT: v_mov_b32_e32 v6, 0
; GFX1064-NEXT: v_mov_b32_e32 v7, 0
@@ -7751,16 +7751,16 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1064-NEXT: s_mov_b32 s13, s40
; GFX1064-NEXT: s_mov_b32 s14, s33
; GFX1064-NEXT: s_mov_b64 s[2:3], s[50:51]
-; GFX1064-NEXT: v_min_f64 v[3:4], v[3:4], v[41:42]
-; GFX1064-NEXT: buffer_store_dword v4, off, s[48:51], 0 offset:12
-; GFX1064-NEXT: buffer_store_dword v3, off, s[48:51], 0 offset:8
-; GFX1064-NEXT: v_mov_b32_e32 v3, s43
-; GFX1064-NEXT: v_mov_b32_e32 v4, 0
+; GFX1064-NEXT: v_min_f64 v[0:1], v[0:1], v[41:42]
+; GFX1064-NEXT: buffer_store_dword v1, off, s[48:51], 0 offset:12
+; GFX1064-NEXT: buffer_store_dword v0, off, s[48:51], 0 offset:8
+; GFX1064-NEXT: v_mov_b32_e32 v0, 8
+; GFX1064-NEXT: v_mov_b32_e32 v1, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[6:7]
; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: buffer_load_dword v1, off, s[48:51], 0
-; GFX1064-NEXT: buffer_load_dword v2, off, s[48:51], 0 offset:4
+; GFX1064-NEXT: buffer_load_dword v4, off, s[48:51], 0
+; GFX1064-NEXT: buffer_load_dword v5, off, s[48:51], 0 offset:4
; GFX1064-NEXT: v_and_b32_e32 v0, 1, v0
; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX1064-NEXT: s_or_b64 s[44:45], vcc, s[44:45]
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index ea18e0d9eeefbd..fee881d78c4d32 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -949,6 +949,7 @@ entry:
ret void
}
+; FIXME: Fold out s_or_b32 s2, 0, s3
define amdgpu_kernel void @bit4_inselt(ptr addrspace(1) %out, <4 x i1> %vec, i32 %sel) {
; GCN-LABEL: bit4_inselt:
; GCN: ; %bb.0: ; %entry
@@ -961,21 +962,20 @@ define amdgpu_kernel void @bit4_inselt(ptr addrspace(1) %out, <4 x i1> %vec, i32
; GCN-NEXT: s_addc_u32 s13, s13, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bfe_u32 s6, s2, 0x10003
-; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: s_bfe_u32 s5, s2, 0x20002
-; GCN-NEXT: buffer_store_byte v1, off, s[12:15], 0
-; GCN-NEXT: v_mov_b32_e32 v1, s6
+; GCN-NEXT: buffer_store_byte v0, off, s[12:15], 0
+; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GCN-NEXT: buffer_store_byte v1, off, s[12:15], 0 offset:3
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:3
+; GCN-NEXT: v_mov_b32_e32 v0, s5
; GCN-NEXT: s_and_b32 s3, s3, 3
-; GCN-NEXT: buffer_store_byte v1, off, s[12:15], 0 offset:2
-; GCN-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NEXT: v_or_b32_e32 v0, s3, v0
-; GCN-NEXT: buffer_store_byte v1, off, s[12:15], 0 offset:1
-; GCN-NEXT: v_mov_b32_e32 v1, 1
-; GCN-NEXT: buffer_store_byte v1, v0, s[12:15], 0 offen
+; GCN-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:2
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_or_b32_e64 v1, s3, 0
+; GCN-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:1
+; GCN-NEXT: v_mov_b32_e32 v0, 1
+; GCN-NEXT: buffer_store_byte v0, v1, s[12:15], 0 offen
; GCN-NEXT: buffer_load_ubyte v0, off, s[12:15], 0
; GCN-NEXT: buffer_load_ubyte v1, off, s[12:15], 0 offset:1
; GCN-NEXT: buffer_load_ubyte v2, off, s[12:15], 0 offset:2
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
index f9f343268105ed..1d698655bac0ff 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
@@ -14,9 +14,6 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
; CHECK-NEXT: s_add_u32 s0, s0, s15
; CHECK-NEXT: s_addc_u32 s1, s1, 0
; CHECK-NEXT: s_mov_b64 s[10:11], s[8:9]
-; CHECK-NEXT: v_mov_b32_e32 v3, v2
-; CHECK-NEXT: v_mov_b32_e32 v2, v1
-; CHECK-NEXT: v_mov_b32_e32 v1, v0
; CHECK-NEXT: s_load_dword s8, s[6:7], 0x0
; CHECK-NEXT: ; implicit-def: $vgpr40 : SGPR spill to VGPR lane
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
@@ -35,8 +32,8 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
; CHECK-NEXT: s_addc_u32 s6, s6, s7
; CHECK-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9
; CHECK-NEXT: s_mov_b32 s9, s6
-; CHECK-NEXT: v_mov_b32_e32 v0, 0x2000
-; CHECK-NEXT: ; implicit-def: $sgpr6
+; CHECK-NEXT: s_mov_b32 s6, 0x2000
+; CHECK-NEXT: s_mov_b32 s18, s6
; CHECK-NEXT: s_getpc_b64 s[6:7]
; CHECK-NEXT: s_add_u32 s6, s6, device_func at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s7, s7, device_func at gotpcrel32@hi+12
@@ -44,14 +41,15 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
; CHECK-NEXT: s_mov_b32 s6, 20
-; CHECK-NEXT: v_lshlrev_b32_e64 v3, s6, v3
-; CHECK-NEXT: s_mov_b32 s6, 10
; CHECK-NEXT: v_lshlrev_b32_e64 v2, s6, v2
-; CHECK-NEXT: v_or3_b32 v31, v1, v2, v3
+; CHECK-NEXT: s_mov_b32 s6, 10
+; CHECK-NEXT: v_lshlrev_b32_e64 v1, s6, v1
+; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2
; CHECK-NEXT: ; implicit-def: $sgpr6_sgpr7
; CHECK-NEXT: ; implicit-def: $sgpr15
; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
+; CHECK-NEXT: v_mov_b32_e32 v0, s18
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: s_add_i32 s4, s33, 0x100100
diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
index 7698372b687797..da98eb40a129dd 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -38,7 +38,7 @@
; GCNHSA: .amdhsa_system_sgpr_workgroup_id_z 1
; GCNHSA: .amdhsa_system_sgpr_workgroup_info 0
; GCNHSA: .amdhsa_system_vgpr_workitem_id 2
-; GCNHSA: .amdhsa_next_free_vgpr 3
+; GCNHSA: .amdhsa_next_free_vgpr {{2|3}}
; GCNHSA: .amdhsa_next_free_sgpr 18
; GCNHSA: .amdhsa_float_round_mode_32 0
; GCNHSA: .amdhsa_float_round_mode_16_64 0
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
index 904fb974e3d700..f4a0eb39d8aa3d 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
@@ -20,25 +20,24 @@ define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) {
; MUBUF-LABEL: local_stack_offset_uses_sp:
; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_add_u32 s0, s0, s15
-; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
-; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1
-; MUBUF-NEXT: v_mov_b32_e32 v2, 0
-; MUBUF-NEXT: v_mov_b32_e32 v3, 0x2000
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0x3040
+; MUBUF-NEXT: v_mov_b32_e32 v1, 0
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x2000
; MUBUF-NEXT: s_mov_b32 s4, 0
-; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: .LBB0_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
-; MUBUF-NEXT: v_add_u32_e32 v3, s4, v1
+; MUBUF-NEXT: v_mov_b32_e32 v3, 0x3000
+; MUBUF-NEXT: v_add_u32_e32 v2, s4, v3
; MUBUF-NEXT: s_add_i32 s4, s4, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120
-; MUBUF-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_store_byte v1, v2, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 .LBB0_1
; MUBUF-NEXT: ; %bb.2: ; %split
-; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
-; MUBUF-NEXT: v_add_u32_e32 v1, 0x20d0, v1
+; MUBUF-NEXT: v_mov_b32_e32 v1, 0x50d0
; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v3, v1, s[0:3], 0 offen offset:4 glc
@@ -111,26 +110,27 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) {
; MUBUF-NEXT: s_add_i32 s33, s32, 0x7ffc0
; MUBUF-NEXT: s_and_b32 s33, s33, 0xfff80000
; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
-; MUBUF-NEXT: v_add_u32_e32 v3, 0x3000, v3
-; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3
-; MUBUF-NEXT: v_mov_b32_e32 v4, 0
-; MUBUF-NEXT: v_mov_b32_e32 v5, 0x2000
+; MUBUF-NEXT: v_add_u32_e32 v2, 0x3040, v3
+; MUBUF-NEXT: v_mov_b32_e32 v3, 0
+; MUBUF-NEXT: v_mov_b32_e32 v4, 0x2000
; MUBUF-NEXT: s_mov_b32 s4, 0
; MUBUF-NEXT: s_add_i32 s32, s32, 0x200000
-; MUBUF-NEXT: buffer_store_dword v4, v5, s[0:3], s33 offen
+; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], s33 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: .LBB1_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
-; MUBUF-NEXT: v_add_u32_e32 v5, s4, v3
+; MUBUF-NEXT: v_lshrrev_b32_e64 v5, 6, s33
+; MUBUF-NEXT: v_add_u32_e32 v4, s4, v5
+; MUBUF-NEXT: v_mov_b32_e32 v5, 0x3000
; MUBUF-NEXT: s_add_i32 s4, s4, 1
+; MUBUF-NEXT: v_add_u32_e32 v4, v5, v4
; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120
-; MUBUF-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_store_byte v3, v4, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 .LBB1_1
; MUBUF-NEXT: ; %bb.2: ; %split
-; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
-; MUBUF-NEXT: v_add_u32_e32 v3, 0x3000, v3
-; MUBUF-NEXT: v_add_u32_e32 v3, 0x20d0, v3
+; MUBUF-NEXT: v_lshrrev_b32_e64 v4, 6, s33
+; MUBUF-NEXT: v_add_u32_e32 v3, 0x50d0, v4
; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v5, v3, s[0:3], 0 offen offset:4 glc
@@ -203,41 +203,51 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
; MUBUF: ; %bb.0: ; %entry
; MUBUF-NEXT: s_add_u32 s0, s0, s15
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000
-; MUBUF-NEXT: v_mov_b32_e32 v1, 0
-; MUBUF-NEXT: v_mov_b32_e32 v2, 0x2000
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
+; MUBUF-NEXT: v_mov_b32_e32 v1, 0x2000
; MUBUF-NEXT: s_mov_b32 s4, 0
-; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: .LBB2_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
-; MUBUF-NEXT: v_add_u32_e32 v2, s4, v0
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
+; MUBUF-NEXT: v_add_u32_e32 v1, s4, v2
; MUBUF-NEXT: s_add_i32 s4, s4, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120
-; MUBUF-NEXT: buffer_store_byte v1, v2, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_store_byte v0, v1, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 .LBB2_1
; MUBUF-NEXT: ; %bb.2: ; %split
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0x4000
-; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d4, v0
-; MUBUF-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen glc
+; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000
+; MUBUF-NEXT: s_movk_i32 s4, 0x12d4
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
+; MUBUF-NEXT: v_or_b32_e32 v0, 0x12c0, v1
+; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2
+; MUBUF-NEXT: s_movk_i32 s4, 0x12d0
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
+; MUBUF-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: v_or_b32_e32 v2, 0x12d0, v0
-; MUBUF-NEXT: v_or_b32_e32 v1, 0x12c0, v0
-; MUBUF-NEXT: buffer_load_dword v4, v2, s[0:3], 0 offen glc
+; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2
+; MUBUF-NEXT: s_movk_i32 s4, 0x12c4
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
+; MUBUF-NEXT: buffer_load_dword v4, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: v_or_b32_e32 v2, 0x12c4, v0
-; MUBUF-NEXT: buffer_load_dword v6, v2, s[0:3], 0 offen glc
+; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2
+; MUBUF-NEXT: buffer_load_dword v6, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: buffer_load_dword v7, v1, s[0:3], 0 offen glc
+; MUBUF-NEXT: buffer_load_dword v7, v0, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: v_or_b32_e32 v1, 0x12cc, v0
-; MUBUF-NEXT: v_or_b32_e32 v0, 0x12c8, v0
+; MUBUF-NEXT: s_movk_i32 s4, 0x12cc
+; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000
+; MUBUF-NEXT: v_or_b32_e32 v0, s4, v1
+; MUBUF-NEXT: s_movk_i32 s4, 0x12c8
; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
-; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen glc
+; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2
+; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000
+; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_mov_b32_e32 v3, 0x4000
-; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc
+; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_mov_b32_e32 v10, 0x4000
; MUBUF-NEXT: buffer_load_dword v8, v2, s[0:3], 0 offen glc
@@ -254,10 +264,10 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
; MUBUF-NEXT: buffer_load_dword v10, v11, s[0:3], 0 offen offset:16 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
+; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v1, v2
; MUBUF-NEXT: buffer_load_dword v11, v12, s[0:3], 0 offen offset:20 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
-; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
+; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v3, vcc
; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v7, v8
; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v9, vcc
; MUBUF-NEXT: v_add_co_u32_e32 v4, vcc, v4, v10
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
index 302b140e32f3aa..feeeb8f07c24ef 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
@@ -1423,26 +1423,25 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX10_1-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_store_dword v2, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v3, 5, s32
-; GFX10_1-NEXT: v_writelane_b32 v2, s59, 0
+; GFX10_1-NEXT: v_writelane_b32 v1, s59, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_1-NEXT: s_add_i32 s59, s4, 0x442c
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 0x442c, v3
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use alloca0 v0
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readfirstlane_b32 s59, v1
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s59, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s59, v2, 0
+; GFX10_1-NEXT: v_readlane_b32 s59, v1, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_load_dword v2, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -1453,25 +1452,24 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX10_3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_store_dword v2, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v3, 5, s32
-; GFX10_3-NEXT: v_writelane_b32 v2, s59, 0
+; GFX10_3-NEXT: v_writelane_b32 v1, s59, 0
; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_3-NEXT: s_add_i32 s59, s4, 0x442c
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 0x442c, v3
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use alloca0 v0
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readfirstlane_b32 s59, v1
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s59, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s59, v2, 0
+; GFX10_3-NEXT: v_readlane_b32 s59, v1, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_load_dword v2, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_3-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: s_waitcnt vmcnt(0)
; GFX10_3-NEXT: s_setpc_b64 s[30:31]
@@ -1481,25 +1479,23 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX11-NEXT: scratch_store_b32 off, v2, s1 ; 4-byte Folded Spill
+; GFX11-NEXT: scratch_store_b32 off, v1, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v1, s59, 0
; GFX11-NEXT: s_add_i32 s0, s32, 64
-; GFX11-NEXT: v_writelane_b32 v2, s59, 0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s32
+; GFX11-NEXT: s_add_i32 s59, s32, 0x442c
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use alloca0 v0
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x442c, v3
-; GFX11-NEXT: v_readfirstlane_b32 s59, v1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s59, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readlane_b32 s59, v2, 0
+; GFX11-NEXT: v_readlane_b32 s59, v1, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX11-NEXT: scratch_load_b32 v2, off, s1 ; 4-byte Folded Reload
+; GFX11-NEXT: scratch_load_b32 v1, off, s1 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1512,24 +1508,22 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX12-NEXT: scratch_store_b32 off, v2, s32 offset:32768 ; 4-byte Folded Spill
+; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:32768 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_dual_mov_b32 v0, s32 :: v_dual_mov_b32 v3, s32
-; GFX12-NEXT: v_writelane_b32 v2, s59, 0
+; GFX12-NEXT: v_writelane_b32 v1, s59, 0
+; GFX12-NEXT: s_add_co_i32 s59, s32, 0x43ec
+; GFX12-NEXT: v_mov_b32_e32 v0, s32
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_add_nc_u32_e32 v1, 0x43ec, v3
-; GFX12-NEXT: v_readfirstlane_b32 s59, v1
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s59, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_readlane_b32 s59, v2, 0
+; GFX12-NEXT: v_readlane_b32 s59, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX12-NEXT: scratch_load_b32 v2, off, s32 offset:32768 ; 4-byte Folded Reload
+; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:32768 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1541,25 +1535,24 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s6 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x442c, v1
-; GFX8-NEXT: v_writelane_b32 v2, s59, 0
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX8-NEXT: v_readfirstlane_b32 s59, v0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, 64, v1
+; GFX8-NEXT: s_lshr_b32 s4, s32, 6
+; GFX8-NEXT: v_writelane_b32 v1, s59, 0
+; GFX8-NEXT: s_add_i32 s59, s4, 0x442c
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: ;;#ASMSTART
-; GFX8-NEXT: ; use alloca0 v1
+; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s59, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s59, v2, 0
+; GFX8-NEXT: v_readlane_b32 s59, v1, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s6 ; 4-byte Folded Reload
+; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -1569,26 +1562,24 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s6 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
+; GFX900-NEXT: s_lshr_b32 s4, s32, 6
+; GFX900-NEXT: v_writelane_b32 v1, s59, 0
+; GFX900-NEXT: s_add_i32 s59, s4, 0x442c
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
-; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0
-; GFX900-NEXT: v_add_u32_e32 v0, 0x3ec, v0
-; GFX900-NEXT: v_writelane_b32 v2, s59, 0
-; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX900-NEXT: v_readfirstlane_b32 s59, v0
-; GFX900-NEXT: v_add_u32_e32 v1, 64, v1
+; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use alloca0 v1
+; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s59, scc
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_readlane_b32 s59, v2, 0
+; GFX900-NEXT: v_readlane_b32 s59, v1, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s6 ; 4-byte Folded Reload
+; GFX900-NEXT: buffer_load_dword v1, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1598,26 +1589,23 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX940-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX940-NEXT: scratch_store_dword off, v2, s2 sc0 sc1 ; 4-byte Folded Spill
+; GFX940-NEXT: scratch_store_dword off, v1, s2 sc0 sc1 ; 4-byte Folded Spill
; GFX940-NEXT: s_mov_b64 exec, s[0:1]
-; GFX940-NEXT: s_add_i32 s0, s32, 0x4040
-; GFX940-NEXT: v_mov_b32_e32 v0, s0
-; GFX940-NEXT: v_add_u32_e32 v0, 0x3ec, v0
-; GFX940-NEXT: v_writelane_b32 v2, s59, 0
+; GFX940-NEXT: v_writelane_b32 v1, s59, 0
+; GFX940-NEXT: s_add_i32 s59, s32, 0x442c
; GFX940-NEXT: s_add_i32 s0, s32, 64
-; GFX940-NEXT: v_readfirstlane_b32 s59, v0
-; GFX940-NEXT: v_mov_b32_e32 v1, s0
+; GFX940-NEXT: v_mov_b32_e32 v0, s0
; GFX940-NEXT: ;;#ASMSTART
-; GFX940-NEXT: ; use alloca0 v1
+; GFX940-NEXT: ; use alloca0 v0
; GFX940-NEXT: ;;#ASMEND
; GFX940-NEXT: s_and_b64 s[0:1], 0, exec
; GFX940-NEXT: ;;#ASMSTART
; GFX940-NEXT: ; use s59, scc
; GFX940-NEXT: ;;#ASMEND
-; GFX940-NEXT: v_readlane_b32 s59, v2, 0
+; GFX940-NEXT: v_readlane_b32 s59, v1, 0
; GFX940-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX940-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX940-NEXT: scratch_load_dword v2, off, s2 ; 4-byte Folded Reload
+; GFX940-NEXT: scratch_load_dword v1, off, s2 ; 4-byte Folded Reload
; GFX940-NEXT: s_mov_b64 exec, s[0:1]
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
@@ -1635,28 +1623,27 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX10_1-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_store_dword v2, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v3, 5, s32
-; GFX10_1-NEXT: s_lshl_b32 s4, s6, 2
-; GFX10_1-NEXT: v_writelane_b32 v2, s59, 0
+; GFX10_1-NEXT: v_writelane_b32 v1, s59, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_1-NEXT: v_add_nc_u32_e32 v1, s4, v3
-; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_1-NEXT: s_lshl_b32 s4, s6, 2
+; GFX10_1-NEXT: s_lshr_b32 s59, s32, 5
+; GFX10_1-NEXT: s_add_i32 s59, s59, s4
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_1-NEXT: s_addk_i32 s59, 0x4040
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use alloca0 v0
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 0x4040, v1
-; GFX10_1-NEXT: v_readfirstlane_b32 s59, v1
+; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s59, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s59, v2, 0
+; GFX10_1-NEXT: v_readlane_b32 s59, v1, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_load_dword v2, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -1667,27 +1654,26 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX10_3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_store_dword v2, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v3, 5, s32
-; GFX10_3-NEXT: s_lshl_b32 s4, s6, 2
-; GFX10_3-NEXT: v_writelane_b32 v2, s59, 0
+; GFX10_3-NEXT: v_writelane_b32 v1, s59, 0
; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_3-NEXT: v_add_nc_u32_e32 v1, s4, v3
-; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_3-NEXT: s_lshl_b32 s4, s6, 2
+; GFX10_3-NEXT: s_lshr_b32 s59, s32, 5
+; GFX10_3-NEXT: s_add_i32 s59, s59, s4
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_3-NEXT: s_addk_i32 s59, 0x4040
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use alloca0 v0
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 0x4040, v1
-; GFX10_3-NEXT: v_readfirstlane_b32 s59, v1
+; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s59, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s59, v2, 0
+; GFX10_3-NEXT: v_readlane_b32 s59, v1, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_load_dword v2, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_3-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: s_waitcnt vmcnt(0)
; GFX10_3-NEXT: s_setpc_b64 s[30:31]
@@ -1697,27 +1683,25 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s1, -1
; GFX11-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX11-NEXT: scratch_store_b32 off, v2, s2 ; 4-byte Folded Spill
+; GFX11-NEXT: scratch_store_b32 off, v1, s2 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-NEXT: s_add_i32 s1, s32, 64
-; GFX11-NEXT: v_add_nc_u32_e64 v1, s0, s32
+; GFX11-NEXT: v_writelane_b32 v1, s59, 0
+; GFX11-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-NEXT: v_mov_b32_e32 v0, s1
-; GFX11-NEXT: v_writelane_b32 v2, s59, 0
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x4040, v1
+; GFX11-NEXT: s_add_i32 s59, s32, s0
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use alloca0 v0
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readfirstlane_b32 s59, v1
+; GFX11-NEXT: s_addk_i32 s59, 0x4040
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s59, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readlane_b32 s59, v2, 0
+; GFX11-NEXT: v_readlane_b32 s59, v1, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX11-NEXT: scratch_load_b32 v2, off, s1 ; 4-byte Folded Reload
+; GFX11-NEXT: scratch_load_b32 v1, off, s1 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1730,27 +1714,26 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s1, -1
-; GFX12-NEXT: scratch_store_b32 off, v2, s32 offset:32768 ; 4-byte Folded Spill
+; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:32768 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s1
+; GFX12-NEXT: v_writelane_b32 v1, s59, 0
; GFX12-NEXT: s_lshl_b32 s0, s0, 2
-; GFX12-NEXT: v_writelane_b32 v2, s59, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_add_nc_u32_e64 v1, s0, s32
; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_add_nc_u32_e32 v1, 0x4000, v1
+; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_add_co_i32 s59, s32, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_readfirstlane_b32 s59, v1
+; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_addk_co_i32 s59, 0x4000
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s59, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_readlane_b32 s59, v2, 0
+; GFX12-NEXT: v_readlane_b32 s59, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX12-NEXT: scratch_load_b32 v2, off, s32 offset:32768 ; 4-byte Folded Reload
+; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:32768 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1762,28 +1745,26 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s7, s32, 0x201000
-; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s7 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
-; GFX8-NEXT: s_movk_i32 vcc_lo, 0x4040
+; GFX8-NEXT: v_writelane_b32 v1, s59, 0
; GFX8-NEXT: s_lshl_b32 s4, s6, 2
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, vcc_lo, v0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v0
-; GFX8-NEXT: v_writelane_b32 v2, s59, 0
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX8-NEXT: v_readfirstlane_b32 s59, v0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, 64, v1
+; GFX8-NEXT: s_lshr_b32 s59, s32, 6
+; GFX8-NEXT: s_add_i32 s59, s59, s4
+; GFX8-NEXT: s_addk_i32 s59, 0x4040
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: ;;#ASMSTART
-; GFX8-NEXT: ; use alloca0 v1
+; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s59, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s59, v2, 0
+; GFX8-NEXT: v_readlane_b32 s59, v1, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s6 ; 4-byte Folded Reload
+; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -1793,27 +1774,26 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s7, s32, 0x201000
-; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s7 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; GFX900-NEXT: v_writelane_b32 v1, s59, 0
; GFX900-NEXT: s_lshl_b32 s4, s6, 2
-; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0
-; GFX900-NEXT: v_add_u32_e32 v0, s4, v0
-; GFX900-NEXT: v_writelane_b32 v2, s59, 0
-; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX900-NEXT: v_readfirstlane_b32 s59, v0
-; GFX900-NEXT: v_add_u32_e32 v1, 64, v1
+; GFX900-NEXT: s_lshr_b32 s59, s32, 6
+; GFX900-NEXT: s_add_i32 s59, s59, s4
+; GFX900-NEXT: s_addk_i32 s59, 0x4040
+; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use alloca0 v1
+; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s59, scc
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_readlane_b32 s59, v2, 0
+; GFX900-NEXT: v_readlane_b32 s59, v1, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x201000
-; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s6 ; 4-byte Folded Reload
+; GFX900-NEXT: buffer_load_dword v1, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1823,27 +1803,25 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT: s_xor_saveexec_b64 s[2:3], -1
; GFX940-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX940-NEXT: scratch_store_dword off, v2, s1 sc0 sc1 ; 4-byte Folded Spill
+; GFX940-NEXT: scratch_store_dword off, v1, s1 sc0 sc1 ; 4-byte Folded Spill
; GFX940-NEXT: s_mov_b64 exec, s[2:3]
; GFX940-NEXT: s_lshl_b32 s0, s0, 2
-; GFX940-NEXT: s_add_i32 s1, s32, 0x4040
-; GFX940-NEXT: v_mov_b32_e32 v0, s1
-; GFX940-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX940-NEXT: v_writelane_b32 v2, s59, 0
+; GFX940-NEXT: v_writelane_b32 v1, s59, 0
+; GFX940-NEXT: s_add_i32 s59, s32, s0
+; GFX940-NEXT: s_addk_i32 s59, 0x4040
; GFX940-NEXT: s_add_i32 s0, s32, 64
-; GFX940-NEXT: v_readfirstlane_b32 s59, v0
-; GFX940-NEXT: v_mov_b32_e32 v1, s0
+; GFX940-NEXT: v_mov_b32_e32 v0, s0
; GFX940-NEXT: ;;#ASMSTART
-; GFX940-NEXT: ; use alloca0 v1
+; GFX940-NEXT: ; use alloca0 v0
; GFX940-NEXT: ;;#ASMEND
; GFX940-NEXT: s_and_b64 s[0:1], 0, exec
; GFX940-NEXT: ;;#ASMSTART
; GFX940-NEXT: ; use s59, scc
; GFX940-NEXT: ;;#ASMEND
-; GFX940-NEXT: v_readlane_b32 s59, v2, 0
+; GFX940-NEXT: v_readlane_b32 s59, v1, 0
; GFX940-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX940-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX940-NEXT: scratch_load_dword v2, off, s2 ; 4-byte Folded Reload
+; GFX940-NEXT: scratch_load_dword v1, off, s2 ; 4-byte Folded Reload
; GFX940-NEXT: s_mov_b64 exec, s[0:1]
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index 308411fa225dae..d4110850f32066 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -1520,9 +1520,9 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX7-NEXT: s_add_i32 s6, s32, 0x202000
+; GFX7-NEXT: s_add_i32 s6, s32, 0x201000
; GFX7-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill
-; GFX7-NEXT: s_add_i32 s6, s32, 0x202100
+; GFX7-NEXT: s_add_i32 s6, s32, 0x201100
; GFX7-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
; GFX7-NEXT: v_writelane_b32 v23, s28, 28
@@ -1552,66 +1552,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: v_writelane_b32 v23, s53, 22
; GFX7-NEXT: v_writelane_b32 v23, s54, 23
; GFX7-NEXT: v_writelane_b32 v23, s55, 24
-; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
+; GFX7-NEXT: s_lshr_b32 s5, s32, 6
; GFX7-NEXT: v_writelane_b32 v23, s56, 25
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
+; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
+; GFX7-NEXT: s_add_i32 s4, s5, 0x4240
+; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; GFX7-NEXT: v_writelane_b32 v23, s57, 26
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
+; GFX7-NEXT: v_writelane_b32 v22, s4, 0
+; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
+; GFX7-NEXT: v_writelane_b32 v23, s59, 27
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX7-NEXT: ;;#ASMEND
-; GFX7-NEXT: buffer_store_dword v16, off, s[0:3], s32
-; GFX7-NEXT: v_mov_b32_e32 v16, 0x8040
-; GFX7-NEXT: buffer_store_dword v0, v16, s[0:3], s32 offen ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v1, v16, s[0:3], s32 offen offset:4 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v2, v16, s[0:3], s32 offen offset:8 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v3, v16, s[0:3], s32 offen offset:12 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v4, v16, s[0:3], s32 offen offset:16 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v5, v16, s[0:3], s32 offen offset:20 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v6, v16, s[0:3], s32 offen offset:24 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v7, v16, s[0:3], s32 offen offset:28 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v8, v16, s[0:3], s32 offen offset:32 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v9, v16, s[0:3], s32 offen offset:36 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v10, v16, s[0:3], s32 offen offset:40 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v11, v16, s[0:3], s32 offen offset:44 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v12, v16, s[0:3], s32 offen offset:48 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v13, v16, s[0:3], s32 offen offset:52 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v14, v16, s[0:3], s32 offen offset:56 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_store_dword v15, v16, s[0:3], s32 offen offset:60 ; 4-byte Folded Spill
-; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32
-; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX7-NEXT: v_lshr_b32_e64 v1, s32, 6
-; GFX7-NEXT: v_writelane_b32 v22, vcc_lo, 0
-; GFX7-NEXT: v_writelane_b32 v22, vcc_hi, 1
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0x4240, v1
-; GFX7-NEXT: v_writelane_b32 v23, s59, 27
-; GFX7-NEXT: v_readfirstlane_b32 s59, v0
-; GFX7-NEXT: s_and_b64 vcc, 0, exec
-; GFX7-NEXT: v_readlane_b32 vcc_lo, v22, 0
-; GFX7-NEXT: v_readlane_b32 vcc_hi, v22, 1
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: buffer_store_dword v16, off, s[0:3], s32
-; GFX7-NEXT: v_mov_b32_e32 v16, 0x8040
-; GFX7-NEXT: buffer_load_dword v0, v16, s[0:3], s32 offen ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v1, v16, s[0:3], s32 offen offset:4 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v2, v16, s[0:3], s32 offen offset:8 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v3, v16, s[0:3], s32 offen offset:12 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v4, v16, s[0:3], s32 offen offset:16 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v5, v16, s[0:3], s32 offen offset:20 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v6, v16, s[0:3], s32 offen offset:24 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v7, v16, s[0:3], s32 offen offset:28 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v8, v16, s[0:3], s32 offen offset:32 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v9, v16, s[0:3], s32 offen offset:36 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v10, v16, s[0:3], s32 offen offset:40 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v11, v16, s[0:3], s32 offen offset:44 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v12, v16, s[0:3], s32 offen offset:48 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v13, v16, s[0:3], s32 offen offset:52 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v14, v16, s[0:3], s32 offen offset:56 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v15, v16, s[0:3], s32 offen offset:60 ; 4-byte Folded Reload
-; GFX7-NEXT: buffer_load_dword v16, off, s[0:3], s32
-; GFX7-NEXT: s_waitcnt vmcnt(0)
+; GFX7-NEXT: v_readlane_b32 s59, v22, 0
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX7-NEXT: ;;#ASMEND
@@ -1646,9 +1603,9 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: v_readlane_b32 s28, v23, 28
; GFX7-NEXT: v_readlane_b32 s29, v23, 29
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX7-NEXT: s_add_i32 s6, s32, 0x202000
+; GFX7-NEXT: s_add_i32 s6, s32, 0x201000
; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
-; GFX7-NEXT: s_add_i32 s6, s32, 0x202100
+; GFX7-NEXT: s_add_i32 s6, s32, 0x201100
; GFX7-NEXT: buffer_load_dword v22, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
; GFX7-NEXT: s_waitcnt vmcnt(0)
@@ -1658,137 +1615,81 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX8-NEXT: s_add_i32 s6, s32, 0x202000
-; GFX8-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill
-; GFX8-NEXT: s_add_i32 s6, s32, 0x202100
+; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
; GFX8-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_writelane_b32 v23, s58, 28
-; GFX8-NEXT: v_writelane_b32 v23, s59, 29
-; GFX8-NEXT: v_writelane_b32 v23, s30, 0
-; GFX8-NEXT: v_writelane_b32 v23, s31, 1
-; GFX8-NEXT: v_writelane_b32 v23, s33, 2
-; GFX8-NEXT: v_writelane_b32 v23, s34, 3
-; GFX8-NEXT: v_writelane_b32 v23, s35, 4
-; GFX8-NEXT: v_writelane_b32 v23, s36, 5
-; GFX8-NEXT: v_writelane_b32 v23, s37, 6
-; GFX8-NEXT: v_writelane_b32 v23, s38, 7
-; GFX8-NEXT: v_writelane_b32 v23, s39, 8
-; GFX8-NEXT: v_writelane_b32 v23, s40, 9
-; GFX8-NEXT: v_writelane_b32 v23, s41, 10
-; GFX8-NEXT: v_writelane_b32 v23, s42, 11
-; GFX8-NEXT: v_writelane_b32 v23, s43, 12
-; GFX8-NEXT: v_writelane_b32 v23, s44, 13
-; GFX8-NEXT: v_writelane_b32 v23, s45, 14
-; GFX8-NEXT: v_writelane_b32 v23, s46, 15
-; GFX8-NEXT: v_writelane_b32 v23, s47, 16
-; GFX8-NEXT: v_writelane_b32 v23, s48, 17
-; GFX8-NEXT: v_writelane_b32 v23, s49, 18
-; GFX8-NEXT: v_writelane_b32 v23, s50, 19
-; GFX8-NEXT: v_writelane_b32 v23, s51, 20
-; GFX8-NEXT: v_writelane_b32 v23, s52, 21
-; GFX8-NEXT: v_writelane_b32 v23, s53, 22
-; GFX8-NEXT: v_writelane_b32 v23, s54, 23
-; GFX8-NEXT: v_writelane_b32 v23, s55, 24
+; GFX8-NEXT: v_writelane_b32 v22, s30, 0
+; GFX8-NEXT: v_writelane_b32 v22, s31, 1
+; GFX8-NEXT: v_writelane_b32 v22, s33, 2
+; GFX8-NEXT: v_writelane_b32 v22, s34, 3
+; GFX8-NEXT: v_writelane_b32 v22, s35, 4
+; GFX8-NEXT: v_writelane_b32 v22, s36, 5
+; GFX8-NEXT: v_writelane_b32 v22, s37, 6
+; GFX8-NEXT: v_writelane_b32 v22, s38, 7
+; GFX8-NEXT: v_writelane_b32 v22, s39, 8
+; GFX8-NEXT: v_writelane_b32 v22, s40, 9
+; GFX8-NEXT: v_writelane_b32 v22, s41, 10
+; GFX8-NEXT: v_writelane_b32 v22, s42, 11
+; GFX8-NEXT: v_writelane_b32 v22, s43, 12
+; GFX8-NEXT: v_writelane_b32 v22, s44, 13
+; GFX8-NEXT: v_writelane_b32 v22, s45, 14
+; GFX8-NEXT: v_writelane_b32 v22, s46, 15
+; GFX8-NEXT: v_writelane_b32 v22, s47, 16
+; GFX8-NEXT: v_writelane_b32 v22, s48, 17
+; GFX8-NEXT: v_writelane_b32 v22, s49, 18
+; GFX8-NEXT: v_writelane_b32 v22, s50, 19
+; GFX8-NEXT: v_writelane_b32 v22, s51, 20
+; GFX8-NEXT: v_writelane_b32 v22, s52, 21
+; GFX8-NEXT: v_writelane_b32 v22, s53, 22
+; GFX8-NEXT: v_writelane_b32 v22, s54, 23
+; GFX8-NEXT: v_writelane_b32 v22, s55, 24
+; GFX8-NEXT: v_writelane_b32 v22, s56, 25
+; GFX8-NEXT: v_writelane_b32 v22, s57, 26
+; GFX8-NEXT: s_lshr_b32 s4, s32, 6
+; GFX8-NEXT: v_writelane_b32 v22, s59, 27
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
-; GFX8-NEXT: v_writelane_b32 v23, s56, 25
+; GFX8-NEXT: s_add_i32 s59, s4, 0x4240
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
-; GFX8-NEXT: v_writelane_b32 v23, s57, 26
+; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: buffer_store_dword v16, off, s[0:3], s32
-; GFX8-NEXT: v_mov_b32_e32 v16, 0x8040
-; GFX8-NEXT: buffer_store_dword v0, v16, s[0:3], s32 offen ; 4-byte Folded Spill
-; GFX8-NEXT: s_nop 0
-; GFX8-NEXT: buffer_store_dword v1, v16, s[0:3], s32 offen offset:4 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v2, v16, s[0:3], s32 offen offset:8 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v3, v16, s[0:3], s32 offen offset:12 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v4, v16, s[0:3], s32 offen offset:16 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v5, v16, s[0:3], s32 offen offset:20 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v6, v16, s[0:3], s32 offen offset:24 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v7, v16, s[0:3], s32 offen offset:28 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v8, v16, s[0:3], s32 offen offset:32 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v9, v16, s[0:3], s32 offen offset:36 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v10, v16, s[0:3], s32 offen offset:40 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v11, v16, s[0:3], s32 offen offset:44 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v12, v16, s[0:3], s32 offen offset:48 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v13, v16, s[0:3], s32 offen offset:52 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v14, v16, s[0:3], s32 offen offset:56 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v15, v16, s[0:3], s32 offen offset:60 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32
-; GFX8-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s32
-; GFX8-NEXT: v_writelane_b32 v22, vcc_lo, 0
-; GFX8-NEXT: v_writelane_b32 v22, vcc_hi, 1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x4240, v1
-; GFX8-NEXT: v_writelane_b32 v23, s59, 27
-; GFX8-NEXT: v_readfirstlane_b32 s59, v0
-; GFX8-NEXT: s_and_b64 vcc, 0, exec
-; GFX8-NEXT: v_readlane_b32 vcc_lo, v22, 0
-; GFX8-NEXT: v_readlane_b32 vcc_hi, v22, 1
-; GFX8-NEXT: v_readlane_b32 s58, v23, 28
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: buffer_store_dword v16, off, s[0:3], s32
-; GFX8-NEXT: v_mov_b32_e32 v16, 0x8040
-; GFX8-NEXT: buffer_load_dword v0, v16, s[0:3], s32 offen ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v1, v16, s[0:3], s32 offen offset:4 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v2, v16, s[0:3], s32 offen offset:8 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v3, v16, s[0:3], s32 offen offset:12 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v4, v16, s[0:3], s32 offen offset:16 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v5, v16, s[0:3], s32 offen offset:20 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v6, v16, s[0:3], s32 offen offset:24 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v7, v16, s[0:3], s32 offen offset:28 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v8, v16, s[0:3], s32 offen offset:32 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v9, v16, s[0:3], s32 offen offset:36 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v10, v16, s[0:3], s32 offen offset:40 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v11, v16, s[0:3], s32 offen offset:44 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v12, v16, s[0:3], s32 offen offset:48 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v13, v16, s[0:3], s32 offen offset:52 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v14, v16, s[0:3], s32 offen offset:56 ; 4-byte Folded Reload
-; GFX8-NEXT: buffer_load_dword v15, v16, s[0:3], s32 offen offset:60 ; 4-byte Folded Reload
-; GFX8-NEXT: s_nop 0
-; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32
-; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s59, v23, 27
-; GFX8-NEXT: v_readlane_b32 s57, v23, 26
-; GFX8-NEXT: v_readlane_b32 s56, v23, 25
-; GFX8-NEXT: v_readlane_b32 s55, v23, 24
-; GFX8-NEXT: v_readlane_b32 s54, v23, 23
-; GFX8-NEXT: v_readlane_b32 s53, v23, 22
-; GFX8-NEXT: v_readlane_b32 s52, v23, 21
-; GFX8-NEXT: v_readlane_b32 s51, v23, 20
-; GFX8-NEXT: v_readlane_b32 s50, v23, 19
-; GFX8-NEXT: v_readlane_b32 s49, v23, 18
-; GFX8-NEXT: v_readlane_b32 s48, v23, 17
-; GFX8-NEXT: v_readlane_b32 s47, v23, 16
-; GFX8-NEXT: v_readlane_b32 s46, v23, 15
-; GFX8-NEXT: v_readlane_b32 s45, v23, 14
-; GFX8-NEXT: v_readlane_b32 s44, v23, 13
-; GFX8-NEXT: v_readlane_b32 s43, v23, 12
-; GFX8-NEXT: v_readlane_b32 s42, v23, 11
-; GFX8-NEXT: v_readlane_b32 s41, v23, 10
-; GFX8-NEXT: v_readlane_b32 s40, v23, 9
-; GFX8-NEXT: v_readlane_b32 s39, v23, 8
-; GFX8-NEXT: v_readlane_b32 s38, v23, 7
-; GFX8-NEXT: v_readlane_b32 s37, v23, 6
-; GFX8-NEXT: v_readlane_b32 s36, v23, 5
-; GFX8-NEXT: v_readlane_b32 s35, v23, 4
-; GFX8-NEXT: v_readlane_b32 s34, v23, 3
-; GFX8-NEXT: v_readlane_b32 s33, v23, 2
-; GFX8-NEXT: v_readlane_b32 s31, v23, 1
-; GFX8-NEXT: v_readlane_b32 s30, v23, 0
-; GFX8-NEXT: v_readlane_b32 s59, v23, 29
+; GFX8-NEXT: v_readlane_b32 s59, v22, 27
+; GFX8-NEXT: v_readlane_b32 s57, v22, 26
+; GFX8-NEXT: v_readlane_b32 s56, v22, 25
+; GFX8-NEXT: v_readlane_b32 s55, v22, 24
+; GFX8-NEXT: v_readlane_b32 s54, v22, 23
+; GFX8-NEXT: v_readlane_b32 s53, v22, 22
+; GFX8-NEXT: v_readlane_b32 s52, v22, 21
+; GFX8-NEXT: v_readlane_b32 s51, v22, 20
+; GFX8-NEXT: v_readlane_b32 s50, v22, 19
+; GFX8-NEXT: v_readlane_b32 s49, v22, 18
+; GFX8-NEXT: v_readlane_b32 s48, v22, 17
+; GFX8-NEXT: v_readlane_b32 s47, v22, 16
+; GFX8-NEXT: v_readlane_b32 s46, v22, 15
+; GFX8-NEXT: v_readlane_b32 s45, v22, 14
+; GFX8-NEXT: v_readlane_b32 s44, v22, 13
+; GFX8-NEXT: v_readlane_b32 s43, v22, 12
+; GFX8-NEXT: v_readlane_b32 s42, v22, 11
+; GFX8-NEXT: v_readlane_b32 s41, v22, 10
+; GFX8-NEXT: v_readlane_b32 s40, v22, 9
+; GFX8-NEXT: v_readlane_b32 s39, v22, 8
+; GFX8-NEXT: v_readlane_b32 s38, v22, 7
+; GFX8-NEXT: v_readlane_b32 s37, v22, 6
+; GFX8-NEXT: v_readlane_b32 s36, v22, 5
+; GFX8-NEXT: v_readlane_b32 s35, v22, 4
+; GFX8-NEXT: v_readlane_b32 s34, v22, 3
+; GFX8-NEXT: v_readlane_b32 s33, v22, 2
+; GFX8-NEXT: v_readlane_b32 s31, v22, 1
+; GFX8-NEXT: v_readlane_b32 s30, v22, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX8-NEXT: s_add_i32 s6, s32, 0x202000
-; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
-; GFX8-NEXT: s_add_i32 s6, s32, 0x202100
+; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -1824,21 +1725,19 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX900-NEXT: v_writelane_b32 v22, s51, 20
; GFX900-NEXT: v_writelane_b32 v22, s52, 21
; GFX900-NEXT: v_writelane_b32 v22, s53, 22
-; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_writelane_b32 v22, s54, 23
-; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: v_writelane_b32 v22, s55, 24
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use alloca0 v0
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_writelane_b32 v22, s56, 25
-; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0
; GFX900-NEXT: v_writelane_b32 v22, s57, 26
-; GFX900-NEXT: v_add_u32_e32 v0, 0x200, v0
-; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
+; GFX900-NEXT: s_lshr_b32 s4, s32, 6
; GFX900-NEXT: v_writelane_b32 v22, s59, 27
-; GFX900-NEXT: v_readfirstlane_b32 s59, v0
+; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; GFX900-NEXT: s_add_i32 s59, s4, 0x4240
+; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
+; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
+; GFX900-NEXT: ;;#ASMSTART
+; GFX900-NEXT: ; use alloca0 v0
+; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX900-NEXT: ;;#ASMEND
@@ -1885,87 +1784,84 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX940-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX940-NEXT: scratch_store_dword off, v23, s2 sc0 sc1 ; 4-byte Folded Spill
+; GFX940-NEXT: scratch_store_dword off, v22, s2 sc0 sc1 ; 4-byte Folded Spill
; GFX940-NEXT: s_mov_b64 exec, s[0:1]
-; GFX940-NEXT: v_writelane_b32 v23, s30, 0
-; GFX940-NEXT: v_writelane_b32 v23, s31, 1
-; GFX940-NEXT: v_writelane_b32 v23, s33, 2
-; GFX940-NEXT: v_writelane_b32 v23, s34, 3
-; GFX940-NEXT: v_writelane_b32 v23, s35, 4
-; GFX940-NEXT: v_writelane_b32 v23, s36, 5
-; GFX940-NEXT: v_writelane_b32 v23, s37, 6
-; GFX940-NEXT: v_writelane_b32 v23, s38, 7
-; GFX940-NEXT: v_writelane_b32 v23, s39, 8
-; GFX940-NEXT: v_writelane_b32 v23, s40, 9
-; GFX940-NEXT: v_writelane_b32 v23, s41, 10
-; GFX940-NEXT: v_writelane_b32 v23, s42, 11
-; GFX940-NEXT: v_writelane_b32 v23, s43, 12
-; GFX940-NEXT: v_writelane_b32 v23, s44, 13
-; GFX940-NEXT: v_writelane_b32 v23, s45, 14
-; GFX940-NEXT: v_writelane_b32 v23, s46, 15
-; GFX940-NEXT: v_writelane_b32 v23, s47, 16
-; GFX940-NEXT: v_writelane_b32 v23, s48, 17
-; GFX940-NEXT: v_writelane_b32 v23, s49, 18
-; GFX940-NEXT: v_writelane_b32 v23, s50, 19
-; GFX940-NEXT: v_writelane_b32 v23, s51, 20
-; GFX940-NEXT: v_writelane_b32 v23, s52, 21
-; GFX940-NEXT: v_writelane_b32 v23, s53, 22
-; GFX940-NEXT: v_writelane_b32 v23, s54, 23
-; GFX940-NEXT: v_writelane_b32 v23, s55, 24
-; GFX940-NEXT: v_writelane_b32 v23, s56, 25
+; GFX940-NEXT: v_writelane_b32 v22, s30, 0
+; GFX940-NEXT: v_writelane_b32 v22, s31, 1
+; GFX940-NEXT: v_writelane_b32 v22, s33, 2
+; GFX940-NEXT: v_writelane_b32 v22, s34, 3
+; GFX940-NEXT: v_writelane_b32 v22, s35, 4
+; GFX940-NEXT: v_writelane_b32 v22, s36, 5
+; GFX940-NEXT: v_writelane_b32 v22, s37, 6
+; GFX940-NEXT: v_writelane_b32 v22, s38, 7
+; GFX940-NEXT: v_writelane_b32 v22, s39, 8
+; GFX940-NEXT: v_writelane_b32 v22, s40, 9
+; GFX940-NEXT: v_writelane_b32 v22, s41, 10
+; GFX940-NEXT: v_writelane_b32 v22, s42, 11
+; GFX940-NEXT: v_writelane_b32 v22, s43, 12
+; GFX940-NEXT: v_writelane_b32 v22, s44, 13
+; GFX940-NEXT: v_writelane_b32 v22, s45, 14
+; GFX940-NEXT: v_writelane_b32 v22, s46, 15
+; GFX940-NEXT: v_writelane_b32 v22, s47, 16
+; GFX940-NEXT: v_writelane_b32 v22, s48, 17
+; GFX940-NEXT: v_writelane_b32 v22, s49, 18
+; GFX940-NEXT: v_writelane_b32 v22, s50, 19
+; GFX940-NEXT: v_writelane_b32 v22, s51, 20
+; GFX940-NEXT: v_writelane_b32 v22, s52, 21
+; GFX940-NEXT: v_writelane_b32 v22, s53, 22
+; GFX940-NEXT: v_writelane_b32 v22, s54, 23
+; GFX940-NEXT: v_writelane_b32 v22, s55, 24
+; GFX940-NEXT: v_writelane_b32 v22, s56, 25
+; GFX940-NEXT: v_writelane_b32 v22, s57, 26
; GFX940-NEXT: s_add_i32 s0, s32, 64
-; GFX940-NEXT: v_writelane_b32 v23, s57, 26
+; GFX940-NEXT: v_writelane_b32 v22, s59, 27
; GFX940-NEXT: v_mov_b32_e32 v0, s0
-; GFX940-NEXT: v_writelane_b32 v23, s59, 27
+; GFX940-NEXT: v_writelane_b32 v22, s60, 28
; GFX940-NEXT: ;;#ASMSTART
; GFX940-NEXT: ; use alloca0 v0
; GFX940-NEXT: ;;#ASMEND
; GFX940-NEXT: ;;#ASMSTART
; GFX940-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX940-NEXT: ;;#ASMEND
-; GFX940-NEXT: s_add_i32 s59, s32, 0x4040
-; GFX940-NEXT: v_mov_b32_e32 v22, s59
-; GFX940-NEXT: v_writelane_b32 v23, s60, 28
-; GFX940-NEXT: v_add_u32_e32 v22, 0x200, v22
-; GFX940-NEXT: v_writelane_b32 v23, s61, 29
-; GFX940-NEXT: v_readfirstlane_b32 s59, v22
+; GFX940-NEXT: s_add_i32 s59, s32, 0x4240
+; GFX940-NEXT: v_writelane_b32 v22, s61, 29
; GFX940-NEXT: s_and_b64 s[60:61], 0, exec
; GFX940-NEXT: ;;#ASMSTART
; GFX940-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX940-NEXT: ;;#ASMEND
-; GFX940-NEXT: v_readlane_b32 s61, v23, 29
-; GFX940-NEXT: v_readlane_b32 s60, v23, 28
-; GFX940-NEXT: v_readlane_b32 s59, v23, 27
-; GFX940-NEXT: v_readlane_b32 s57, v23, 26
-; GFX940-NEXT: v_readlane_b32 s56, v23, 25
-; GFX940-NEXT: v_readlane_b32 s55, v23, 24
-; GFX940-NEXT: v_readlane_b32 s54, v23, 23
-; GFX940-NEXT: v_readlane_b32 s53, v23, 22
-; GFX940-NEXT: v_readlane_b32 s52, v23, 21
-; GFX940-NEXT: v_readlane_b32 s51, v23, 20
-; GFX940-NEXT: v_readlane_b32 s50, v23, 19
-; GFX940-NEXT: v_readlane_b32 s49, v23, 18
-; GFX940-NEXT: v_readlane_b32 s48, v23, 17
-; GFX940-NEXT: v_readlane_b32 s47, v23, 16
-; GFX940-NEXT: v_readlane_b32 s46, v23, 15
-; GFX940-NEXT: v_readlane_b32 s45, v23, 14
-; GFX940-NEXT: v_readlane_b32 s44, v23, 13
-; GFX940-NEXT: v_readlane_b32 s43, v23, 12
-; GFX940-NEXT: v_readlane_b32 s42, v23, 11
-; GFX940-NEXT: v_readlane_b32 s41, v23, 10
-; GFX940-NEXT: v_readlane_b32 s40, v23, 9
-; GFX940-NEXT: v_readlane_b32 s39, v23, 8
-; GFX940-NEXT: v_readlane_b32 s38, v23, 7
-; GFX940-NEXT: v_readlane_b32 s37, v23, 6
-; GFX940-NEXT: v_readlane_b32 s36, v23, 5
-; GFX940-NEXT: v_readlane_b32 s35, v23, 4
-; GFX940-NEXT: v_readlane_b32 s34, v23, 3
-; GFX940-NEXT: v_readlane_b32 s33, v23, 2
-; GFX940-NEXT: v_readlane_b32 s31, v23, 1
-; GFX940-NEXT: v_readlane_b32 s30, v23, 0
+; GFX940-NEXT: v_readlane_b32 s61, v22, 29
+; GFX940-NEXT: v_readlane_b32 s60, v22, 28
+; GFX940-NEXT: v_readlane_b32 s59, v22, 27
+; GFX940-NEXT: v_readlane_b32 s57, v22, 26
+; GFX940-NEXT: v_readlane_b32 s56, v22, 25
+; GFX940-NEXT: v_readlane_b32 s55, v22, 24
+; GFX940-NEXT: v_readlane_b32 s54, v22, 23
+; GFX940-NEXT: v_readlane_b32 s53, v22, 22
+; GFX940-NEXT: v_readlane_b32 s52, v22, 21
+; GFX940-NEXT: v_readlane_b32 s51, v22, 20
+; GFX940-NEXT: v_readlane_b32 s50, v22, 19
+; GFX940-NEXT: v_readlane_b32 s49, v22, 18
+; GFX940-NEXT: v_readlane_b32 s48, v22, 17
+; GFX940-NEXT: v_readlane_b32 s47, v22, 16
+; GFX940-NEXT: v_readlane_b32 s46, v22, 15
+; GFX940-NEXT: v_readlane_b32 s45, v22, 14
+; GFX940-NEXT: v_readlane_b32 s44, v22, 13
+; GFX940-NEXT: v_readlane_b32 s43, v22, 12
+; GFX940-NEXT: v_readlane_b32 s42, v22, 11
+; GFX940-NEXT: v_readlane_b32 s41, v22, 10
+; GFX940-NEXT: v_readlane_b32 s40, v22, 9
+; GFX940-NEXT: v_readlane_b32 s39, v22, 8
+; GFX940-NEXT: v_readlane_b32 s38, v22, 7
+; GFX940-NEXT: v_readlane_b32 s37, v22, 6
+; GFX940-NEXT: v_readlane_b32 s36, v22, 5
+; GFX940-NEXT: v_readlane_b32 s35, v22, 4
+; GFX940-NEXT: v_readlane_b32 s34, v22, 3
+; GFX940-NEXT: v_readlane_b32 s33, v22, 2
+; GFX940-NEXT: v_readlane_b32 s31, v22, 1
+; GFX940-NEXT: v_readlane_b32 s30, v22, 0
; GFX940-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX940-NEXT: s_add_i32 s2, s32, 0x8040
-; GFX940-NEXT: scratch_load_dword v23, off, s2 ; 4-byte Folded Reload
+; GFX940-NEXT: scratch_load_dword v22, off, s2 ; 4-byte Folded Reload
; GFX940-NEXT: s_mov_b64 exec, s[0:1]
; GFX940-NEXT: s_waitcnt vmcnt(0)
; GFX940-NEXT: s_setpc_b64 s[30:31]
@@ -1975,83 +1871,82 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_1-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_writelane_b32 v23, s30, 0
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32
+; GFX10_1-NEXT: v_writelane_b32 v22, s30, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_1-NEXT: v_writelane_b32 v23, s31, 1
-; GFX10_1-NEXT: v_add_nc_u32_e32 v22, 0x4240, v1
+; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_1-NEXT: v_writelane_b32 v22, s31, 1
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use alloca0 v0
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_writelane_b32 v23, s33, 2
-; GFX10_1-NEXT: v_writelane_b32 v23, s34, 3
-; GFX10_1-NEXT: v_writelane_b32 v23, s35, 4
-; GFX10_1-NEXT: v_writelane_b32 v23, s36, 5
-; GFX10_1-NEXT: v_writelane_b32 v23, s37, 6
-; GFX10_1-NEXT: v_writelane_b32 v23, s38, 7
-; GFX10_1-NEXT: v_writelane_b32 v23, s39, 8
-; GFX10_1-NEXT: v_writelane_b32 v23, s40, 9
-; GFX10_1-NEXT: v_writelane_b32 v23, s41, 10
-; GFX10_1-NEXT: v_writelane_b32 v23, s42, 11
-; GFX10_1-NEXT: v_writelane_b32 v23, s43, 12
-; GFX10_1-NEXT: v_writelane_b32 v23, s44, 13
-; GFX10_1-NEXT: v_writelane_b32 v23, s45, 14
-; GFX10_1-NEXT: v_writelane_b32 v23, s46, 15
-; GFX10_1-NEXT: v_writelane_b32 v23, s47, 16
-; GFX10_1-NEXT: v_writelane_b32 v23, s48, 17
-; GFX10_1-NEXT: v_writelane_b32 v23, s49, 18
-; GFX10_1-NEXT: v_writelane_b32 v23, s50, 19
-; GFX10_1-NEXT: v_writelane_b32 v23, s51, 20
-; GFX10_1-NEXT: v_writelane_b32 v23, s52, 21
-; GFX10_1-NEXT: v_writelane_b32 v23, s53, 22
-; GFX10_1-NEXT: v_writelane_b32 v23, s54, 23
-; GFX10_1-NEXT: v_writelane_b32 v23, s55, 24
-; GFX10_1-NEXT: v_writelane_b32 v23, s56, 25
-; GFX10_1-NEXT: v_writelane_b32 v23, s57, 26
+; GFX10_1-NEXT: v_writelane_b32 v22, s33, 2
+; GFX10_1-NEXT: v_writelane_b32 v22, s34, 3
+; GFX10_1-NEXT: v_writelane_b32 v22, s35, 4
+; GFX10_1-NEXT: v_writelane_b32 v22, s36, 5
+; GFX10_1-NEXT: v_writelane_b32 v22, s37, 6
+; GFX10_1-NEXT: v_writelane_b32 v22, s38, 7
+; GFX10_1-NEXT: v_writelane_b32 v22, s39, 8
+; GFX10_1-NEXT: v_writelane_b32 v22, s40, 9
+; GFX10_1-NEXT: v_writelane_b32 v22, s41, 10
+; GFX10_1-NEXT: v_writelane_b32 v22, s42, 11
+; GFX10_1-NEXT: v_writelane_b32 v22, s43, 12
+; GFX10_1-NEXT: v_writelane_b32 v22, s44, 13
+; GFX10_1-NEXT: v_writelane_b32 v22, s45, 14
+; GFX10_1-NEXT: v_writelane_b32 v22, s46, 15
+; GFX10_1-NEXT: v_writelane_b32 v22, s47, 16
+; GFX10_1-NEXT: v_writelane_b32 v22, s48, 17
+; GFX10_1-NEXT: v_writelane_b32 v22, s49, 18
+; GFX10_1-NEXT: v_writelane_b32 v22, s50, 19
+; GFX10_1-NEXT: v_writelane_b32 v22, s51, 20
+; GFX10_1-NEXT: v_writelane_b32 v22, s52, 21
+; GFX10_1-NEXT: v_writelane_b32 v22, s53, 22
+; GFX10_1-NEXT: v_writelane_b32 v22, s54, 23
+; GFX10_1-NEXT: v_writelane_b32 v22, s55, 24
+; GFX10_1-NEXT: v_writelane_b32 v22, s56, 25
+; GFX10_1-NEXT: v_writelane_b32 v22, s57, 26
+; GFX10_1-NEXT: v_writelane_b32 v22, s59, 27
+; GFX10_1-NEXT: s_add_i32 s59, s4, 0x4240
+; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_writelane_b32 v23, s59, 27
-; GFX10_1-NEXT: v_readfirstlane_b32 s59, v22
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s59, v23, 27
-; GFX10_1-NEXT: v_readlane_b32 s57, v23, 26
-; GFX10_1-NEXT: v_readlane_b32 s56, v23, 25
-; GFX10_1-NEXT: v_readlane_b32 s55, v23, 24
-; GFX10_1-NEXT: v_readlane_b32 s54, v23, 23
-; GFX10_1-NEXT: v_readlane_b32 s53, v23, 22
-; GFX10_1-NEXT: v_readlane_b32 s52, v23, 21
-; GFX10_1-NEXT: v_readlane_b32 s51, v23, 20
-; GFX10_1-NEXT: v_readlane_b32 s50, v23, 19
-; GFX10_1-NEXT: v_readlane_b32 s49, v23, 18
-; GFX10_1-NEXT: v_readlane_b32 s48, v23, 17
-; GFX10_1-NEXT: v_readlane_b32 s47, v23, 16
-; GFX10_1-NEXT: v_readlane_b32 s46, v23, 15
-; GFX10_1-NEXT: v_readlane_b32 s45, v23, 14
-; GFX10_1-NEXT: v_readlane_b32 s44, v23, 13
-; GFX10_1-NEXT: v_readlane_b32 s43, v23, 12
-; GFX10_1-NEXT: v_readlane_b32 s42, v23, 11
-; GFX10_1-NEXT: v_readlane_b32 s41, v23, 10
-; GFX10_1-NEXT: v_readlane_b32 s40, v23, 9
-; GFX10_1-NEXT: v_readlane_b32 s39, v23, 8
-; GFX10_1-NEXT: v_readlane_b32 s38, v23, 7
-; GFX10_1-NEXT: v_readlane_b32 s37, v23, 6
-; GFX10_1-NEXT: v_readlane_b32 s36, v23, 5
-; GFX10_1-NEXT: v_readlane_b32 s35, v23, 4
-; GFX10_1-NEXT: v_readlane_b32 s34, v23, 3
-; GFX10_1-NEXT: v_readlane_b32 s33, v23, 2
-; GFX10_1-NEXT: v_readlane_b32 s31, v23, 1
-; GFX10_1-NEXT: v_readlane_b32 s30, v23, 0
+; GFX10_1-NEXT: v_readlane_b32 s59, v22, 27
+; GFX10_1-NEXT: v_readlane_b32 s57, v22, 26
+; GFX10_1-NEXT: v_readlane_b32 s56, v22, 25
+; GFX10_1-NEXT: v_readlane_b32 s55, v22, 24
+; GFX10_1-NEXT: v_readlane_b32 s54, v22, 23
+; GFX10_1-NEXT: v_readlane_b32 s53, v22, 22
+; GFX10_1-NEXT: v_readlane_b32 s52, v22, 21
+; GFX10_1-NEXT: v_readlane_b32 s51, v22, 20
+; GFX10_1-NEXT: v_readlane_b32 s50, v22, 19
+; GFX10_1-NEXT: v_readlane_b32 s49, v22, 18
+; GFX10_1-NEXT: v_readlane_b32 s48, v22, 17
+; GFX10_1-NEXT: v_readlane_b32 s47, v22, 16
+; GFX10_1-NEXT: v_readlane_b32 s46, v22, 15
+; GFX10_1-NEXT: v_readlane_b32 s45, v22, 14
+; GFX10_1-NEXT: v_readlane_b32 s44, v22, 13
+; GFX10_1-NEXT: v_readlane_b32 s43, v22, 12
+; GFX10_1-NEXT: v_readlane_b32 s42, v22, 11
+; GFX10_1-NEXT: v_readlane_b32 s41, v22, 10
+; GFX10_1-NEXT: v_readlane_b32 s40, v22, 9
+; GFX10_1-NEXT: v_readlane_b32 s39, v22, 8
+; GFX10_1-NEXT: v_readlane_b32 s38, v22, 7
+; GFX10_1-NEXT: v_readlane_b32 s37, v22, 6
+; GFX10_1-NEXT: v_readlane_b32 s36, v22, 5
+; GFX10_1-NEXT: v_readlane_b32 s35, v22, 4
+; GFX10_1-NEXT: v_readlane_b32 s34, v22, 3
+; GFX10_1-NEXT: v_readlane_b32 s33, v22, 2
+; GFX10_1-NEXT: v_readlane_b32 s31, v22, 1
+; GFX10_1-NEXT: v_readlane_b32 s30, v22, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_1-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_1-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -2062,82 +1957,81 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
+; GFX10_3-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_writelane_b32 v23, s30, 0
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s32
+; GFX10_3-NEXT: v_writelane_b32 v22, s30, 0
; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_3-NEXT: v_writelane_b32 v23, s31, 1
-; GFX10_3-NEXT: v_add_nc_u32_e32 v22, 0x4240, v1
+; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_3-NEXT: v_writelane_b32 v22, s31, 1
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use alloca0 v0
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_writelane_b32 v23, s33, 2
-; GFX10_3-NEXT: v_writelane_b32 v23, s34, 3
-; GFX10_3-NEXT: v_writelane_b32 v23, s35, 4
-; GFX10_3-NEXT: v_writelane_b32 v23, s36, 5
-; GFX10_3-NEXT: v_writelane_b32 v23, s37, 6
-; GFX10_3-NEXT: v_writelane_b32 v23, s38, 7
-; GFX10_3-NEXT: v_writelane_b32 v23, s39, 8
-; GFX10_3-NEXT: v_writelane_b32 v23, s40, 9
-; GFX10_3-NEXT: v_writelane_b32 v23, s41, 10
-; GFX10_3-NEXT: v_writelane_b32 v23, s42, 11
-; GFX10_3-NEXT: v_writelane_b32 v23, s43, 12
-; GFX10_3-NEXT: v_writelane_b32 v23, s44, 13
-; GFX10_3-NEXT: v_writelane_b32 v23, s45, 14
-; GFX10_3-NEXT: v_writelane_b32 v23, s46, 15
-; GFX10_3-NEXT: v_writelane_b32 v23, s47, 16
-; GFX10_3-NEXT: v_writelane_b32 v23, s48, 17
-; GFX10_3-NEXT: v_writelane_b32 v23, s49, 18
-; GFX10_3-NEXT: v_writelane_b32 v23, s50, 19
-; GFX10_3-NEXT: v_writelane_b32 v23, s51, 20
-; GFX10_3-NEXT: v_writelane_b32 v23, s52, 21
-; GFX10_3-NEXT: v_writelane_b32 v23, s53, 22
-; GFX10_3-NEXT: v_writelane_b32 v23, s54, 23
-; GFX10_3-NEXT: v_writelane_b32 v23, s55, 24
-; GFX10_3-NEXT: v_writelane_b32 v23, s56, 25
-; GFX10_3-NEXT: v_writelane_b32 v23, s57, 26
+; GFX10_3-NEXT: v_writelane_b32 v22, s33, 2
+; GFX10_3-NEXT: v_writelane_b32 v22, s34, 3
+; GFX10_3-NEXT: v_writelane_b32 v22, s35, 4
+; GFX10_3-NEXT: v_writelane_b32 v22, s36, 5
+; GFX10_3-NEXT: v_writelane_b32 v22, s37, 6
+; GFX10_3-NEXT: v_writelane_b32 v22, s38, 7
+; GFX10_3-NEXT: v_writelane_b32 v22, s39, 8
+; GFX10_3-NEXT: v_writelane_b32 v22, s40, 9
+; GFX10_3-NEXT: v_writelane_b32 v22, s41, 10
+; GFX10_3-NEXT: v_writelane_b32 v22, s42, 11
+; GFX10_3-NEXT: v_writelane_b32 v22, s43, 12
+; GFX10_3-NEXT: v_writelane_b32 v22, s44, 13
+; GFX10_3-NEXT: v_writelane_b32 v22, s45, 14
+; GFX10_3-NEXT: v_writelane_b32 v22, s46, 15
+; GFX10_3-NEXT: v_writelane_b32 v22, s47, 16
+; GFX10_3-NEXT: v_writelane_b32 v22, s48, 17
+; GFX10_3-NEXT: v_writelane_b32 v22, s49, 18
+; GFX10_3-NEXT: v_writelane_b32 v22, s50, 19
+; GFX10_3-NEXT: v_writelane_b32 v22, s51, 20
+; GFX10_3-NEXT: v_writelane_b32 v22, s52, 21
+; GFX10_3-NEXT: v_writelane_b32 v22, s53, 22
+; GFX10_3-NEXT: v_writelane_b32 v22, s54, 23
+; GFX10_3-NEXT: v_writelane_b32 v22, s55, 24
+; GFX10_3-NEXT: v_writelane_b32 v22, s56, 25
+; GFX10_3-NEXT: v_writelane_b32 v22, s57, 26
+; GFX10_3-NEXT: v_writelane_b32 v22, s59, 27
+; GFX10_3-NEXT: s_add_i32 s59, s4, 0x4240
+; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_writelane_b32 v23, s59, 27
-; GFX10_3-NEXT: v_readfirstlane_b32 s59, v22
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s59, v23, 27
-; GFX10_3-NEXT: v_readlane_b32 s57, v23, 26
-; GFX10_3-NEXT: v_readlane_b32 s56, v23, 25
-; GFX10_3-NEXT: v_readlane_b32 s55, v23, 24
-; GFX10_3-NEXT: v_readlane_b32 s54, v23, 23
-; GFX10_3-NEXT: v_readlane_b32 s53, v23, 22
-; GFX10_3-NEXT: v_readlane_b32 s52, v23, 21
-; GFX10_3-NEXT: v_readlane_b32 s51, v23, 20
-; GFX10_3-NEXT: v_readlane_b32 s50, v23, 19
-; GFX10_3-NEXT: v_readlane_b32 s49, v23, 18
-; GFX10_3-NEXT: v_readlane_b32 s48, v23, 17
-; GFX10_3-NEXT: v_readlane_b32 s47, v23, 16
-; GFX10_3-NEXT: v_readlane_b32 s46, v23, 15
-; GFX10_3-NEXT: v_readlane_b32 s45, v23, 14
-; GFX10_3-NEXT: v_readlane_b32 s44, v23, 13
-; GFX10_3-NEXT: v_readlane_b32 s43, v23, 12
-; GFX10_3-NEXT: v_readlane_b32 s42, v23, 11
-; GFX10_3-NEXT: v_readlane_b32 s41, v23, 10
-; GFX10_3-NEXT: v_readlane_b32 s40, v23, 9
-; GFX10_3-NEXT: v_readlane_b32 s39, v23, 8
-; GFX10_3-NEXT: v_readlane_b32 s38, v23, 7
-; GFX10_3-NEXT: v_readlane_b32 s37, v23, 6
-; GFX10_3-NEXT: v_readlane_b32 s36, v23, 5
-; GFX10_3-NEXT: v_readlane_b32 s35, v23, 4
-; GFX10_3-NEXT: v_readlane_b32 s34, v23, 3
-; GFX10_3-NEXT: v_readlane_b32 s33, v23, 2
-; GFX10_3-NEXT: v_readlane_b32 s31, v23, 1
-; GFX10_3-NEXT: v_readlane_b32 s30, v23, 0
+; GFX10_3-NEXT: v_readlane_b32 s59, v22, 27
+; GFX10_3-NEXT: v_readlane_b32 s57, v22, 26
+; GFX10_3-NEXT: v_readlane_b32 s56, v22, 25
+; GFX10_3-NEXT: v_readlane_b32 s55, v22, 24
+; GFX10_3-NEXT: v_readlane_b32 s54, v22, 23
+; GFX10_3-NEXT: v_readlane_b32 s53, v22, 22
+; GFX10_3-NEXT: v_readlane_b32 s52, v22, 21
+; GFX10_3-NEXT: v_readlane_b32 s51, v22, 20
+; GFX10_3-NEXT: v_readlane_b32 s50, v22, 19
+; GFX10_3-NEXT: v_readlane_b32 s49, v22, 18
+; GFX10_3-NEXT: v_readlane_b32 s48, v22, 17
+; GFX10_3-NEXT: v_readlane_b32 s47, v22, 16
+; GFX10_3-NEXT: v_readlane_b32 s46, v22, 15
+; GFX10_3-NEXT: v_readlane_b32 s45, v22, 14
+; GFX10_3-NEXT: v_readlane_b32 s44, v22, 13
+; GFX10_3-NEXT: v_readlane_b32 s43, v22, 12
+; GFX10_3-NEXT: v_readlane_b32 s42, v22, 11
+; GFX10_3-NEXT: v_readlane_b32 s41, v22, 10
+; GFX10_3-NEXT: v_readlane_b32 s40, v22, 9
+; GFX10_3-NEXT: v_readlane_b32 s39, v22, 8
+; GFX10_3-NEXT: v_readlane_b32 s38, v22, 7
+; GFX10_3-NEXT: v_readlane_b32 s37, v22, 6
+; GFX10_3-NEXT: v_readlane_b32 s36, v22, 5
+; GFX10_3-NEXT: v_readlane_b32 s35, v22, 4
+; GFX10_3-NEXT: v_readlane_b32 s34, v22, 3
+; GFX10_3-NEXT: v_readlane_b32 s33, v22, 2
+; GFX10_3-NEXT: v_readlane_b32 s31, v22, 1
+; GFX10_3-NEXT: v_readlane_b32 s30, v22, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
-; GFX10_3-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload
+; GFX10_3-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: s_waitcnt vmcnt(0)
; GFX10_3-NEXT: s_setpc_b64 s[30:31]
@@ -2147,83 +2041,81 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX11-NEXT: scratch_store_b32 off, v23, s1 ; 4-byte Folded Spill
+; GFX11-NEXT: scratch_store_b32 off, v22, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: v_writelane_b32 v23, s30, 0
+; GFX11-NEXT: v_writelane_b32 v22, s30, 0
; GFX11-NEXT: s_add_i32 s0, s32, 64
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v1, s32 :: v_dual_mov_b32 v0, s0
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX11-NEXT: v_writelane_b32 v23, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use alloca0 v0
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_add_nc_u32_e32 v22, 0x4240, v1
-; GFX11-NEXT: v_writelane_b32 v23, s33, 2
-; GFX11-NEXT: v_writelane_b32 v23, s34, 3
-; GFX11-NEXT: v_writelane_b32 v23, s35, 4
-; GFX11-NEXT: v_writelane_b32 v23, s36, 5
-; GFX11-NEXT: v_writelane_b32 v23, s37, 6
-; GFX11-NEXT: v_writelane_b32 v23, s38, 7
-; GFX11-NEXT: v_writelane_b32 v23, s39, 8
-; GFX11-NEXT: v_writelane_b32 v23, s40, 9
-; GFX11-NEXT: v_writelane_b32 v23, s41, 10
-; GFX11-NEXT: v_writelane_b32 v23, s42, 11
-; GFX11-NEXT: v_writelane_b32 v23, s43, 12
-; GFX11-NEXT: v_writelane_b32 v23, s44, 13
-; GFX11-NEXT: v_writelane_b32 v23, s45, 14
-; GFX11-NEXT: v_writelane_b32 v23, s46, 15
-; GFX11-NEXT: v_writelane_b32 v23, s47, 16
-; GFX11-NEXT: v_writelane_b32 v23, s48, 17
-; GFX11-NEXT: v_writelane_b32 v23, s49, 18
-; GFX11-NEXT: v_writelane_b32 v23, s50, 19
-; GFX11-NEXT: v_writelane_b32 v23, s51, 20
-; GFX11-NEXT: v_writelane_b32 v23, s52, 21
-; GFX11-NEXT: v_writelane_b32 v23, s53, 22
-; GFX11-NEXT: v_writelane_b32 v23, s54, 23
-; GFX11-NEXT: v_writelane_b32 v23, s55, 24
-; GFX11-NEXT: v_writelane_b32 v23, s56, 25
-; GFX11-NEXT: v_writelane_b32 v23, s57, 26
+; GFX11-NEXT: v_writelane_b32 v22, s31, 1
+; GFX11-NEXT: v_writelane_b32 v22, s33, 2
+; GFX11-NEXT: v_writelane_b32 v22, s34, 3
+; GFX11-NEXT: v_writelane_b32 v22, s35, 4
+; GFX11-NEXT: v_writelane_b32 v22, s36, 5
+; GFX11-NEXT: v_writelane_b32 v22, s37, 6
+; GFX11-NEXT: v_writelane_b32 v22, s38, 7
+; GFX11-NEXT: v_writelane_b32 v22, s39, 8
+; GFX11-NEXT: v_writelane_b32 v22, s40, 9
+; GFX11-NEXT: v_writelane_b32 v22, s41, 10
+; GFX11-NEXT: v_writelane_b32 v22, s42, 11
+; GFX11-NEXT: v_writelane_b32 v22, s43, 12
+; GFX11-NEXT: v_writelane_b32 v22, s44, 13
+; GFX11-NEXT: v_writelane_b32 v22, s45, 14
+; GFX11-NEXT: v_writelane_b32 v22, s46, 15
+; GFX11-NEXT: v_writelane_b32 v22, s47, 16
+; GFX11-NEXT: v_writelane_b32 v22, s48, 17
+; GFX11-NEXT: v_writelane_b32 v22, s49, 18
+; GFX11-NEXT: v_writelane_b32 v22, s50, 19
+; GFX11-NEXT: v_writelane_b32 v22, s51, 20
+; GFX11-NEXT: v_writelane_b32 v22, s52, 21
+; GFX11-NEXT: v_writelane_b32 v22, s53, 22
+; GFX11-NEXT: v_writelane_b32 v22, s54, 23
+; GFX11-NEXT: v_writelane_b32 v22, s55, 24
+; GFX11-NEXT: v_writelane_b32 v22, s56, 25
+; GFX11-NEXT: v_writelane_b32 v22, s57, 26
+; GFX11-NEXT: v_writelane_b32 v22, s59, 27
+; GFX11-NEXT: s_add_i32 s59, s32, 0x4240
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v23, s59, 27
-; GFX11-NEXT: v_readfirstlane_b32 s59, v22
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_readlane_b32 s59, v23, 27
-; GFX11-NEXT: v_readlane_b32 s57, v23, 26
-; GFX11-NEXT: v_readlane_b32 s56, v23, 25
-; GFX11-NEXT: v_readlane_b32 s55, v23, 24
-; GFX11-NEXT: v_readlane_b32 s54, v23, 23
-; GFX11-NEXT: v_readlane_b32 s53, v23, 22
-; GFX11-NEXT: v_readlane_b32 s52, v23, 21
-; GFX11-NEXT: v_readlane_b32 s51, v23, 20
-; GFX11-NEXT: v_readlane_b32 s50, v23, 19
-; GFX11-NEXT: v_readlane_b32 s49, v23, 18
-; GFX11-NEXT: v_readlane_b32 s48, v23, 17
-; GFX11-NEXT: v_readlane_b32 s47, v23, 16
-; GFX11-NEXT: v_readlane_b32 s46, v23, 15
-; GFX11-NEXT: v_readlane_b32 s45, v23, 14
-; GFX11-NEXT: v_readlane_b32 s44, v23, 13
-; GFX11-NEXT: v_readlane_b32 s43, v23, 12
-; GFX11-NEXT: v_readlane_b32 s42, v23, 11
-; GFX11-NEXT: v_readlane_b32 s41, v23, 10
-; GFX11-NEXT: v_readlane_b32 s40, v23, 9
-; GFX11-NEXT: v_readlane_b32 s39, v23, 8
-; GFX11-NEXT: v_readlane_b32 s38, v23, 7
-; GFX11-NEXT: v_readlane_b32 s37, v23, 6
-; GFX11-NEXT: v_readlane_b32 s36, v23, 5
-; GFX11-NEXT: v_readlane_b32 s35, v23, 4
-; GFX11-NEXT: v_readlane_b32 s34, v23, 3
-; GFX11-NEXT: v_readlane_b32 s33, v23, 2
-; GFX11-NEXT: v_readlane_b32 s31, v23, 1
-; GFX11-NEXT: v_readlane_b32 s30, v23, 0
+; GFX11-NEXT: v_readlane_b32 s59, v22, 27
+; GFX11-NEXT: v_readlane_b32 s57, v22, 26
+; GFX11-NEXT: v_readlane_b32 s56, v22, 25
+; GFX11-NEXT: v_readlane_b32 s55, v22, 24
+; GFX11-NEXT: v_readlane_b32 s54, v22, 23
+; GFX11-NEXT: v_readlane_b32 s53, v22, 22
+; GFX11-NEXT: v_readlane_b32 s52, v22, 21
+; GFX11-NEXT: v_readlane_b32 s51, v22, 20
+; GFX11-NEXT: v_readlane_b32 s50, v22, 19
+; GFX11-NEXT: v_readlane_b32 s49, v22, 18
+; GFX11-NEXT: v_readlane_b32 s48, v22, 17
+; GFX11-NEXT: v_readlane_b32 s47, v22, 16
+; GFX11-NEXT: v_readlane_b32 s46, v22, 15
+; GFX11-NEXT: v_readlane_b32 s45, v22, 14
+; GFX11-NEXT: v_readlane_b32 s44, v22, 13
+; GFX11-NEXT: v_readlane_b32 s43, v22, 12
+; GFX11-NEXT: v_readlane_b32 s42, v22, 11
+; GFX11-NEXT: v_readlane_b32 s41, v22, 10
+; GFX11-NEXT: v_readlane_b32 s40, v22, 9
+; GFX11-NEXT: v_readlane_b32 s39, v22, 8
+; GFX11-NEXT: v_readlane_b32 s38, v22, 7
+; GFX11-NEXT: v_readlane_b32 s37, v22, 6
+; GFX11-NEXT: v_readlane_b32 s36, v22, 5
+; GFX11-NEXT: v_readlane_b32 s35, v22, 4
+; GFX11-NEXT: v_readlane_b32 s34, v22, 3
+; GFX11-NEXT: v_readlane_b32 s33, v22, 2
+; GFX11-NEXT: v_readlane_b32 s31, v22, 1
+; GFX11-NEXT: v_readlane_b32 s30, v22, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
-; GFX11-NEXT: scratch_load_b32 v23, off, s1 ; 4-byte Folded Reload
+; GFX11-NEXT: scratch_load_b32 v22, off, s1 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2236,82 +2128,79 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX12-NEXT: scratch_store_b32 off, v23, s32 offset:32768 ; 4-byte Folded Spill
+; GFX12-NEXT: scratch_store_b32 off, v22, s32 offset:32768 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_writelane_b32 v23, s30, 0
-; GFX12-NEXT: v_dual_mov_b32 v0, s32 :: v_dual_mov_b32 v1, s32
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
+; GFX12-NEXT: v_writelane_b32 v22, s30, 0
+; GFX12-NEXT: v_mov_b32_e32 v0, s32
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_writelane_b32 v23, s31, 1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_add_nc_u32_e32 v22, 0x4200, v1
-; GFX12-NEXT: v_writelane_b32 v23, s33, 2
-; GFX12-NEXT: v_writelane_b32 v23, s34, 3
-; GFX12-NEXT: v_writelane_b32 v23, s35, 4
-; GFX12-NEXT: v_writelane_b32 v23, s36, 5
-; GFX12-NEXT: v_writelane_b32 v23, s37, 6
-; GFX12-NEXT: v_writelane_b32 v23, s38, 7
-; GFX12-NEXT: v_writelane_b32 v23, s39, 8
-; GFX12-NEXT: v_writelane_b32 v23, s40, 9
-; GFX12-NEXT: v_writelane_b32 v23, s41, 10
-; GFX12-NEXT: v_writelane_b32 v23, s42, 11
-; GFX12-NEXT: v_writelane_b32 v23, s43, 12
-; GFX12-NEXT: v_writelane_b32 v23, s44, 13
-; GFX12-NEXT: v_writelane_b32 v23, s45, 14
-; GFX12-NEXT: v_writelane_b32 v23, s46, 15
-; GFX12-NEXT: v_writelane_b32 v23, s47, 16
-; GFX12-NEXT: v_writelane_b32 v23, s48, 17
-; GFX12-NEXT: v_writelane_b32 v23, s49, 18
-; GFX12-NEXT: v_writelane_b32 v23, s50, 19
-; GFX12-NEXT: v_writelane_b32 v23, s51, 20
-; GFX12-NEXT: v_writelane_b32 v23, s52, 21
-; GFX12-NEXT: v_writelane_b32 v23, s53, 22
-; GFX12-NEXT: v_writelane_b32 v23, s54, 23
-; GFX12-NEXT: v_writelane_b32 v23, s55, 24
-; GFX12-NEXT: v_writelane_b32 v23, s56, 25
-; GFX12-NEXT: v_writelane_b32 v23, s57, 26
+; GFX12-NEXT: v_writelane_b32 v22, s31, 1
+; GFX12-NEXT: v_writelane_b32 v22, s33, 2
+; GFX12-NEXT: v_writelane_b32 v22, s34, 3
+; GFX12-NEXT: v_writelane_b32 v22, s35, 4
+; GFX12-NEXT: v_writelane_b32 v22, s36, 5
+; GFX12-NEXT: v_writelane_b32 v22, s37, 6
+; GFX12-NEXT: v_writelane_b32 v22, s38, 7
+; GFX12-NEXT: v_writelane_b32 v22, s39, 8
+; GFX12-NEXT: v_writelane_b32 v22, s40, 9
+; GFX12-NEXT: v_writelane_b32 v22, s41, 10
+; GFX12-NEXT: v_writelane_b32 v22, s42, 11
+; GFX12-NEXT: v_writelane_b32 v22, s43, 12
+; GFX12-NEXT: v_writelane_b32 v22, s44, 13
+; GFX12-NEXT: v_writelane_b32 v22, s45, 14
+; GFX12-NEXT: v_writelane_b32 v22, s46, 15
+; GFX12-NEXT: v_writelane_b32 v22, s47, 16
+; GFX12-NEXT: v_writelane_b32 v22, s48, 17
+; GFX12-NEXT: v_writelane_b32 v22, s49, 18
+; GFX12-NEXT: v_writelane_b32 v22, s50, 19
+; GFX12-NEXT: v_writelane_b32 v22, s51, 20
+; GFX12-NEXT: v_writelane_b32 v22, s52, 21
+; GFX12-NEXT: v_writelane_b32 v22, s53, 22
+; GFX12-NEXT: v_writelane_b32 v22, s54, 23
+; GFX12-NEXT: v_writelane_b32 v22, s55, 24
+; GFX12-NEXT: v_writelane_b32 v22, s56, 25
+; GFX12-NEXT: v_writelane_b32 v22, s57, 26
+; GFX12-NEXT: v_writelane_b32 v22, s59, 27
+; GFX12-NEXT: s_add_co_i32 s59, s32, 0x4200
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_writelane_b32 v23, s59, 27
-; GFX12-NEXT: v_readfirstlane_b32 s59, v22
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s59, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_readlane_b32 s59, v23, 27
-; GFX12-NEXT: v_readlane_b32 s57, v23, 26
-; GFX12-NEXT: v_readlane_b32 s56, v23, 25
-; GFX12-NEXT: v_readlane_b32 s55, v23, 24
-; GFX12-NEXT: v_readlane_b32 s54, v23, 23
-; GFX12-NEXT: v_readlane_b32 s53, v23, 22
-; GFX12-NEXT: v_readlane_b32 s52, v23, 21
-; GFX12-NEXT: v_readlane_b32 s51, v23, 20
-; GFX12-NEXT: v_readlane_b32 s50, v23, 19
-; GFX12-NEXT: v_readlane_b32 s49, v23, 18
-; GFX12-NEXT: v_readlane_b32 s48, v23, 17
-; GFX12-NEXT: v_readlane_b32 s47, v23, 16
-; GFX12-NEXT: v_readlane_b32 s46, v23, 15
-; GFX12-NEXT: v_readlane_b32 s45, v23, 14
-; GFX12-NEXT: v_readlane_b32 s44, v23, 13
-; GFX12-NEXT: v_readlane_b32 s43, v23, 12
-; GFX12-NEXT: v_readlane_b32 s42, v23, 11
-; GFX12-NEXT: v_readlane_b32 s41, v23, 10
-; GFX12-NEXT: v_readlane_b32 s40, v23, 9
-; GFX12-NEXT: v_readlane_b32 s39, v23, 8
-; GFX12-NEXT: v_readlane_b32 s38, v23, 7
-; GFX12-NEXT: v_readlane_b32 s37, v23, 6
-; GFX12-NEXT: v_readlane_b32 s36, v23, 5
-; GFX12-NEXT: v_readlane_b32 s35, v23, 4
-; GFX12-NEXT: v_readlane_b32 s34, v23, 3
-; GFX12-NEXT: v_readlane_b32 s33, v23, 2
-; GFX12-NEXT: v_readlane_b32 s31, v23, 1
-; GFX12-NEXT: v_readlane_b32 s30, v23, 0
+; GFX12-NEXT: v_readlane_b32 s59, v22, 27
+; GFX12-NEXT: v_readlane_b32 s57, v22, 26
+; GFX12-NEXT: v_readlane_b32 s56, v22, 25
+; GFX12-NEXT: v_readlane_b32 s55, v22, 24
+; GFX12-NEXT: v_readlane_b32 s54, v22, 23
+; GFX12-NEXT: v_readlane_b32 s53, v22, 22
+; GFX12-NEXT: v_readlane_b32 s52, v22, 21
+; GFX12-NEXT: v_readlane_b32 s51, v22, 20
+; GFX12-NEXT: v_readlane_b32 s50, v22, 19
+; GFX12-NEXT: v_readlane_b32 s49, v22, 18
+; GFX12-NEXT: v_readlane_b32 s48, v22, 17
+; GFX12-NEXT: v_readlane_b32 s47, v22, 16
+; GFX12-NEXT: v_readlane_b32 s46, v22, 15
+; GFX12-NEXT: v_readlane_b32 s45, v22, 14
+; GFX12-NEXT: v_readlane_b32 s44, v22, 13
+; GFX12-NEXT: v_readlane_b32 s43, v22, 12
+; GFX12-NEXT: v_readlane_b32 s42, v22, 11
+; GFX12-NEXT: v_readlane_b32 s41, v22, 10
+; GFX12-NEXT: v_readlane_b32 s40, v22, 9
+; GFX12-NEXT: v_readlane_b32 s39, v22, 8
+; GFX12-NEXT: v_readlane_b32 s38, v22, 7
+; GFX12-NEXT: v_readlane_b32 s37, v22, 6
+; GFX12-NEXT: v_readlane_b32 s36, v22, 5
+; GFX12-NEXT: v_readlane_b32 s35, v22, 4
+; GFX12-NEXT: v_readlane_b32 s34, v22, 3
+; GFX12-NEXT: v_readlane_b32 s33, v22, 2
+; GFX12-NEXT: v_readlane_b32 s31, v22, 1
+; GFX12-NEXT: v_readlane_b32 s30, v22, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX12-NEXT: scratch_load_b32 v23, off, s32 offset:32768 ; 4-byte Folded Reload
+; GFX12-NEXT: scratch_load_b32 v22, off, s32 offset:32768 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll b/llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
index 343925528a520e..37a261cab75635 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
@@ -10,7 +10,7 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; MUBUF-NEXT: global_load_dwordx2 v[11:12], v[1:2], off offset:32
; MUBUF-NEXT: global_load_dwordx4 v[3:6], v[1:2], off
; MUBUF-NEXT: global_load_dwordx4 v[7:10], v[1:2], off offset:16
-; MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
+; MUBUF-NEXT: s_lshr_b32 s4, s32, 6
; MUBUF-NEXT: s_waitcnt vmcnt(2)
; MUBUF-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:32
; MUBUF-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:36
@@ -25,7 +25,7 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; MUBUF-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:20
; MUBUF-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:16
; MUBUF-NEXT: ;;#ASMSTART
-; MUBUF-NEXT: ; use v0
+; MUBUF-NEXT: ; use s4
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_setpc_b64 s[30:31]
@@ -36,7 +36,7 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; FLATSCR-NEXT: global_load_dwordx4 v[3:6], v[1:2], off
; FLATSCR-NEXT: global_load_dwordx4 v[7:10], v[1:2], off offset:16
; FLATSCR-NEXT: global_load_dwordx2 v[11:12], v[1:2], off offset:32
-; FLATSCR-NEXT: v_mov_b32_e32 v0, s32
+; FLATSCR-NEXT: s_mov_b32 s0, s32
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
; FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s32
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
@@ -44,7 +44,7 @@ define void @memcpy_fixed_align(ptr addrspace(5) %dst, ptr addrspace(1) %src) {
; FLATSCR-NEXT: s_waitcnt vmcnt(2)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[11:12], s32 offset:32
; FLATSCR-NEXT: ;;#ASMSTART
-; FLATSCR-NEXT: ; use v0
+; FLATSCR-NEXT: ; use s0
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
index ebc209bd4d4510..a37e2bf4eb2945 100644
--- a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
+++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
@@ -263,10 +263,10 @@ define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 {
; GCN-LABEL: test_export_across_store_load:
; GCN: ; %bb.0:
; GCN-NEXT: s_setprio 2
-; GCN-NEXT: v_mov_b32_e32 v2, 16
+; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
+; GCN-NEXT: v_cndmask_b32_e32 v0, 16, v2, vcc_lo
; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: scratch_store_b32 v0, v1, off
; GCN-NEXT: scratch_load_b32 v0, off, off
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
index 5f9e9b8280326b..4ada73029716dc 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
@@ -46,7 +46,7 @@ done:
; GCN-LABEL: {{^}}legal_offset_fi_offset:
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
-; GCN-DAG: v_mov_b32_e32 [[K8000:v[0-9]+]], 0x8004
+; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, 4,
; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, 0x8004
; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
@@ -84,8 +84,10 @@ done:
}
; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds:
-; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
-; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
+; GCN: s_add_i32 [[ADD0:s[0-9]+]], s{{[0-9]+}}, 4
+; GCN: s_add_i32 [[ADD1:s[0-9]+]], [[ADD0]], 16
+; GCN: v_mov_b32_e32 [[V_ADD:v[0-9]+]], [[ADD1]]
+; GCN: buffer_store_dword v{{[0-9]+}}, [[V_ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) {
entry:
%array = alloca [8192 x i32], addrspace(5)
@@ -96,8 +98,10 @@ entry:
}
; GCN-LABEL: {{^}}neg_vaddr_offset:
-; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
-; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
+; GCN: s_add_i32 [[ADD0:s[0-9]+]], s{{[0-9]+}}, 4
+; GCN: s_add_i32 [[ADD1:s[0-9]+]], [[ADD0]], 16
+; GCN: v_mov_b32_e32 [[V_ADD:v[0-9]+]], [[ADD1]]
+; GCN: buffer_store_dword v{{[0-9]+}}, [[V_ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {
entry:
%array = alloca [8192 x i32], addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
index da6f90561b517e..674c7a67303e49 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
@@ -51,11 +51,16 @@
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
-; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
-; MUBUF-DAG: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
-; MUBUF-DAG: s_mov_b32 s2, -1
-; SI-DAG: s_mov_b32 s3, 0xe8f000
-; VI-DAG: s_mov_b32 s3, 0xe80000
+; SIVI-DAG: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
+; SIVI-DAG: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
+; SIVI-DAG: s_mov_b32 s6, -1
+
+; GFX9-MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; GFX9-MUBUF-DAG: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; GFX9-MUBUF-DAG: s_mov_b32 s2, -1
+
+; SI-DAG: s_mov_b32 s7, 0xe8f000
+; VI-DAG: s_mov_b32 s7, 0xe80000
; GFX9-MUBUF-DAG: s_mov_b32 s3, 0xe00000
; GFX10_W32-MUBUF-DAG: s_mov_b32 s3, 0x31c16000
; GFX10_W64-MUBUF-DAG: s_mov_b32 s3, 0x31e16000
@@ -117,7 +122,7 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
-; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; MUBUF-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; FLATSCR-NOT: SCRATCH_RSRC_DWORD
@@ -170,7 +175,7 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
-; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; MUBUF-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; FLATSCR-NOT: SCRATCH_RSRC_DWORD
@@ -199,8 +204,8 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-FLATSCR: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; SIVI: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
-; SIVI-NOT: s_mov_b32 s0
+; SIVI: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
+; SIVI-NOT: s_mov_b32 s4
; SIVI: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
; SIVI: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
@@ -252,11 +257,11 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; SIVI: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SIVI: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
; SIVI: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
; SIVI: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
-; GFX9_10-MUBUF: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; GFX9_10-MUBUF: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; GFX9_10-MUBUF: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
; GFX9_10-MUBUF: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
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