[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Clang][OpenMP] Add interchange directive (PR #92030)
Michael Kruse via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed May 22 04:46:46 PDT 2024
https://github.com/Meinersbur updated https://github.com/llvm/llvm-project/pull/92030
>From 76634ade083cde2881bb072fe821f1d434f99196 Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Wed, 22 May 2024 13:22:05 +0200
Subject: [PATCH 1/2] [Clang][OpenMP] Add interchange directive
---
clang/include/clang-c/Index.h | 4 +
clang/include/clang/AST/RecursiveASTVisitor.h | 3 +
clang/include/clang/AST/StmtOpenMP.h | 76 +-
clang/include/clang/Basic/StmtNodes.td | 1 +
clang/include/clang/Sema/SemaOpenMP.h | 6 +
.../include/clang/Serialization/ASTBitCodes.h | 1 +
clang/lib/AST/StmtOpenMP.cpp | 20 +
clang/lib/AST/StmtPrinter.cpp | 5 +
clang/lib/AST/StmtProfile.cpp | 5 +
clang/lib/Basic/OpenMPKinds.cpp | 4 +-
clang/lib/CodeGen/CGStmt.cpp | 3 +
clang/lib/CodeGen/CGStmtOpenMP.cpp | 10 +
clang/lib/CodeGen/CodeGenFunction.h | 1 +
clang/lib/Parse/ParseOpenMP.cpp | 2 +
clang/lib/Sema/SemaExceptionSpec.cpp | 1 +
clang/lib/Sema/SemaOpenMP.cpp | 162 ++
clang/lib/Sema/TreeTransform.h | 11 +
clang/lib/Serialization/ASTReaderStmt.cpp | 11 +
clang/lib/Serialization/ASTWriterStmt.cpp | 5 +
clang/test/OpenMP/interchange_ast_print.cpp | 135 ++
clang/test/OpenMP/interchange_codegen.cpp | 1990 +++++++++++++++++
clang/test/OpenMP/interchange_messages.cpp | 77 +
clang/tools/libclang/CIndex.cpp | 8 +
clang/tools/libclang/CXCursor.cpp | 3 +
llvm/include/llvm/Frontend/OpenMP/OMP.td | 3 +
.../test/transform/interchange/foreach.cpp | 216 ++
.../test/transform/interchange/intfor.c | 38 +
.../test/transform/interchange/iterfor.cpp | 222 ++
.../parallel-wsloop-collapse-foreach.cpp | 340 +++
.../parallel-wsloop-collapse-intfor.cpp | 106 +
30 files changed, 3467 insertions(+), 2 deletions(-)
create mode 100644 clang/test/OpenMP/interchange_ast_print.cpp
create mode 100644 clang/test/OpenMP/interchange_codegen.cpp
create mode 100644 clang/test/OpenMP/interchange_messages.cpp
create mode 100644 openmp/runtime/test/transform/interchange/foreach.cpp
create mode 100644 openmp/runtime/test/transform/interchange/intfor.c
create mode 100644 openmp/runtime/test/transform/interchange/iterfor.cpp
create mode 100644 openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-foreach.cpp
create mode 100644 openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-intfor.cpp
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index c7d63818ece23..a79aafbf20222 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2150,6 +2150,10 @@ enum CXCursorKind {
*/
CXCursor_OMPReverseDirective = 307,
+ /** OpenMP interchange directive.
+ */
+ CXCursor_OMPInterchangeDirective = 308,
+
/** OpenACC Compute Construct.
*/
CXCursor_OpenACCComputeConstruct = 320,
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index 06b29d59785f6..1bb167d7ddc3c 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3024,6 +3024,9 @@ DEF_TRAVERSE_STMT(OMPUnrollDirective,
DEF_TRAVERSE_STMT(OMPReverseDirective,
{ TRY_TO(TraverseOMPExecutableDirective(S)); })
+DEF_TRAVERSE_STMT(OMPInterchangeDirective,
+ { TRY_TO(TraverseOMPExecutableDirective(S)); })
+
DEF_TRAVERSE_STMT(OMPForDirective,
{ TRY_TO(TraverseOMPExecutableDirective(S)); })
diff --git a/clang/include/clang/AST/StmtOpenMP.h b/clang/include/clang/AST/StmtOpenMP.h
index fb7f413162fad..01c8b8e1a9f5e 100644
--- a/clang/include/clang/AST/StmtOpenMP.h
+++ b/clang/include/clang/AST/StmtOpenMP.h
@@ -1009,7 +1009,7 @@ class OMPLoopTransformationDirective : public OMPLoopBasedDirective {
static bool classof(const Stmt *T) {
Stmt::StmtClass C = T->getStmtClass();
return C == OMPTileDirectiveClass || C == OMPUnrollDirectiveClass ||
- C == OMPReverseDirectiveClass;
+ C == OMPReverseDirectiveClass || C == OMPInterchangeDirectiveClass;
}
};
@@ -5777,6 +5777,80 @@ class OMPReverseDirective final : public OMPLoopTransformationDirective {
}
};
+/// Represents the '#pragma omp interchange' loop transformation directive.
+///
+/// \code{c}
+/// #pragma omp interchange
+/// for (int i = 0; i < m; ++i)
+/// for (int j = 0; j < n; ++j)
+/// ..
+/// \endcode
+class OMPInterchangeDirective final : public OMPLoopTransformationDirective {
+ friend class ASTStmtReader;
+ friend class OMPExecutableDirective;
+
+ /// Offsets of child members.
+ enum {
+ PreInitsOffset = 0,
+ TransformedStmtOffset,
+ };
+
+ explicit OMPInterchangeDirective(SourceLocation StartLoc,
+ SourceLocation EndLoc, unsigned NumLoops)
+ : OMPLoopTransformationDirective(OMPInterchangeDirectiveClass,
+ llvm::omp::OMPD_interchange, StartLoc,
+ EndLoc, NumLoops) {
+ setNumGeneratedLoops(3 * NumLoops);
+ }
+
+ void setPreInits(Stmt *PreInits) {
+ Data->getChildren()[PreInitsOffset] = PreInits;
+ }
+
+ void setTransformedStmt(Stmt *S) {
+ Data->getChildren()[TransformedStmtOffset] = S;
+ }
+
+public:
+ /// Create a new AST node representation for '#pragma omp interchange'.
+ ///
+ /// \param C Context of the AST.
+ /// \param StartLoc Location of the introducer (e.g. the 'omp' token).
+ /// \param EndLoc Location of the directive's end (e.g. the tok::eod).
+ /// \param Clauses The directive's clauses.
+ /// \param NumLoops Number of affected loops
+ /// (number of items in the 'permutation' clause if present).
+ /// \param AssociatedStmt The outermost associated loop.
+ /// \param TransformedStmt The loop nest after tiling, or nullptr in
+ /// dependent contexts.
+ /// \param PreInits Helper preinits statements for the loop nest.
+ static OMPInterchangeDirective *
+ Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc,
+ ArrayRef<OMPClause *> Clauses, unsigned NumLoops, Stmt *AssociatedStmt,
+ Stmt *TransformedStmt, Stmt *PreInits);
+
+ /// Build an empty '#pragma omp interchange' AST node for deserialization.
+ ///
+ /// \param C Context of the AST.
+ /// \param NumClauses Number of clauses to allocate.
+ /// \param NumLoops Number of associated loops to allocate.
+ static OMPInterchangeDirective *
+ CreateEmpty(const ASTContext &C, unsigned NumClauses, unsigned NumLoops);
+
+ /// Gets the associated loops after the transformation. This is the de-sugared
+ /// replacement or nullptr in dependent contexts.
+ Stmt *getTransformedStmt() const {
+ return Data->getChildren()[TransformedStmtOffset];
+ }
+
+ /// Return preinits statement.
+ Stmt *getPreInits() const { return Data->getChildren()[PreInitsOffset]; }
+
+ static bool classof(const Stmt *T) {
+ return T->getStmtClass() == OMPInterchangeDirectiveClass;
+ }
+};
+
/// This represents '#pragma omp scan' directive.
///
/// \code
diff --git a/clang/include/clang/Basic/StmtNodes.td b/clang/include/clang/Basic/StmtNodes.td
index b2e2be5c998bb..b445ea225eac5 100644
--- a/clang/include/clang/Basic/StmtNodes.td
+++ b/clang/include/clang/Basic/StmtNodes.td
@@ -230,6 +230,7 @@ def OMPLoopTransformationDirective : StmtNode<OMPLoopBasedDirective, 1>;
def OMPTileDirective : StmtNode<OMPLoopTransformationDirective>;
def OMPUnrollDirective : StmtNode<OMPLoopTransformationDirective>;
def OMPReverseDirective : StmtNode<OMPLoopTransformationDirective>;
+def OMPInterchangeDirective : StmtNode<OMPLoopTransformationDirective>;
def OMPForDirective : StmtNode<OMPLoopDirective>;
def OMPForSimdDirective : StmtNode<OMPLoopDirective>;
def OMPSectionsDirective : StmtNode<OMPExecutableDirective>;
diff --git a/clang/include/clang/Sema/SemaOpenMP.h b/clang/include/clang/Sema/SemaOpenMP.h
index ca91bffe24f6f..06376f173e8df 100644
--- a/clang/include/clang/Sema/SemaOpenMP.h
+++ b/clang/include/clang/Sema/SemaOpenMP.h
@@ -425,6 +425,12 @@ class SemaOpenMP : public SemaBase {
/// Called on well-formed '#pragma omp reverse'.
StmtResult ActOnOpenMPReverseDirective(Stmt *AStmt, SourceLocation StartLoc,
SourceLocation EndLoc);
+ /// Called on well-formed '#pragma omp interchange' after parsing of its
+ /// clauses and the associated statement.
+ StmtResult ActOnOpenMPInterchangeDirective(ArrayRef<OMPClause *> Clauses,
+ Stmt *AStmt,
+ SourceLocation StartLoc,
+ SourceLocation EndLoc);
/// Called on well-formed '\#pragma omp for' after parsing
/// of the associated statement.
StmtResult
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h
index dee0d073557cc..5fbdfd7a496fe 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1857,6 +1857,7 @@ enum StmtCode {
STMT_OMP_TILE_DIRECTIVE,
STMT_OMP_UNROLL_DIRECTIVE,
STMT_OMP_REVERSE_DIRECTIVE,
+ STMT_OMP_INTERCHANGE_DIRECTIVE,
STMT_OMP_FOR_DIRECTIVE,
STMT_OMP_FOR_SIMD_DIRECTIVE,
STMT_OMP_SECTIONS_DIRECTIVE,
diff --git a/clang/lib/AST/StmtOpenMP.cpp b/clang/lib/AST/StmtOpenMP.cpp
index 83b8a08e9af73..24d8eb25c59ba 100644
--- a/clang/lib/AST/StmtOpenMP.cpp
+++ b/clang/lib/AST/StmtOpenMP.cpp
@@ -467,6 +467,26 @@ OMPReverseDirective *OMPReverseDirective::CreateEmpty(const ASTContext &C,
SourceLocation(), SourceLocation());
}
+OMPInterchangeDirective *OMPInterchangeDirective::Create(
+ const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc,
+ ArrayRef<OMPClause *> Clauses, unsigned NumLoops, Stmt *AssociatedStmt,
+ Stmt *TransformedStmt, Stmt *PreInits) {
+ OMPInterchangeDirective *Dir = createDirective<OMPInterchangeDirective>(
+ C, Clauses, AssociatedStmt, TransformedStmtOffset + 1, StartLoc, EndLoc,
+ NumLoops);
+ Dir->setTransformedStmt(TransformedStmt);
+ Dir->setPreInits(PreInits);
+ return Dir;
+}
+
+OMPInterchangeDirective *
+OMPInterchangeDirective::CreateEmpty(const ASTContext &C, unsigned NumClauses,
+ unsigned NumLoops) {
+ return createEmptyDirective<OMPInterchangeDirective>(
+ C, NumClauses, /*HasAssociatedStmt=*/true, TransformedStmtOffset + 1,
+ SourceLocation(), SourceLocation(), NumLoops);
+}
+
OMPForSimdDirective *
OMPForSimdDirective::Create(const ASTContext &C, SourceLocation StartLoc,
SourceLocation EndLoc, unsigned CollapsedNum,
diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp
index 64b481f680311..64bee75b205ae 100644
--- a/clang/lib/AST/StmtPrinter.cpp
+++ b/clang/lib/AST/StmtPrinter.cpp
@@ -768,6 +768,11 @@ void StmtPrinter::VisitOMPReverseDirective(OMPReverseDirective *Node) {
PrintOMPExecutableDirective(Node);
}
+void StmtPrinter::VisitOMPInterchangeDirective(OMPInterchangeDirective *Node) {
+ Indent() << "#pragma omp interchange";
+ PrintOMPExecutableDirective(Node);
+}
+
void StmtPrinter::VisitOMPForDirective(OMPForDirective *Node) {
Indent() << "#pragma omp for";
PrintOMPExecutableDirective(Node);
diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 7445e5519b972..1ae99d43575a7 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -989,6 +989,11 @@ void StmtProfiler::VisitOMPReverseDirective(const OMPReverseDirective *S) {
VisitOMPLoopTransformationDirective(S);
}
+void StmtProfiler::VisitOMPInterchangeDirective(
+ const OMPInterchangeDirective *S) {
+ VisitOMPLoopTransformationDirective(S);
+}
+
void StmtProfiler::VisitOMPForDirective(const OMPForDirective *S) {
VisitOMPLoopDirective(S);
}
diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp
index 803808c38e2fe..ff5d5c8bdc981 100644
--- a/clang/lib/Basic/OpenMPKinds.cpp
+++ b/clang/lib/Basic/OpenMPKinds.cpp
@@ -684,7 +684,8 @@ bool clang::isOpenMPLoopBoundSharingDirective(OpenMPDirectiveKind Kind) {
}
bool clang::isOpenMPLoopTransformationDirective(OpenMPDirectiveKind DKind) {
- return DKind == OMPD_tile || DKind == OMPD_unroll || DKind == OMPD_reverse;
+ return DKind == OMPD_tile || DKind == OMPD_unroll || DKind == OMPD_reverse ||
+ DKind == OMPD_interchange;
}
bool clang::isOpenMPCombinedParallelADirective(OpenMPDirectiveKind DKind) {
@@ -809,6 +810,7 @@ void clang::getOpenMPCaptureRegions(
case OMPD_tile:
case OMPD_unroll:
case OMPD_reverse:
+ case OMPD_interchange:
// loop transformations do not introduce captures.
break;
case OMPD_threadprivate:
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 93c2f8900dd12..ba7c52cc6ab7b 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -225,6 +225,9 @@ void CodeGenFunction::EmitStmt(const Stmt *S, ArrayRef<const Attr *> Attrs) {
case Stmt::OMPReverseDirectiveClass:
EmitOMPReverseDirective(cast<OMPReverseDirective>(*S));
break;
+ case Stmt::OMPInterchangeDirectiveClass:
+ EmitOMPInterchangeDirective(cast<OMPInterchangeDirective>(*S));
+ break;
case Stmt::OMPForDirectiveClass:
EmitOMPForDirective(cast<OMPForDirective>(*S));
break;
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index ad6c044aa483b..7a37e452fb559 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -189,6 +189,9 @@ class OMPLoopScope : public CodeGenFunction::RunCleanupsScope {
PreInits = Unroll->getPreInits();
} else if (const auto *Reverse = dyn_cast<OMPReverseDirective>(&S)) {
PreInits = Reverse->getPreInits();
+ } else if (const auto *Interchange =
+ dyn_cast<OMPInterchangeDirective>(&S)) {
+ PreInits = Interchange->getPreInits();
} else {
llvm_unreachable("Unknown loop-based directive kind.");
}
@@ -2770,6 +2773,13 @@ void CodeGenFunction::EmitOMPReverseDirective(const OMPReverseDirective &S) {
EmitStmt(S.getTransformedStmt());
}
+void CodeGenFunction::EmitOMPInterchangeDirective(
+ const OMPInterchangeDirective &S) {
+ // Emit the de-sugared statement.
+ OMPTransformDirectiveScopeRAII InterchangeScope(*this, &S);
+ EmitStmt(S.getTransformedStmt());
+}
+
void CodeGenFunction::EmitOMPUnrollDirective(const OMPUnrollDirective &S) {
bool UseOMPIRBuilder = CGM.getLangOpts().OpenMPIRBuilder;
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index ac738e1e82886..c2a8e65ca2d0a 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -3808,6 +3808,7 @@ class CodeGenFunction : public CodeGenTypeCache {
void EmitOMPTileDirective(const OMPTileDirective &S);
void EmitOMPUnrollDirective(const OMPUnrollDirective &S);
void EmitOMPReverseDirective(const OMPReverseDirective &S);
+ void EmitOMPInterchangeDirective(const OMPInterchangeDirective &S);
void EmitOMPForDirective(const OMPForDirective &S);
void EmitOMPForSimdDirective(const OMPForSimdDirective &S);
void EmitOMPSectionsDirective(const OMPSectionsDirective &S);
diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp
index 57fcf6ce520ac..0e3e604203c86 100644
--- a/clang/lib/Parse/ParseOpenMP.cpp
+++ b/clang/lib/Parse/ParseOpenMP.cpp
@@ -2385,6 +2385,7 @@ Parser::DeclGroupPtrTy Parser::ParseOpenMPDeclarativeDirectiveWithExtDecl(
case OMPD_tile:
case OMPD_unroll:
case OMPD_reverse:
+ case OMPD_interchange:
case OMPD_task:
case OMPD_taskyield:
case OMPD_barrier:
@@ -2804,6 +2805,7 @@ StmtResult Parser::ParseOpenMPDeclarativeOrExecutableDirective(
case OMPD_tile:
case OMPD_unroll:
case OMPD_reverse:
+ case OMPD_interchange:
case OMPD_for:
case OMPD_for_simd:
case OMPD_sections:
diff --git a/clang/lib/Sema/SemaExceptionSpec.cpp b/clang/lib/Sema/SemaExceptionSpec.cpp
index 4de7183cde281..5991f496d3a0f 100644
--- a/clang/lib/Sema/SemaExceptionSpec.cpp
+++ b/clang/lib/Sema/SemaExceptionSpec.cpp
@@ -1487,6 +1487,7 @@ CanThrowResult Sema::canThrow(const Stmt *S) {
case Stmt::OMPTileDirectiveClass:
case Stmt::OMPUnrollDirectiveClass:
case Stmt::OMPReverseDirectiveClass:
+ case Stmt::OMPInterchangeDirectiveClass:
case Stmt::OMPSingleDirectiveClass:
case Stmt::OMPTargetDataDirectiveClass:
case Stmt::OMPTargetDirectiveClass:
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index c2fd4de933ae4..ef141003b7d61 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -39,6 +39,7 @@
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/PointerEmbeddedInt.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Frontend/OpenMP/OMPAssume.h"
@@ -4335,6 +4336,7 @@ void SemaOpenMP::ActOnOpenMPRegionStart(OpenMPDirectiveKind DKind,
case OMPD_tile:
case OMPD_unroll:
case OMPD_reverse:
+ case OMPD_interchange:
break;
case OMPD_loop:
// TODO: 'loop' may require additional parameters depending on the binding.
@@ -6552,6 +6554,10 @@ StmtResult SemaOpenMP::ActOnOpenMPExecutableDirective(
"reverse directive does not support any clauses");
Res = ActOnOpenMPReverseDirective(AStmt, StartLoc, EndLoc);
break;
+ case OMPD_interchange:
+ Res = ActOnOpenMPInterchangeDirective(ClausesWithImplicit, AStmt, StartLoc,
+ EndLoc);
+ break;
case OMPD_for:
Res = ActOnOpenMPForDirective(ClausesWithImplicit, AStmt, StartLoc, EndLoc,
VarsWithInheritedDSA);
@@ -15139,6 +15145,8 @@ bool SemaOpenMP::checkTransformableLoopNest(
DependentPreInits = Dir->getPreInits();
else if (auto *Dir = dyn_cast<OMPReverseDirective>(Transform))
DependentPreInits = Dir->getPreInits();
+ else if (auto *Dir = dyn_cast<OMPInterchangeDirective>(Transform))
+ DependentPreInits = Dir->getPreInits();
else
llvm_unreachable("Unhandled loop transformation");
@@ -15937,6 +15945,160 @@ StmtResult SemaOpenMP::ActOnOpenMPReverseDirective(Stmt *AStmt,
buildPreInits(Context, PreInits));
}
+StmtResult SemaOpenMP::ActOnOpenMPInterchangeDirective(
+ ArrayRef<OMPClause *> Clauses, Stmt *AStmt, SourceLocation StartLoc,
+ SourceLocation EndLoc) {
+ ASTContext &Context = getASTContext();
+ DeclContext *CurContext = SemaRef.CurContext;
+ Scope *CurScope = SemaRef.getCurScope();
+
+ // Empty statement should only be possible if there already was an error.
+ if (!AStmt)
+ return StmtError();
+
+ // interchange without permutation clause swaps two loops.
+ constexpr size_t NumLoops = 2;
+
+ // Verify and diagnose loop nest.
+ SmallVector<OMPLoopBasedDirective::HelperExprs, 4> LoopHelpers(NumLoops);
+ Stmt *Body = nullptr;
+ SmallVector<SmallVector<Stmt *, 0>, 2> OriginalInits;
+ if (!checkTransformableLoopNest(OMPD_interchange, AStmt, NumLoops,
+ LoopHelpers, Body, OriginalInits))
+ return StmtError();
+
+ // Delay interchange to when template is completely instantiated.
+ if (CurContext->isDependentContext())
+ return OMPInterchangeDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, nullptr, nullptr);
+
+ assert(LoopHelpers.size() == NumLoops &&
+ "Expecting loop iteration space dimensionaly to match number of "
+ "affected loops");
+ assert(OriginalInits.size() == NumLoops &&
+ "Expecting loop iteration space dimensionaly to match number of "
+ "affected loops");
+
+ // Decode the permutation clause.
+ constexpr uint64_t Permutation[] = {1, 0};
+
+ // Find the affected loops.
+ SmallVector<Stmt *> LoopStmts(NumLoops, nullptr);
+ collectLoopStmts(AStmt, LoopStmts);
+
+ // Collect pre-init statements on the order before the permuation.
+ SmallVector<Stmt *> PreInits;
+ for (auto I : llvm::seq<int>(NumLoops)) {
+ OMPLoopBasedDirective::HelperExprs &LoopHelper = LoopHelpers[I];
+
+ assert(LoopHelper.Counters.size() == 1 &&
+ "Single-dimensional loop iteration space expected");
+ auto *OrigCntVar = cast<DeclRefExpr>(LoopHelper.Counters.front());
+
+ std::string OrigVarName = OrigCntVar->getNameInfo().getAsString();
+ addLoopPreInits(Context, LoopHelper, LoopStmts[I], OriginalInits[I],
+ PreInits);
+ }
+
+ SmallVector<VarDecl *> PermutedIndVars;
+ PermutedIndVars.resize(NumLoops);
+ CaptureVars CopyTransformer(SemaRef);
+
+ // Create the permuted loops from the inside to the outside of the
+ // interchanged loop nest. Body of the innermost new loop is the original
+ // innermost body.
+ Stmt *Inner = Body;
+ for (auto TargetIdx : llvm::reverse(llvm::seq<int>(NumLoops))) {
+ // Get the original loop that belongs to this new position.
+ uint64_t SourceIdx = Permutation[TargetIdx];
+ OMPLoopBasedDirective::HelperExprs &SourceHelper = LoopHelpers[SourceIdx];
+ Stmt *SourceLoopStmt = LoopStmts[SourceIdx];
+ assert(SourceHelper.Counters.size() == 1 &&
+ "Single-dimensional loop iteration space expected");
+ auto *OrigCntVar = cast<DeclRefExpr>(SourceHelper.Counters.front());
+
+ // Normalized loop counter variable: From 0 to n-1, always an integer type.
+ DeclRefExpr *IterVarRef = cast<DeclRefExpr>(SourceHelper.IterationVarRef);
+ QualType IVTy = IterVarRef->getType();
+ assert(IVTy->isIntegerType() &&
+ "Expected the logical iteration counter to be an integer");
+
+ std::string OrigVarName = OrigCntVar->getNameInfo().getAsString();
+ SourceLocation OrigVarLoc = IterVarRef->getExprLoc();
+
+ // Make a copy of the NumIterations expression for each use: By the AST
+ // constraints, every expression object in a DeclContext must be unique.
+ auto MakeNumIterations = [&CopyTransformer, &SourceHelper]() -> Expr * {
+ return AssertSuccess(
+ CopyTransformer.TransformExpr(SourceHelper.NumIterations));
+ };
+
+ // Iteration variable for the permuted loop. Reuse the one from
+ // checkOpenMPLoop which will also be used to update the original loop
+ // variable.
+ std::string PermutedCntName =
+ (Twine(".permuted_") + llvm::utostr(TargetIdx) + ".iv." + OrigVarName)
+ .str();
+ auto *PermutedCntDecl = cast<VarDecl>(IterVarRef->getDecl());
+ PermutedCntDecl->setDeclName(
+ &SemaRef.PP.getIdentifierTable().get(PermutedCntName));
+ PermutedIndVars[TargetIdx] = PermutedCntDecl;
+ auto MakePermutedRef = [this, PermutedCntDecl, IVTy, OrigVarLoc]() {
+ return buildDeclRefExpr(SemaRef, PermutedCntDecl, IVTy, OrigVarLoc);
+ };
+
+ // For init-statement:
+ // \code{c}
+ // auto .permuted_{target}.iv = 0
+ // \endcode
+ ExprResult Zero = SemaRef.ActOnIntegerConstant(OrigVarLoc, 0);
+ if (!Zero.isUsable())
+ return StmtError();
+ SemaRef.AddInitializerToDecl(PermutedCntDecl, Zero.get(),
+ /*DirectInit=*/false);
+ StmtResult InitStmt = new (Context)
+ DeclStmt(DeclGroupRef(PermutedCntDecl), OrigCntVar->getBeginLoc(),
+ OrigCntVar->getEndLoc());
+ if (!InitStmt.isUsable())
+ return StmtError();
+
+ // For cond-expression:
+ // \code{c}
+ // .permuted_{target}.iv < NumIterations
+ // \endcode
+ ExprResult CondExpr =
+ SemaRef.BuildBinOp(CurScope, SourceHelper.Cond->getExprLoc(), BO_LT,
+ MakePermutedRef(), MakeNumIterations());
+ if (!CondExpr.isUsable())
+ return StmtError();
+
+ // For incr-statement:
+ // \code{c}
+ // ++.tile.iv
+ // \endcode
+ ExprResult IncrStmt = SemaRef.BuildUnaryOp(
+ CurScope, SourceHelper.Inc->getExprLoc(), UO_PreInc, MakePermutedRef());
+ if (!IncrStmt.isUsable())
+ return StmtError();
+
+ SmallVector<Stmt *, 4> BodyParts(SourceHelper.Updates.begin(),
+ SourceHelper.Updates.end());
+ if (auto *SourceCXXFor = dyn_cast<CXXForRangeStmt>(SourceLoopStmt))
+ BodyParts.push_back(SourceCXXFor->getLoopVarStmt());
+ BodyParts.push_back(Inner);
+ Inner = CompoundStmt::Create(Context, BodyParts, FPOptionsOverride(),
+ Inner->getBeginLoc(), Inner->getEndLoc());
+ Inner = new (Context) ForStmt(
+ Context, InitStmt.get(), CondExpr.get(), nullptr, IncrStmt.get(), Inner,
+ SourceHelper.Init->getBeginLoc(), SourceHelper.Init->getBeginLoc(),
+ SourceHelper.Inc->getEndLoc());
+ }
+
+ return OMPInterchangeDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, Inner,
+ buildPreInits(Context, PreInits));
+}
+
OMPClause *SemaOpenMP::ActOnOpenMPSingleExprClause(OpenMPClauseKind Kind,
Expr *Expr,
SourceLocation StartLoc,
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index c1a08da885507..8da35f522d8ff 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -9184,6 +9184,17 @@ TreeTransform<Derived>::TransformOMPReverseDirective(OMPReverseDirective *D) {
return Res;
}
+template <typename Derived>
+StmtResult TreeTransform<Derived>::TransformOMPInterchangeDirective(
+ OMPInterchangeDirective *D) {
+ DeclarationNameInfo DirName;
+ getDerived().getSema().OpenMP().StartOpenMPDSABlock(
+ D->getDirectiveKind(), DirName, nullptr, D->getBeginLoc());
+ StmtResult Res = getDerived().TransformOMPExecutableDirective(D);
+ getDerived().getSema().OpenMP().EndOpenMPDSABlock(Res.get());
+ return Res;
+}
+
template <typename Derived>
StmtResult
TreeTransform<Derived>::TransformOMPForDirective(OMPForDirective *D) {
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index ff72679f993e2..92e14473e7b51 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -2432,6 +2432,10 @@ void ASTStmtReader::VisitOMPReverseDirective(OMPReverseDirective *D) {
VisitOMPLoopTransformationDirective(D);
}
+void ASTStmtReader::VisitOMPInterchangeDirective(OMPInterchangeDirective *D) {
+ VisitOMPLoopTransformationDirective(D);
+}
+
void ASTStmtReader::VisitOMPForDirective(OMPForDirective *D) {
VisitOMPLoopDirective(D);
D->setHasCancel(Record.readBool());
@@ -3448,6 +3452,13 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) {
break;
}
+ case STMT_OMP_INTERCHANGE_DIRECTIVE: {
+ unsigned NumLoops = Record[ASTStmtReader::NumStmtFields];
+ unsigned NumClauses = Record[ASTStmtReader::NumStmtFields + 1];
+ S = OMPInterchangeDirective::CreateEmpty(Context, NumClauses, NumLoops);
+ break;
+ }
+
case STMT_OMP_FOR_DIRECTIVE: {
unsigned CollapsedNum = Record[ASTStmtReader::NumStmtFields];
unsigned NumClauses = Record[ASTStmtReader::NumStmtFields + 1];
diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp
index ffb09ece981e6..0ac8e1967e17c 100644
--- a/clang/lib/Serialization/ASTWriterStmt.cpp
+++ b/clang/lib/Serialization/ASTWriterStmt.cpp
@@ -2417,6 +2417,11 @@ void ASTStmtWriter::VisitOMPReverseDirective(OMPReverseDirective *D) {
Code = serialization::STMT_OMP_REVERSE_DIRECTIVE;
}
+void ASTStmtWriter::VisitOMPInterchangeDirective(OMPInterchangeDirective *D) {
+ VisitOMPLoopTransformationDirective(D);
+ Code = serialization::STMT_OMP_INTERCHANGE_DIRECTIVE;
+}
+
void ASTStmtWriter::VisitOMPForDirective(OMPForDirective *D) {
VisitOMPLoopDirective(D);
Record.writeBool(D->hasCancel());
diff --git a/clang/test/OpenMP/interchange_ast_print.cpp b/clang/test/OpenMP/interchange_ast_print.cpp
new file mode 100644
index 0000000000000..f8bf075cd300f
--- /dev/null
+++ b/clang/test/OpenMP/interchange_ast_print.cpp
@@ -0,0 +1,135 @@
+// Check no warnings/errors
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -fsyntax-only -verify %s
+// expected-no-diagnostics
+
+// Check AST and unparsing
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -ast-dump %s | FileCheck %s --check-prefix=DUMP
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -ast-print %s | FileCheck %s --check-prefix=PRINT
+
+// Check same results after serialization round-trip
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -emit-pch -o %t %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -include-pch %t -ast-dump-all %s | FileCheck %s --check-prefix=DUMP
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++20 -fopenmp -fopenmp-version=60 -include-pch %t -ast-print %s | FileCheck %s --check-prefix=PRINT
+
+#ifndef HEADER
+#define HEADER
+
+// placeholder for loop body code.
+extern "C" void body(...);
+
+// PRINT-LABEL: void foo1(
+// DUMP-LABEL: FunctionDecl {{.*}} foo1
+void foo1() {
+ // PRINT: #pragma omp interchange
+ // DUMP: OMPInterchangeDirective
+ #pragma omp interchange
+ // PRINT: for (int i = 7; i < 17; i += 3)
+ // DUMP-NEXT: ForStmt
+ for (int i = 7; i < 17; i += 3)
+ // PRINT: for (int j = 7; j < 17; j += 3)
+ // DUMP: ForStmt
+ for (int j = 7; j < 17; j += 3)
+ // PRINT: body(i, j);
+ // DUMP: CallExpr
+ body(i, j);
+}
+
+
+
+
+// PRINT-LABEL: void foo3(
+// DUMP-LABEL: FunctionDecl {{.*}} foo3
+void foo3() {
+ // PRINT: #pragma omp for collapse(3)
+ // DUMP: OMPForDirective
+ // DUMP-NEXT: OMPCollapseClause
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 3
+ // DUMP-NEXT: IntegerLiteral {{.*}} 3
+ // DUMP-NEXT: CapturedStmt
+ // DUMP-NEXT: CapturedDecl
+ #pragma omp for collapse(3)
+ // PRINT: #pragma omp interchange
+ // DUMP: OMPInterchangeDirective
+ #pragma omp interchange
+ // PRINT: for (int i = 7; i < 17; i += 1)
+ // DUMP-NEXT: ForStmt
+ for (int i = 7; i < 17; i += 1)
+ // PRINT: for (int j = 7; j < 17; j += 1)
+ // DUMP: ForStmt
+ for (int j = 7; j < 17; j += 1)
+ // PRINT: for (int k = 7; k < 17; k += 1)
+ // DUMP: ForStmt
+ for (int k = 7; k < 17; k += 1)
+ // PRINT: body(i, j, k);
+ // DUMP: CallExpr
+ body(i, j, k);
+}
+
+
+// PRINT-LABEL: void foo6(
+// DUMP-LABEL: FunctionTemplateDecl {{.*}} foo6
+template<int Tile>
+void foo6() {
+ // PRINT: #pragma omp interchange
+ // DUMP: OMPInterchangeDirective
+ #pragma omp interchange
+ // PRINT-NEXT: for (int i = 0; i < 11; i += 2)
+ // DUMP-NEXT: ForStmt
+ for (int i = 0; i < 11; i += 2)
+ // PRINT-NEXT: #pragma omp tile sizes(Tile)
+ // DUMP: OMPTileDirective
+ #pragma omp tile sizes(Tile)
+ // PRINT-NEXT: for (int j = 0; j < 13; j += 2)
+ // DUMP: ForStmt
+ for (int j = 0; j < 13; j += 2)
+ // PRINT-NEXT: body(i, j);
+ // DUMP: CallExpr
+ body(i, j);
+}
+
+// Also test instantiating the template.
+void tfoo6() {
+ foo6<32>();
+}
+
+
+// PRINT-LABEL: void foo7(
+// DUMP-LABEL: FunctionDecl {{.*}} foo7
+void foo7() {
+ double arr[128];
+ // PRINT: #pragma omp interchange
+ // DUMP: OMPInterchangeDirective
+ #pragma omp interchange
+ // PRINT-NEXT: for (double c = 42; auto &&v : arr)
+ // DUMP-NEXT: CXXForRangeStmt
+ for (double c = 42; auto &&v : arr)
+ // PRINT-NEXT: for (int i = 0; i < 42; i += 2)
+ // DUMP: ForStmt
+ for (int i = 0; i < 42; i += 2)
+ // PRINT-NEXT: body(c, v, i);
+ // DUMP: CallExpr
+ body(c, v, i);
+}
+
+
+// PRINT-LABEL: void foo8(
+// DUMP-LABEL: FunctionDecl {{.*}} foo8
+void foo8() {
+ double arr[128];
+ // PRINT: #pragma omp interchange
+ // DUMP: OMPInterchangeDirective
+ #pragma omp interchange
+ // PRINT-NEXT: for (int i = 0; i < 42; i += 2)
+ // DUMP-NEXT: ForStmt
+ for (int i = 0; i < 42; i += 2)
+ // PRINT-NEXT: for (double c = 42; auto &&v : arr)
+ // DUMP: CXXForRangeStmt
+ for (double c = 42; auto &&v : arr)
+ // PRINT-NEXT: body(i, c, v);
+ // DUMP: CallExpr
+ body(i, c, v);
+}
+
+#endif
+
diff --git a/clang/test/OpenMP/interchange_codegen.cpp b/clang/test/OpenMP/interchange_codegen.cpp
new file mode 100644
index 0000000000000..9c1782183cf98
--- /dev/null
+++ b/clang/test/OpenMP/interchange_codegen.cpp
@@ -0,0 +1,1990 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
+
+// expected-no-diagnostics
+
+// Check code generation
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
+
+// Check same results after serialization round-trip
+// FIXME: They should be exactly the same but currently differ in function order
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -emit-pch -o %t %s
+// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -std=c++20 -fclang-abi-compat=latest -fopenmp -fopenmp-version=60 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2
+
+#ifndef HEADER
+#define HEADER
+
+// placeholder for loop body code.
+extern "C" void body(...) {}
+
+
+
+
+extern "C" void foo2(int start1, int start2, int end1, int end2, int step1, int step2) {
+#pragma omp interchange
+ for (int i = start1; i < end1; i += step1)
+ for (int j = start2; j < end2; j += step2)
+ body(i, j);
+}
+
+
+extern "C" void foo3() {
+#pragma omp for
+#pragma omp interchange
+ for (int i = 7; i < 17; i += 3)
+ for (int j = 7; j < 17; j += 3)
+ body(i, j);
+}
+
+
+extern "C" void foo4() {
+#pragma omp for collapse(2)
+ for (int k = 7; k < 17; k += 3)
+#pragma omp interchange
+ for (int i = 7; i < 17; i += 3)
+ for (int j = 7; j < 17; j += 3)
+ body(i, j);
+}
+
+
+extern "C" void foo6() {
+#pragma omp for collapse(4)
+ for (int i = 7; i < 17; i += 3)
+#pragma omp interchange
+ for (int j = 7; j < 17; j += 3)
+ for (int k = 7; k < 17; k += 3)
+ for (int l = 7; l < 17; l += 3)
+ body(i, j, k, l);
+}
+
+
+extern "C" void foo9() {
+ double arr[128];
+ #pragma omp interchange
+ for (double c = 42; auto && v : arr)
+ for (int i = 0; i < 42; i += 2)
+ body(c, v, i);
+}
+
+
+extern "C" void foo10() {
+ double A[128], B[16];
+ #pragma omp for collapse(4)
+ for (int i = 0; i < 128; ++i)
+ #pragma omp interchange
+ for (double c = 42; auto aa : A)
+ for (double d = 42; auto &bb : B)
+ for (int j = 0; j < 128; ++j)
+ body(i, c, aa, d, bb, j);
+}
+
+#endif /* HEADER */
+
+// CHECK1-LABEL: define {{[^@]+}}@body
+// CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo2
+// CHECK1-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]
+// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP8]], ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]]
+// CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 1
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]]
+// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 1
+// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 1
+// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]]
+// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD15]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND16:%.*]]
+// CHECK1: for.cond16:
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
+// CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 1
+// CHECK1-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]]
+// CHECK1-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body19:
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]]
+// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]]
+// CHECK1-NEXT: store i32 [[ADD21]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
+// CHECK1: for.inc22:
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
+// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK1: for.end24:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo3
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
+// CHECK1-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 3
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 4
+// CHECK1-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 3
+// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo4
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 15
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 4
+// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]
+// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
+// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 3
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 4
+// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 3
+// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]
+// CHECK1-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo6
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[K]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 255
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 64
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 64
+// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 64
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]]
+// CHECK1-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 16
+// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1
+// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
+// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 64
+// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 64
+// CHECK1-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 64
+// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 64
+// CHECK1-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]]
+// CHECK1-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 16
+// CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 16
+// CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]]
+// CHECK1-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 4
+// CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 1
+// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]]
+// CHECK1-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 64
+// CHECK1-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 64
+// CHECK1-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 64
+// CHECK1-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 64
+// CHECK1-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]]
+// CHECK1-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 16
+// CHECK1-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 16
+// CHECK1-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 64
+// CHECK1-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 64
+// CHECK1-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 64
+// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 64
+// CHECK1-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]]
+// CHECK1-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 16
+// CHECK1-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 16
+// CHECK1-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]]
+// CHECK1-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 4
+// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 4
+// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]]
+// CHECK1-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 3
+// CHECK1-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]]
+// CHECK1-NEXT: store i32 [[ADD44]], ptr [[L]], align 4
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 4
+// CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 3
+// CHECK1-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]]
+// CHECK1-NEXT: store i32 [[ADD46]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 4
+// CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 3
+// CHECK1-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]]
+// CHECK1-NEXT: store i32 [[ADD48]], ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 1
+// CHECK1-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo9
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[ARR:%.*]] = alloca [128 x double], align 16
+// CHECK1-NEXT: [[C:%.*]] = alloca double, align 8
+// CHECK1-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__END2:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[V:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8
+// CHECK1-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0
+// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
+// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
+// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK1-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 21
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2
+// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK1-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK1: for.cond7:
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 1
+// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]]
+// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body10:
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK1-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 1
+// CHECK1-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]]
+// CHECK1-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8
+// CHECK1-NEXT: store ptr [[TMP12]], ptr [[V]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
+// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK1: for.inc13:
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
+// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1: for.end15:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@foo10
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[A:%.*]] = alloca [128 x double], align 16
+// CHECK1-NEXT: [[B:%.*]] = alloca [16 x double], align 16
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[C:%.*]] = alloca double, align 8
+// CHECK1-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__END3:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[D:%.*]] = alloca double, align 8
+// CHECK1-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__END4:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I37:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[BB:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[AA:%.*]] = alloca double, align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8
+// CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
+// CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
+// CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8
+// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK1-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i64
+// CHECK1-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK1-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK1-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK1-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK1-NEXT: store double 4.200000e+01, ptr [[D]], align 8
+// CHECK1-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0
+// CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16
+// CHECK1-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0
+// CHECK1-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8
+// CHECK1-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK1-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i64
+// CHECK1-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i64
+// CHECK1-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]]
+// CHECK1-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 8
+// CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 1
+// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 1
+// CHECK1-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 1
+// CHECK1-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 1
+// CHECK1-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 8
+// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 1
+// CHECK1-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 1
+// CHECK1-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 0
+// CHECK1-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 1
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 0
+// CHECK1-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 1
+// CHECK1-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]]
+// CHECK1-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 128
+// CHECK1-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 1
+// CHECK1-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 8
+// CHECK1-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK1: land.lhs.true:
+// CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]]
+// CHECK1-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.then:
+// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK1-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK1-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]
+// CHECK1-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]
+// CHECK1-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 0
+// CHECK1-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 1
+// CHECK1-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 0
+// CHECK1-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 1
+// CHECK1-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]]
+// CHECK1-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 128
+// CHECK1-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]]
+// CHECK1-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 1
+// CHECK1-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]]
+// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i32
+// CHECK1-NEXT: store i32 [[CONV]], ptr [[I37]], align 4
+// CHECK1-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 0
+// CHECK1-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 1
+// CHECK1-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]]
+// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 0
+// CHECK1-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 1
+// CHECK1-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]]
+// CHECK1-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 128
+// CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]]
+// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 0
+// CHECK1-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 1
+// CHECK1-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]]
+// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 0
+// CHECK1-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 1
+// CHECK1-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]]
+// CHECK1-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 128
+// CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]]
+// CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]]
+// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 0
+// CHECK1-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 1
+// CHECK1-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]]
+// CHECK1-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 128
+// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]]
+// CHECK1-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 1
+// CHECK1-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]]
+// CHECK1-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8
+// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 0
+// CHECK1-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 1
+// CHECK1-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]]
+// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 0
+// CHECK1-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 1
+// CHECK1-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]]
+// CHECK1-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 128
+// CHECK1-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]]
+// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 0
+// CHECK1-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 1
+// CHECK1-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]]
+// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 0
+// CHECK1-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 1
+// CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]]
+// CHECK1-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 128
+// CHECK1-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]]
+// CHECK1-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]]
+// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 0
+// CHECK1-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 1
+// CHECK1-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]]
+// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 0
+// CHECK1-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 1
+// CHECK1-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]]
+// CHECK1-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 128
+// CHECK1-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]]
+// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 0
+// CHECK1-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 1
+// CHECK1-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]]
+// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 0
+// CHECK1-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 1
+// CHECK1-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]]
+// CHECK1-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 128
+// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]]
+// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]]
+// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 0
+// CHECK1-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 1
+// CHECK1-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]]
+// CHECK1-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 128
+// CHECK1-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]]
+// CHECK1-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 0
+// CHECK1-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 1
+// CHECK1-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]]
+// CHECK1-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 128
+// CHECK1-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]]
+// CHECK1-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]]
+// CHECK1-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 128
+// CHECK1-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 1
+// CHECK1-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]]
+// CHECK1-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8
+// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 0
+// CHECK1-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 1
+// CHECK1-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]]
+// CHECK1-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 0
+// CHECK1-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 1
+// CHECK1-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]]
+// CHECK1-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 128
+// CHECK1-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]]
+// CHECK1-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 0
+// CHECK1-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 1
+// CHECK1-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]]
+// CHECK1-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 0
+// CHECK1-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 1
+// CHECK1-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]]
+// CHECK1-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 128
+// CHECK1-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]]
+// CHECK1-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 0
+// CHECK1-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 1
+// CHECK1-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]]
+// CHECK1-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 0
+// CHECK1-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 1
+// CHECK1-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]]
+// CHECK1-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 128
+// CHECK1-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]]
+// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 0
+// CHECK1-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 1
+// CHECK1-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]]
+// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 0
+// CHECK1-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 1
+// CHECK1-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]]
+// CHECK1-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 128
+// CHECK1-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]]
+// CHECK1-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]]
+// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 0
+// CHECK1-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 1
+// CHECK1-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]]
+// CHECK1-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 128
+// CHECK1-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]]
+// CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 0
+// CHECK1-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 1
+// CHECK1-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]]
+// CHECK1-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 128
+// CHECK1-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]]
+// CHECK1-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]]
+// CHECK1-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 0
+// CHECK1-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 1
+// CHECK1-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]]
+// CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 0
+// CHECK1-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 1
+// CHECK1-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]]
+// CHECK1-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 128
+// CHECK1-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]]
+// CHECK1-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 0
+// CHECK1-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 1
+// CHECK1-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]]
+// CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 0
+// CHECK1-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 1
+// CHECK1-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]]
+// CHECK1-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 128
+// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]]
+// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]]
+// CHECK1-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 0
+// CHECK1-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 1
+// CHECK1-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]]
+// CHECK1-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 0
+// CHECK1-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 1
+// CHECK1-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]]
+// CHECK1-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 128
+// CHECK1-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]]
+// CHECK1-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK1-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 0
+// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 1
+// CHECK1-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]]
+// CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 0
+// CHECK1-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 1
+// CHECK1-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]]
+// CHECK1-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 128
+// CHECK1-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]]
+// CHECK1-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]]
+// CHECK1-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 0
+// CHECK1-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 1
+// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]]
+// CHECK1-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 128
+// CHECK1-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]]
+// CHECK1-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK1-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 0
+// CHECK1-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 1
+// CHECK1-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]]
+// CHECK1-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 128
+// CHECK1-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]]
+// CHECK1-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]]
+// CHECK1-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 128
+// CHECK1-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 128
+// CHECK1-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]]
+// CHECK1-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 1
+// CHECK1-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]]
+// CHECK1-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i32
+// CHECK1-NEXT: store i32 [[CONV220]], ptr [[J40]], align 4
+// CHECK1-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK1-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8
+// CHECK1-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 1
+// CHECK1-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]]
+// CHECK1-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 8
+// CHECK1-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 8
+// CHECK1-NEXT: store ptr [[TMP81]], ptr [[BB]], align 8
+// CHECK1-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK1-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8
+// CHECK1-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 1
+// CHECK1-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]]
+// CHECK1-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 8
+// CHECK1-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 8
+// CHECK1-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 8
+// CHECK1-NEXT: store double [[TMP85]], ptr [[AA]], align 8
+// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 4
+// CHECK1-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8
+// CHECK1-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8
+// CHECK1-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8
+// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8
+// CHECK1-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8
+// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 1
+// CHECK1-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.end:
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@body
+// CHECK2-SAME: (...) #[[ATTR0:[0-9]+]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo10
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[A:%.*]] = alloca [128 x double], align 16
+// CHECK2-NEXT: [[B:%.*]] = alloca [16 x double], align 16
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[C:%.*]] = alloca double, align 8
+// CHECK2-NEXT: [[__RANGE3:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__END3:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__BEGIN3:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[D:%.*]] = alloca double, align 8
+// CHECK2-NEXT: [[__RANGE4:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__END4:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__BEGIN4:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_28:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN4:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN3:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I37:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV___BEGIN438:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN339:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[J40:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[BB:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[AA:%.*]] = alloca double, align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
+// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8
+// CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
+// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
+// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8
+// CHECK2-NEXT: store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_6]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
+// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP6]] to i64
+// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK2-NEXT: [[SUB8:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK2-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK2-NEXT: store double 4.200000e+01, ptr [[D]], align 8
+// CHECK2-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0
+// CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16
+// CHECK2-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8
+// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8
+// CHECK2-NEXT: store ptr [[TMP10]], ptr [[DOTCAPTURE_EXPR_14]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_14]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK2-NEXT: [[SUB_PTR_LHS_CAST16:%.*]] = ptrtoint ptr [[TMP11]] to i64
+// CHECK2-NEXT: [[SUB_PTR_RHS_CAST17:%.*]] = ptrtoint ptr [[TMP12]] to i64
+// CHECK2-NEXT: [[SUB_PTR_SUB18:%.*]] = sub i64 [[SUB_PTR_LHS_CAST16]], [[SUB_PTR_RHS_CAST17]]
+// CHECK2-NEXT: [[SUB_PTR_DIV19:%.*]] = sdiv exact i64 [[SUB_PTR_SUB18]], 8
+// CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 [[SUB_PTR_DIV19]], 1
+// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i64 [[SUB20]], 1
+// CHECK2-NEXT: [[DIV22:%.*]] = sdiv i64 [[ADD21]], 1
+// CHECK2-NEXT: [[SUB23:%.*]] = sub nsw i64 [[DIV22]], 1
+// CHECK2-NEXT: store i64 [[SUB23]], ptr [[DOTCAPTURE_EXPR_15]], align 8
+// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_15]], align 8
+// CHECK2-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP13]], 1
+// CHECK2-NEXT: store i64 [[ADD25]], ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_7]], align 8
+// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i64 [[TMP14]], 1
+// CHECK2-NEXT: store i64 [[ADD27]], ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP15]], 0
+// CHECK2-NEXT: [[DIV30:%.*]] = sdiv i64 [[SUB29]], 1
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 128, [[DIV30]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP16]], 0
+// CHECK2-NEXT: [[DIV32:%.*]] = sdiv i64 [[SUB31]], 1
+// CHECK2-NEXT: [[MUL33:%.*]] = mul nsw i64 [[MUL]], [[DIV32]]
+// CHECK2-NEXT: [[MUL34:%.*]] = mul nsw i64 [[MUL33]], 128
+// CHECK2-NEXT: [[SUB35:%.*]] = sub nsw i64 [[MUL34]], 1
+// CHECK2-NEXT: store i64 [[SUB35]], ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_0_IV___BEGIN4]], align 8
+// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN3]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i64 0, [[TMP17]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK2: land.lhs.true:
+// CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[CMP36:%.*]] = icmp slt i64 0, [[TMP18]]
+// CHECK2-NEXT: br i1 [[CMP36]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.then:
+// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK2-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK2-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]
+// CHECK2-NEXT: br i1 [[CMP41]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_28]], align 8
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[CMP42:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]
+// CHECK2-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB43:%.*]] = sub nsw i64 [[TMP28]], 0
+// CHECK2-NEXT: [[DIV44:%.*]] = sdiv i64 [[SUB43]], 1
+// CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i64 1, [[DIV44]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB46:%.*]] = sub nsw i64 [[TMP29]], 0
+// CHECK2-NEXT: [[DIV47:%.*]] = sdiv i64 [[SUB46]], 1
+// CHECK2-NEXT: [[MUL48:%.*]] = mul nsw i64 [[MUL45]], [[DIV47]]
+// CHECK2-NEXT: [[MUL49:%.*]] = mul nsw i64 [[MUL48]], 128
+// CHECK2-NEXT: [[DIV50:%.*]] = sdiv i64 [[TMP27]], [[MUL49]]
+// CHECK2-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV50]], 1
+// CHECK2-NEXT: [[ADD52:%.*]] = add nsw i64 0, [[MUL51]]
+// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[ADD52]] to i32
+// CHECK2-NEXT: store i32 [[CONV]], ptr [[I37]], align 4
+// CHECK2-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB53:%.*]] = sub nsw i64 [[TMP32]], 0
+// CHECK2-NEXT: [[DIV54:%.*]] = sdiv i64 [[SUB53]], 1
+// CHECK2-NEXT: [[MUL55:%.*]] = mul nsw i64 1, [[DIV54]]
+// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB56:%.*]] = sub nsw i64 [[TMP33]], 0
+// CHECK2-NEXT: [[DIV57:%.*]] = sdiv i64 [[SUB56]], 1
+// CHECK2-NEXT: [[MUL58:%.*]] = mul nsw i64 [[MUL55]], [[DIV57]]
+// CHECK2-NEXT: [[MUL59:%.*]] = mul nsw i64 [[MUL58]], 128
+// CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP31]], [[MUL59]]
+// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB61:%.*]] = sub nsw i64 [[TMP34]], 0
+// CHECK2-NEXT: [[DIV62:%.*]] = sdiv i64 [[SUB61]], 1
+// CHECK2-NEXT: [[MUL63:%.*]] = mul nsw i64 1, [[DIV62]]
+// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB64:%.*]] = sub nsw i64 [[TMP35]], 0
+// CHECK2-NEXT: [[DIV65:%.*]] = sdiv i64 [[SUB64]], 1
+// CHECK2-NEXT: [[MUL66:%.*]] = mul nsw i64 [[MUL63]], [[DIV65]]
+// CHECK2-NEXT: [[MUL67:%.*]] = mul nsw i64 [[MUL66]], 128
+// CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[MUL67]]
+// CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP30]], [[MUL68]]
+// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB70:%.*]] = sub nsw i64 [[TMP36]], 0
+// CHECK2-NEXT: [[DIV71:%.*]] = sdiv i64 [[SUB70]], 1
+// CHECK2-NEXT: [[MUL72:%.*]] = mul nsw i64 1, [[DIV71]]
+// CHECK2-NEXT: [[MUL73:%.*]] = mul nsw i64 [[MUL72]], 128
+// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[SUB69]], [[MUL73]]
+// CHECK2-NEXT: [[MUL75:%.*]] = mul nsw i64 [[DIV74]], 1
+// CHECK2-NEXT: [[ADD76:%.*]] = add nsw i64 0, [[MUL75]]
+// CHECK2-NEXT: store i64 [[ADD76]], ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8
+// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB77:%.*]] = sub nsw i64 [[TMP39]], 0
+// CHECK2-NEXT: [[DIV78:%.*]] = sdiv i64 [[SUB77]], 1
+// CHECK2-NEXT: [[MUL79:%.*]] = mul nsw i64 1, [[DIV78]]
+// CHECK2-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP40]], 0
+// CHECK2-NEXT: [[DIV81:%.*]] = sdiv i64 [[SUB80]], 1
+// CHECK2-NEXT: [[MUL82:%.*]] = mul nsw i64 [[MUL79]], [[DIV81]]
+// CHECK2-NEXT: [[MUL83:%.*]] = mul nsw i64 [[MUL82]], 128
+// CHECK2-NEXT: [[DIV84:%.*]] = sdiv i64 [[TMP38]], [[MUL83]]
+// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB85:%.*]] = sub nsw i64 [[TMP41]], 0
+// CHECK2-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB85]], 1
+// CHECK2-NEXT: [[MUL87:%.*]] = mul nsw i64 1, [[DIV86]]
+// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB88:%.*]] = sub nsw i64 [[TMP42]], 0
+// CHECK2-NEXT: [[DIV89:%.*]] = sdiv i64 [[SUB88]], 1
+// CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[MUL87]], [[DIV89]]
+// CHECK2-NEXT: [[MUL91:%.*]] = mul nsw i64 [[MUL90]], 128
+// CHECK2-NEXT: [[MUL92:%.*]] = mul nsw i64 [[DIV84]], [[MUL91]]
+// CHECK2-NEXT: [[SUB93:%.*]] = sub nsw i64 [[TMP37]], [[MUL92]]
+// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB94:%.*]] = sub nsw i64 [[TMP45]], 0
+// CHECK2-NEXT: [[DIV95:%.*]] = sdiv i64 [[SUB94]], 1
+// CHECK2-NEXT: [[MUL96:%.*]] = mul nsw i64 1, [[DIV95]]
+// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB97:%.*]] = sub nsw i64 [[TMP46]], 0
+// CHECK2-NEXT: [[DIV98:%.*]] = sdiv i64 [[SUB97]], 1
+// CHECK2-NEXT: [[MUL99:%.*]] = mul nsw i64 [[MUL96]], [[DIV98]]
+// CHECK2-NEXT: [[MUL100:%.*]] = mul nsw i64 [[MUL99]], 128
+// CHECK2-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP44]], [[MUL100]]
+// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB102:%.*]] = sub nsw i64 [[TMP47]], 0
+// CHECK2-NEXT: [[DIV103:%.*]] = sdiv i64 [[SUB102]], 1
+// CHECK2-NEXT: [[MUL104:%.*]] = mul nsw i64 1, [[DIV103]]
+// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB105:%.*]] = sub nsw i64 [[TMP48]], 0
+// CHECK2-NEXT: [[DIV106:%.*]] = sdiv i64 [[SUB105]], 1
+// CHECK2-NEXT: [[MUL107:%.*]] = mul nsw i64 [[MUL104]], [[DIV106]]
+// CHECK2-NEXT: [[MUL108:%.*]] = mul nsw i64 [[MUL107]], 128
+// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV101]], [[MUL108]]
+// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP43]], [[MUL109]]
+// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB111:%.*]] = sub nsw i64 [[TMP49]], 0
+// CHECK2-NEXT: [[DIV112:%.*]] = sdiv i64 [[SUB111]], 1
+// CHECK2-NEXT: [[MUL113:%.*]] = mul nsw i64 1, [[DIV112]]
+// CHECK2-NEXT: [[MUL114:%.*]] = mul nsw i64 [[MUL113]], 128
+// CHECK2-NEXT: [[DIV115:%.*]] = sdiv i64 [[SUB110]], [[MUL114]]
+// CHECK2-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB116:%.*]] = sub nsw i64 [[TMP50]], 0
+// CHECK2-NEXT: [[DIV117:%.*]] = sdiv i64 [[SUB116]], 1
+// CHECK2-NEXT: [[MUL118:%.*]] = mul nsw i64 1, [[DIV117]]
+// CHECK2-NEXT: [[MUL119:%.*]] = mul nsw i64 [[MUL118]], 128
+// CHECK2-NEXT: [[MUL120:%.*]] = mul nsw i64 [[DIV115]], [[MUL119]]
+// CHECK2-NEXT: [[SUB121:%.*]] = sub nsw i64 [[SUB93]], [[MUL120]]
+// CHECK2-NEXT: [[DIV122:%.*]] = sdiv i64 [[SUB121]], 128
+// CHECK2-NEXT: [[MUL123:%.*]] = mul nsw i64 [[DIV122]], 1
+// CHECK2-NEXT: [[ADD124:%.*]] = add nsw i64 0, [[MUL123]]
+// CHECK2-NEXT: store i64 [[ADD124]], ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8
+// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP53:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB125:%.*]] = sub nsw i64 [[TMP53]], 0
+// CHECK2-NEXT: [[DIV126:%.*]] = sdiv i64 [[SUB125]], 1
+// CHECK2-NEXT: [[MUL127:%.*]] = mul nsw i64 1, [[DIV126]]
+// CHECK2-NEXT: [[TMP54:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB128:%.*]] = sub nsw i64 [[TMP54]], 0
+// CHECK2-NEXT: [[DIV129:%.*]] = sdiv i64 [[SUB128]], 1
+// CHECK2-NEXT: [[MUL130:%.*]] = mul nsw i64 [[MUL127]], [[DIV129]]
+// CHECK2-NEXT: [[MUL131:%.*]] = mul nsw i64 [[MUL130]], 128
+// CHECK2-NEXT: [[DIV132:%.*]] = sdiv i64 [[TMP52]], [[MUL131]]
+// CHECK2-NEXT: [[TMP55:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB133:%.*]] = sub nsw i64 [[TMP55]], 0
+// CHECK2-NEXT: [[DIV134:%.*]] = sdiv i64 [[SUB133]], 1
+// CHECK2-NEXT: [[MUL135:%.*]] = mul nsw i64 1, [[DIV134]]
+// CHECK2-NEXT: [[TMP56:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP56]], 0
+// CHECK2-NEXT: [[DIV137:%.*]] = sdiv i64 [[SUB136]], 1
+// CHECK2-NEXT: [[MUL138:%.*]] = mul nsw i64 [[MUL135]], [[DIV137]]
+// CHECK2-NEXT: [[MUL139:%.*]] = mul nsw i64 [[MUL138]], 128
+// CHECK2-NEXT: [[MUL140:%.*]] = mul nsw i64 [[DIV132]], [[MUL139]]
+// CHECK2-NEXT: [[SUB141:%.*]] = sub nsw i64 [[TMP51]], [[MUL140]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP58:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP59:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB142:%.*]] = sub nsw i64 [[TMP59]], 0
+// CHECK2-NEXT: [[DIV143:%.*]] = sdiv i64 [[SUB142]], 1
+// CHECK2-NEXT: [[MUL144:%.*]] = mul nsw i64 1, [[DIV143]]
+// CHECK2-NEXT: [[TMP60:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB145:%.*]] = sub nsw i64 [[TMP60]], 0
+// CHECK2-NEXT: [[DIV146:%.*]] = sdiv i64 [[SUB145]], 1
+// CHECK2-NEXT: [[MUL147:%.*]] = mul nsw i64 [[MUL144]], [[DIV146]]
+// CHECK2-NEXT: [[MUL148:%.*]] = mul nsw i64 [[MUL147]], 128
+// CHECK2-NEXT: [[DIV149:%.*]] = sdiv i64 [[TMP58]], [[MUL148]]
+// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB150:%.*]] = sub nsw i64 [[TMP61]], 0
+// CHECK2-NEXT: [[DIV151:%.*]] = sdiv i64 [[SUB150]], 1
+// CHECK2-NEXT: [[MUL152:%.*]] = mul nsw i64 1, [[DIV151]]
+// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB153:%.*]] = sub nsw i64 [[TMP62]], 0
+// CHECK2-NEXT: [[DIV154:%.*]] = sdiv i64 [[SUB153]], 1
+// CHECK2-NEXT: [[MUL155:%.*]] = mul nsw i64 [[MUL152]], [[DIV154]]
+// CHECK2-NEXT: [[MUL156:%.*]] = mul nsw i64 [[MUL155]], 128
+// CHECK2-NEXT: [[MUL157:%.*]] = mul nsw i64 [[DIV149]], [[MUL156]]
+// CHECK2-NEXT: [[SUB158:%.*]] = sub nsw i64 [[TMP57]], [[MUL157]]
+// CHECK2-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB159:%.*]] = sub nsw i64 [[TMP63]], 0
+// CHECK2-NEXT: [[DIV160:%.*]] = sdiv i64 [[SUB159]], 1
+// CHECK2-NEXT: [[MUL161:%.*]] = mul nsw i64 1, [[DIV160]]
+// CHECK2-NEXT: [[MUL162:%.*]] = mul nsw i64 [[MUL161]], 128
+// CHECK2-NEXT: [[DIV163:%.*]] = sdiv i64 [[SUB158]], [[MUL162]]
+// CHECK2-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB164:%.*]] = sub nsw i64 [[TMP64]], 0
+// CHECK2-NEXT: [[DIV165:%.*]] = sdiv i64 [[SUB164]], 1
+// CHECK2-NEXT: [[MUL166:%.*]] = mul nsw i64 1, [[DIV165]]
+// CHECK2-NEXT: [[MUL167:%.*]] = mul nsw i64 [[MUL166]], 128
+// CHECK2-NEXT: [[MUL168:%.*]] = mul nsw i64 [[DIV163]], [[MUL167]]
+// CHECK2-NEXT: [[SUB169:%.*]] = sub nsw i64 [[SUB141]], [[MUL168]]
+// CHECK2-NEXT: [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP66:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP67:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB170:%.*]] = sub nsw i64 [[TMP67]], 0
+// CHECK2-NEXT: [[DIV171:%.*]] = sdiv i64 [[SUB170]], 1
+// CHECK2-NEXT: [[MUL172:%.*]] = mul nsw i64 1, [[DIV171]]
+// CHECK2-NEXT: [[TMP68:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB173:%.*]] = sub nsw i64 [[TMP68]], 0
+// CHECK2-NEXT: [[DIV174:%.*]] = sdiv i64 [[SUB173]], 1
+// CHECK2-NEXT: [[MUL175:%.*]] = mul nsw i64 [[MUL172]], [[DIV174]]
+// CHECK2-NEXT: [[MUL176:%.*]] = mul nsw i64 [[MUL175]], 128
+// CHECK2-NEXT: [[DIV177:%.*]] = sdiv i64 [[TMP66]], [[MUL176]]
+// CHECK2-NEXT: [[TMP69:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB178:%.*]] = sub nsw i64 [[TMP69]], 0
+// CHECK2-NEXT: [[DIV179:%.*]] = sdiv i64 [[SUB178]], 1
+// CHECK2-NEXT: [[MUL180:%.*]] = mul nsw i64 1, [[DIV179]]
+// CHECK2-NEXT: [[TMP70:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB181:%.*]] = sub nsw i64 [[TMP70]], 0
+// CHECK2-NEXT: [[DIV182:%.*]] = sdiv i64 [[SUB181]], 1
+// CHECK2-NEXT: [[MUL183:%.*]] = mul nsw i64 [[MUL180]], [[DIV182]]
+// CHECK2-NEXT: [[MUL184:%.*]] = mul nsw i64 [[MUL183]], 128
+// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV177]], [[MUL184]]
+// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP65]], [[MUL185]]
+// CHECK2-NEXT: [[TMP71:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP72:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP73:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB187:%.*]] = sub nsw i64 [[TMP73]], 0
+// CHECK2-NEXT: [[DIV188:%.*]] = sdiv i64 [[SUB187]], 1
+// CHECK2-NEXT: [[MUL189:%.*]] = mul nsw i64 1, [[DIV188]]
+// CHECK2-NEXT: [[TMP74:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB190:%.*]] = sub nsw i64 [[TMP74]], 0
+// CHECK2-NEXT: [[DIV191:%.*]] = sdiv i64 [[SUB190]], 1
+// CHECK2-NEXT: [[MUL192:%.*]] = mul nsw i64 [[MUL189]], [[DIV191]]
+// CHECK2-NEXT: [[MUL193:%.*]] = mul nsw i64 [[MUL192]], 128
+// CHECK2-NEXT: [[DIV194:%.*]] = sdiv i64 [[TMP72]], [[MUL193]]
+// CHECK2-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_24]], align 8
+// CHECK2-NEXT: [[SUB195:%.*]] = sub nsw i64 [[TMP75]], 0
+// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB195]], 1
+// CHECK2-NEXT: [[MUL197:%.*]] = mul nsw i64 1, [[DIV196]]
+// CHECK2-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB198:%.*]] = sub nsw i64 [[TMP76]], 0
+// CHECK2-NEXT: [[DIV199:%.*]] = sdiv i64 [[SUB198]], 1
+// CHECK2-NEXT: [[MUL200:%.*]] = mul nsw i64 [[MUL197]], [[DIV199]]
+// CHECK2-NEXT: [[MUL201:%.*]] = mul nsw i64 [[MUL200]], 128
+// CHECK2-NEXT: [[MUL202:%.*]] = mul nsw i64 [[DIV194]], [[MUL201]]
+// CHECK2-NEXT: [[SUB203:%.*]] = sub nsw i64 [[TMP71]], [[MUL202]]
+// CHECK2-NEXT: [[TMP77:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB204:%.*]] = sub nsw i64 [[TMP77]], 0
+// CHECK2-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB204]], 1
+// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 1, [[DIV205]]
+// CHECK2-NEXT: [[MUL207:%.*]] = mul nsw i64 [[MUL206]], 128
+// CHECK2-NEXT: [[DIV208:%.*]] = sdiv i64 [[SUB203]], [[MUL207]]
+// CHECK2-NEXT: [[TMP78:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_26]], align 8
+// CHECK2-NEXT: [[SUB209:%.*]] = sub nsw i64 [[TMP78]], 0
+// CHECK2-NEXT: [[DIV210:%.*]] = sdiv i64 [[SUB209]], 1
+// CHECK2-NEXT: [[MUL211:%.*]] = mul nsw i64 1, [[DIV210]]
+// CHECK2-NEXT: [[MUL212:%.*]] = mul nsw i64 [[MUL211]], 128
+// CHECK2-NEXT: [[MUL213:%.*]] = mul nsw i64 [[DIV208]], [[MUL212]]
+// CHECK2-NEXT: [[SUB214:%.*]] = sub nsw i64 [[SUB186]], [[MUL213]]
+// CHECK2-NEXT: [[DIV215:%.*]] = sdiv i64 [[SUB214]], 128
+// CHECK2-NEXT: [[MUL216:%.*]] = mul nsw i64 [[DIV215]], 128
+// CHECK2-NEXT: [[SUB217:%.*]] = sub nsw i64 [[SUB169]], [[MUL216]]
+// CHECK2-NEXT: [[MUL218:%.*]] = mul nsw i64 [[SUB217]], 1
+// CHECK2-NEXT: [[ADD219:%.*]] = add nsw i64 0, [[MUL218]]
+// CHECK2-NEXT: [[CONV220:%.*]] = trunc i64 [[ADD219]] to i32
+// CHECK2-NEXT: store i32 [[CONV220]], ptr [[J40]], align 4
+// CHECK2-NEXT: [[TMP79:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_12]], align 8
+// CHECK2-NEXT: [[TMP80:%.*]] = load i64, ptr [[DOTPERMUTED_0_IV___BEGIN438]], align 8
+// CHECK2-NEXT: [[MUL221:%.*]] = mul nsw i64 [[TMP80]], 1
+// CHECK2-NEXT: [[ADD_PTR222:%.*]] = getelementptr inbounds double, ptr [[TMP79]], i64 [[MUL221]]
+// CHECK2-NEXT: store ptr [[ADD_PTR222]], ptr [[__BEGIN4]], align 8
+// CHECK2-NEXT: [[TMP81:%.*]] = load ptr, ptr [[__BEGIN4]], align 8
+// CHECK2-NEXT: store ptr [[TMP81]], ptr [[BB]], align 8
+// CHECK2-NEXT: [[TMP82:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP83:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN339]], align 8
+// CHECK2-NEXT: [[MUL223:%.*]] = mul nsw i64 [[TMP83]], 1
+// CHECK2-NEXT: [[ADD_PTR224:%.*]] = getelementptr inbounds double, ptr [[TMP82]], i64 [[MUL223]]
+// CHECK2-NEXT: store ptr [[ADD_PTR224]], ptr [[__BEGIN3]], align 8
+// CHECK2-NEXT: [[TMP84:%.*]] = load ptr, ptr [[__BEGIN3]], align 8
+// CHECK2-NEXT: [[TMP85:%.*]] = load double, ptr [[TMP84]], align 8
+// CHECK2-NEXT: store double [[TMP85]], ptr [[AA]], align 8
+// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[I37]], align 4
+// CHECK2-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8
+// CHECK2-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8
+// CHECK2-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8
+// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8
+// CHECK2-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8
+// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP93:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[ADD225:%.*]] = add nsw i64 [[TMP93]], 1
+// CHECK2-NEXT: store i64 [[ADD225]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.end:
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo2
+// CHECK2-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[START1_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[START2_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[END1_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[END2_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[STEP1_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[STEP2_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[START1]], ptr [[START1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[START2]], ptr [[START2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[END1]], ptr [[END1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[END2]], ptr [[END2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[STEP1]], ptr [[STEP1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[STEP2]], ptr [[STEP2_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP1_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP6]]
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP7]]
+// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP8]], ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[START2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[END2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[STEP2_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB9:%.*]] = sub i32 [[TMP12]], [[TMP13]]
+// CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[SUB9]], 1
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[SUB10]], [[TMP14]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV12:%.*]] = udiv i32 [[ADD11]], [[TMP15]]
+// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV12]], 1
+// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP17]], 1
+// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP16]], [[ADD14]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], [[TMP20]]
+// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP18]], [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD15]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND16:%.*]]
+// CHECK2: for.cond16:
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
+// CHECK2-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], 1
+// CHECK2-NEXT: [[CMP18:%.*]] = icmp ult i32 [[TMP21]], [[ADD17]]
+// CHECK2-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body19:
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[MUL20:%.*]] = mul i32 [[TMP24]], [[TMP25]]
+// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP23]], [[MUL20]]
+// CHECK2-NEXT: store i32 [[ADD21]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP26]], i32 noundef [[TMP27]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
+// CHECK2: for.inc22:
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
+// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK2: for.end24:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo3
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP7]], 3
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 7, [[MUL2]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 4
+// CHECK2-NEXT: br i1 [[CMP4]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP9]], 3
+// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 7, [[MUL5]]
+// CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP10]], i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo4
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 15, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 15
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 15, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 4
+// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]
+// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
+// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
+// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP9]], 3
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 4
+// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP11]], 3
+// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]
+// CHECK2-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo6
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV_J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[L:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[K]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 255, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 255
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 255, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 64
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[TMP8]], 64
+// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[DIV5]], 64
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL6]]
+// CHECK2-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 16
+// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1
+// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
+// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTPERMUTED_0_IV_K]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV10:%.*]] = sdiv i32 [[TMP10]], 64
+// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i32 [[DIV10]], 64
+// CHECK2-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP9]], [[MUL11]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV13:%.*]] = sdiv i32 [[TMP12]], 64
+// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[DIV13]], 64
+// CHECK2-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP11]], [[MUL14]]
+// CHECK2-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 16
+// CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 16
+// CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i32 [[SUB12]], [[MUL17]]
+// CHECK2-NEXT: [[DIV19:%.*]] = sdiv i32 [[SUB18]], 4
+// CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[DIV19]], 1
+// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]]
+// CHECK2-NEXT: store i32 [[ADD21]], ptr [[DOTPERMUTED_1_IV_J]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV22:%.*]] = sdiv i32 [[TMP14]], 64
+// CHECK2-NEXT: [[MUL23:%.*]] = mul nsw i32 [[DIV22]], 64
+// CHECK2-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP13]], [[MUL23]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV25:%.*]] = sdiv i32 [[TMP16]], 64
+// CHECK2-NEXT: [[MUL26:%.*]] = mul nsw i32 [[DIV25]], 64
+// CHECK2-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP15]], [[MUL26]]
+// CHECK2-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 16
+// CHECK2-NEXT: [[MUL29:%.*]] = mul nsw i32 [[DIV28]], 16
+// CHECK2-NEXT: [[SUB30:%.*]] = sub nsw i32 [[SUB24]], [[MUL29]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV31:%.*]] = sdiv i32 [[TMP18]], 64
+// CHECK2-NEXT: [[MUL32:%.*]] = mul nsw i32 [[DIV31]], 64
+// CHECK2-NEXT: [[SUB33:%.*]] = sub nsw i32 [[TMP17]], [[MUL32]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV34:%.*]] = sdiv i32 [[TMP20]], 64
+// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i32 [[DIV34]], 64
+// CHECK2-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP19]], [[MUL35]]
+// CHECK2-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 16
+// CHECK2-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 16
+// CHECK2-NEXT: [[SUB39:%.*]] = sub nsw i32 [[SUB33]], [[MUL38]]
+// CHECK2-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 4
+// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 4
+// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i32 [[SUB30]], [[MUL41]]
+// CHECK2-NEXT: [[MUL43:%.*]] = mul nsw i32 [[SUB42]], 3
+// CHECK2-NEXT: [[ADD44:%.*]] = add nsw i32 7, [[MUL43]]
+// CHECK2-NEXT: store i32 [[ADD44]], ptr [[L]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_K]], align 4
+// CHECK2-NEXT: [[MUL45:%.*]] = mul nsw i32 [[TMP21]], 3
+// CHECK2-NEXT: [[ADD46:%.*]] = add nsw i32 7, [[MUL45]]
+// CHECK2-NEXT: store i32 [[ADD46]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_J]], align 4
+// CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i32 [[TMP22]], 3
+// CHECK2-NEXT: [[ADD48:%.*]] = add nsw i32 7, [[MUL47]]
+// CHECK2-NEXT: store i32 [[ADD48]], ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[L]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP23]], i32 noundef [[TMP24]], i32 noundef [[TMP25]], i32 noundef [[TMP26]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[ADD49:%.*]] = add nsw i32 [[TMP27]], 1
+// CHECK2-NEXT: store i32 [[ADD49]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@foo9
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[ARR:%.*]] = alloca [128 x double], align 16
+// CHECK2-NEXT: [[C:%.*]] = alloca double, align 8
+// CHECK2-NEXT: [[__RANGE2:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__END2:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[__BEGIN2:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV___BEGIN2:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[V:%.*]] = alloca ptr, align 8
+// CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8
+// CHECK2-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0
+// CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128
+// CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8
+// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
+// CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0
+// CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8
+// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_3]], align 8
+// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// CHECK2-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
+// CHECK2-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
+// CHECK2-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 8
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1
+// CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[DIV]], 1
+// CHECK2-NEXT: store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], 21
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END15:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2
+// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK2-NEXT: store i64 0, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK2-NEXT: br label [[FOR_COND7:%.*]]
+// CHECK2: for.cond7:
+// CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_4]], align 8
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP9]], 1
+// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i64 [[TMP8]], [[ADD8]]
+// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body10:
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK2-NEXT: [[MUL11:%.*]] = mul nsw i64 [[TMP11]], 1
+// CHECK2-NEXT: [[ADD_PTR12:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i64 [[MUL11]]
+// CHECK2-NEXT: store ptr [[ADD_PTR12]], ptr [[__BEGIN2]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8
+// CHECK2-NEXT: store ptr [[TMP12]], ptr [[V]], align 8
+// CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8
+// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
+// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
+// CHECK2: for.inc13:
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
+// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2: for.end15:
+// CHECK2-NEXT: ret void
+//
diff --git a/clang/test/OpenMP/interchange_messages.cpp b/clang/test/OpenMP/interchange_messages.cpp
new file mode 100644
index 0000000000000..175c2f1efa744
--- /dev/null
+++ b/clang/test/OpenMP/interchange_messages.cpp
@@ -0,0 +1,77 @@
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -std=c++17 -fopenmp -fopenmp-version=60 -fsyntax-only -Wuninitialized -verify %s
+
+void func() {
+
+ // expected-warning at +1 {{extra tokens at the end of '#pragma omp interchange' are ignored}}
+ #pragma omp interchange foo
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{unexpected OpenMP clause 'collapse' in directive '#pragma omp interchange'}}
+ #pragma omp interchange collapse(2)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ {
+ // expected-error at +2 {{expected statement}}
+ #pragma omp interchange
+ }
+
+ // expected-error at +2 {{statement after '#pragma omp interchange' must be a for loop}}
+ #pragma omp interchange
+ int b = 0;
+
+ // expected-error at +3 {{statement after '#pragma omp interchange' must be a for loop}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ ;
+
+ // expected-error at +2 {{statement after '#pragma omp interchange' must be a for loop}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i) {
+ int k = 3;
+ for (int j = 0; j < 7; ++j)
+ ;
+ }
+
+ // expected-error at +3 {{expected loop invariant expression}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ for (int j = i; j < 7; ++j)
+ ;
+
+ // expected-error at +3 {{expected loop invariant expression}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < i; ++j)
+ ;
+
+ // expected-error at +3 {{expected loop invariant expression}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < i; ++j)
+ ;
+
+ // expected-error at +6 {{expected 3 for loops after '#pragma omp for', but found only 2}}
+ // expected-note at +1 {{as specified in 'collapse' clause}}
+ #pragma omp for collapse(3)
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +2 {{statement after '#pragma omp interchange' must be a for loop}}
+ #pragma omp interchange
+ #pragma omp for
+ for (int i = 0; i < 7; ++i)
+ ;
+
+ // expected-error at +3 {{condition of OpenMP for loop must be a relational comparison ('<', '<=', '>', '>=', or '!=') of loop variable 'j'}}
+ #pragma omp interchange
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j/3<7; ++j)
+ ;
+}
+
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 51784ed02b111..a6a002533936f 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -2180,6 +2180,7 @@ class EnqueueVisitor : public ConstStmtVisitor<EnqueueVisitor, void>,
void VisitOMPTileDirective(const OMPTileDirective *D);
void VisitOMPUnrollDirective(const OMPUnrollDirective *D);
void VisitOMPReverseDirective(const OMPReverseDirective *D);
+ void VisitOMPInterchangeDirective(const OMPInterchangeDirective *D);
void VisitOMPForDirective(const OMPForDirective *D);
void VisitOMPForSimdDirective(const OMPForSimdDirective *D);
void VisitOMPSectionsDirective(const OMPSectionsDirective *D);
@@ -3226,6 +3227,11 @@ void EnqueueVisitor::VisitOMPReverseDirective(const OMPReverseDirective *D) {
VisitOMPLoopTransformationDirective(D);
}
+void EnqueueVisitor::VisitOMPInterchangeDirective(
+ const OMPInterchangeDirective *D) {
+ VisitOMPLoopTransformationDirective(D);
+}
+
void EnqueueVisitor::VisitOMPForDirective(const OMPForDirective *D) {
VisitOMPLoopDirective(D);
}
@@ -6086,6 +6092,8 @@ CXString clang_getCursorKindSpelling(enum CXCursorKind Kind) {
return cxstring::createRef("OMPUnrollDirective");
case CXCursor_OMPReverseDirective:
return cxstring::createRef("OMPReverseDirective");
+ case CXCursor_OMPInterchangeDirective:
+ return cxstring::createRef("OMPInterchangeDirective");
case CXCursor_OMPForDirective:
return cxstring::createRef("OMPForDirective");
case CXCursor_OMPForSimdDirective:
diff --git a/clang/tools/libclang/CXCursor.cpp b/clang/tools/libclang/CXCursor.cpp
index 275714d8fbcdd..9d485ce85b829 100644
--- a/clang/tools/libclang/CXCursor.cpp
+++ b/clang/tools/libclang/CXCursor.cpp
@@ -675,6 +675,9 @@ CXCursor cxcursor::MakeCXCursor(const Stmt *S, const Decl *Parent,
case Stmt::OMPReverseDirectiveClass:
K = CXCursor_OMPReverseDirective;
break;
+ case Stmt::OMPInterchangeDirectiveClass:
+ K = CXCursor_OMPTileDirective;
+ break;
case Stmt::OMPForDirectiveClass:
K = CXCursor_OMPForDirective;
break;
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td
index 0ad3d919103fe..3395f82ce1ba2 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMP.td
+++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td
@@ -540,6 +540,9 @@ def OMP_Unroll : Directive<"unroll"> {
def OMP_Reverse : Directive<"reverse"> {
let association = AS_Loop;
}
+def OMP_Interchange : Directive<"interchange"> {
+ let association = AS_Loop;
+}
def OMP_For : Directive<"for"> {
let allowedClauses = [
VersionedClause<OMPC_Private>,
diff --git a/openmp/runtime/test/transform/interchange/foreach.cpp b/openmp/runtime/test/transform/interchange/foreach.cpp
new file mode 100644
index 0000000000000..17eaed6029d01
--- /dev/null
+++ b/openmp/runtime/test/transform/interchange/foreach.cpp
@@ -0,0 +1,216 @@
+// RUN: %libomp-cxx20-compile-and-run | FileCheck %s --match-full-lines
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdarg>
+#include <cstdio>
+#include <vector>
+
+struct Reporter {
+ const char *name;
+
+ Reporter(const char *name) : name(name) { print("ctor"); }
+
+ Reporter() : name("<anon>") { print("ctor"); }
+
+ Reporter(const Reporter &that) : name(that.name) { print("copy ctor"); }
+
+ Reporter(Reporter &&that) : name(that.name) { print("move ctor"); }
+
+ ~Reporter() { print("dtor"); }
+
+ const Reporter &operator=(const Reporter &that) {
+ print("copy assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ const Reporter &operator=(Reporter &&that) {
+ print("move assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ struct Iterator {
+ const Reporter *owner;
+ int pos;
+
+ Iterator(const Reporter *owner, int pos) : owner(owner), pos(pos) {}
+
+ Iterator(const Iterator &that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator copy ctor");
+ }
+
+ Iterator(Iterator &&that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator move ctor");
+ }
+
+ ~Iterator() { owner->print("iterator dtor"); }
+
+ const Iterator &operator=(const Iterator &that) {
+ owner->print("iterator copy assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ const Iterator &operator=(Iterator &&that) {
+ owner->print("iterator move assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ bool operator==(const Iterator &that) const {
+ owner->print("iterator %d == %d", 2 - this->pos, 2 - that.pos);
+ return this->pos == that.pos;
+ }
+
+ Iterator &operator++() {
+ owner->print("iterator prefix ++");
+ pos -= 1;
+ return *this;
+ }
+
+ Iterator operator++(int) {
+ owner->print("iterator postfix ++");
+ auto result = *this;
+ pos -= 1;
+ return result;
+ }
+
+ int operator*() const {
+ int result = 2 - pos;
+ owner->print("iterator deref: %i", result);
+ return result;
+ }
+
+ size_t operator-(const Iterator &that) const {
+ int result = (2 - this->pos) - (2 - that.pos);
+ owner->print("iterator distance: %d", result);
+ return result;
+ }
+
+ Iterator operator+(int steps) const {
+ owner->print("iterator advance: %i += %i", 2 - this->pos, steps);
+ return Iterator(owner, pos - steps);
+ }
+
+ void print(const char *msg) const { owner->print(msg); }
+ };
+
+ Iterator begin() const {
+ print("begin()");
+ return Iterator(this, 2);
+ }
+
+ Iterator end() const {
+ print("end()");
+ return Iterator(this, -1);
+ }
+
+ void print(const char *msg, ...) const {
+ va_list args;
+ va_start(args, msg);
+ printf("[%s] ", name);
+ vprintf(msg, args);
+ printf("\n");
+ va_end(args);
+ }
+};
+
+int main() {
+ printf("do\n");
+#pragma omp interchange
+ for (Reporter c{"C"}; auto &&v : Reporter("A"))
+ for (Reporter d{"D"}; auto &&w : Reporter("B"))
+ printf("v=%d w=%d\n", v, w);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: [C] ctor
+// CHECK-NEXT: [A] ctor
+// CHECK-NEXT: [A] end()
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] iterator distance: 3
+// CHECK-NEXT: [D] ctor
+// CHECK-NEXT: [B] ctor
+// CHECK-NEXT: [B] end()
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] iterator distance: 3
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: v=0 w=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: v=1 w=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: v=2 w=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: v=0 w=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: v=1 w=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: v=2 w=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: v=0 w=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: v=1 w=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: v=2 w=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] dtor
+// CHECK-NEXT: [D] dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] dtor
+// CHECK-NEXT: [C] dtor
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/interchange/intfor.c b/openmp/runtime/test/transform/interchange/intfor.c
new file mode 100644
index 0000000000000..b4842f0f82913
--- /dev/null
+++ b/openmp/runtime/test/transform/interchange/intfor.c
@@ -0,0 +1,38 @@
+// RUN: %libomp-compile-and-run | FileCheck %s --match-full-lines
+
+#ifndef HEADER
+#define HEADER
+
+#include <stdlib.h>
+#include <stdio.h>
+
+int main() {
+ printf("do\n");
+#pragma omp interchange
+ for (int i = 7; i < 17; i += 3)
+ for (int j = 8; j < 18; j += 3)
+ printf("i=%d j=%d\n", i, j);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: i=7 j=8
+// CHECK-NEXT: i=10 j=8
+// CHECK-NEXT: i=13 j=8
+// CHECK-NEXT: i=16 j=8
+// CHECK-NEXT: i=7 j=11
+// CHECK-NEXT: i=10 j=11
+// CHECK-NEXT: i=13 j=11
+// CHECK-NEXT: i=16 j=11
+// CHECK-NEXT: i=7 j=14
+// CHECK-NEXT: i=10 j=14
+// CHECK-NEXT: i=13 j=14
+// CHECK-NEXT: i=16 j=14
+// CHECK-NEXT: i=7 j=17
+// CHECK-NEXT: i=10 j=17
+// CHECK-NEXT: i=13 j=17
+// CHECK-NEXT: i=16 j=17
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/interchange/iterfor.cpp b/openmp/runtime/test/transform/interchange/iterfor.cpp
new file mode 100644
index 0000000000000..51219a07402e3
--- /dev/null
+++ b/openmp/runtime/test/transform/interchange/iterfor.cpp
@@ -0,0 +1,222 @@
+// RUN: %libomp-cxx20-compile-and-run | FileCheck %s --match-full-lines
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdarg>
+#include <cstdio>
+#include <vector>
+
+struct Reporter {
+ const char *name;
+
+ Reporter(const char *name) : name(name) { print("ctor"); }
+
+ Reporter() : name("<anon>") { print("ctor"); }
+
+ Reporter(const Reporter &that) : name(that.name) { print("copy ctor"); }
+
+ Reporter(Reporter &&that) : name(that.name) { print("move ctor"); }
+
+ ~Reporter() { print("dtor"); }
+
+ const Reporter &operator=(const Reporter &that) {
+ print("copy assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ const Reporter &operator=(Reporter &&that) {
+ print("move assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ struct Iterator {
+ const Reporter *owner;
+ int pos;
+
+ Iterator(const Reporter *owner, int pos) : owner(owner), pos(pos) {}
+
+ Iterator(const Iterator &that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator copy ctor");
+ }
+
+ Iterator(Iterator &&that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator move ctor");
+ }
+
+ ~Iterator() { owner->print("iterator dtor"); }
+
+ const Iterator &operator=(const Iterator &that) {
+ owner->print("iterator copy assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ const Iterator &operator=(Iterator &&that) {
+ owner->print("iterator move assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ bool operator==(const Iterator &that) const {
+ owner->print("iterator %d == %d", 2 - this->pos, 2 - that.pos);
+ return this->pos == that.pos;
+ }
+
+ bool operator!=(const Iterator &that) const {
+ owner->print("iterator %d != %d", 2 - this->pos, 2 - that.pos);
+ return this->pos == that.pos;
+ }
+
+ Iterator &operator++() {
+ owner->print("iterator prefix ++");
+ pos -= 1;
+ return *this;
+ }
+
+ Iterator operator++(int) {
+ owner->print("iterator postfix ++");
+ auto result = *this;
+ pos -= 1;
+ return result;
+ }
+
+ int operator*() const {
+ int result = 2 - pos;
+ owner->print("iterator deref: %i", result);
+ return result;
+ }
+
+ size_t operator-(const Iterator &that) const {
+ int result = (2 - this->pos) - (2 - that.pos);
+ owner->print("iterator distance: %d", result);
+ return result;
+ }
+
+ Iterator operator+(int steps) const {
+ owner->print("iterator advance: %i += %i", 2 - this->pos, steps);
+ return Iterator(owner, pos - steps);
+ }
+ };
+
+ Iterator begin() const {
+ print("begin()");
+ return Iterator(this, 2);
+ }
+
+ Iterator end() const {
+ print("end()");
+ return Iterator(this, -1);
+ }
+
+ void print(const char *msg, ...) const {
+ va_list args;
+ va_start(args, msg);
+ printf("[%s] ", name);
+ vprintf(msg, args);
+ printf("\n");
+ va_end(args);
+ }
+};
+
+int main() {
+ printf("do\n");
+ Reporter A("A"), B("B");
+#pragma omp interchange
+ for (auto it = A.begin(); it != A.end(); ++it)
+ for (auto jt = B.begin(); jt != B.end(); ++jt)
+ printf("i=%d j=%d\n", *it, *jt);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: [A] ctor
+// CHECK-NEXT: [B] ctor
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] end()
+// CHECK-NEXT: [A] iterator distance: 3
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] end()
+// CHECK-NEXT: [B] iterator distance: 3
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: i=0 j=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: i=1 j=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: i=2 j=0
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: i=0 j=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: i=1 j=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: i=2 j=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: i=0 j=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: i=1 j=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: i=2 j=2
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: done
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] dtor
+// CHECK-NEXT: [A] dtor
diff --git a/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-foreach.cpp b/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-foreach.cpp
new file mode 100644
index 0000000000000..54399d25a3f15
--- /dev/null
+++ b/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-foreach.cpp
@@ -0,0 +1,340 @@
+// RUN: %libomp-cxx20-compile-and-run | FileCheck %s --match-full-lines
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdarg>
+#include <cstdio>
+#include <vector>
+
+struct Reporter {
+ const char *name;
+
+ Reporter(const char *name) : name(name) { print("ctor"); }
+
+ Reporter() : name("<anon>") { print("ctor"); }
+
+ Reporter(const Reporter &that) : name(that.name) { print("copy ctor"); }
+
+ Reporter(Reporter &&that) : name(that.name) { print("move ctor"); }
+
+ ~Reporter() { print("dtor"); }
+
+ const Reporter &operator=(const Reporter &that) {
+ print("copy assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ const Reporter &operator=(Reporter &&that) {
+ print("move assign");
+ this->name = that.name;
+ return *this;
+ }
+
+ struct Iterator {
+ const Reporter *owner;
+ int pos;
+
+ Iterator(const Reporter *owner, int pos) : owner(owner), pos(pos) {}
+
+ Iterator(const Iterator &that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator copy ctor");
+ }
+
+ Iterator(Iterator &&that) : owner(that.owner), pos(that.pos) {
+ owner->print("iterator move ctor");
+ }
+
+ ~Iterator() { owner->print("iterator dtor"); }
+
+ const Iterator &operator=(const Iterator &that) {
+ owner->print("iterator copy assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ const Iterator &operator=(Iterator &&that) {
+ owner->print("iterator move assign");
+ this->owner = that.owner;
+ this->pos = that.pos;
+ return *this;
+ }
+
+ bool operator==(const Iterator &that) const {
+ owner->print("iterator %d == %d", 2 - this->pos, 2 - that.pos);
+ return this->pos == that.pos;
+ }
+
+ Iterator &operator++() {
+ owner->print("iterator prefix ++");
+ pos -= 1;
+ return *this;
+ }
+
+ Iterator operator++(int) {
+ owner->print("iterator postfix ++");
+ auto result = *this;
+ pos -= 1;
+ return result;
+ }
+
+ int operator*() const {
+ int result = 2 - pos;
+ owner->print("iterator deref: %i", result);
+ return result;
+ }
+
+ size_t operator-(const Iterator &that) const {
+ int result = (2 - this->pos) - (2 - that.pos);
+ owner->print("iterator distance: %d", result);
+ return result;
+ }
+
+ Iterator operator+(int steps) const {
+ owner->print("iterator advance: %i += %i", 2 - this->pos, steps);
+ return Iterator(owner, pos - steps);
+ }
+ };
+
+ Iterator begin() const {
+ print("begin()");
+ return Iterator(this, 2);
+ }
+
+ Iterator end() const {
+ print("end()");
+ return Iterator(this, -1);
+ }
+
+ void print(const char *msg, ...) const {
+ va_list args;
+ va_start(args, msg);
+ printf("[%s] ", name);
+ vprintf(msg, args);
+ printf("\n");
+ va_end(args);
+ }
+};
+
+int main() {
+ printf("do\n");
+#pragma omp parallel for collapse(3) num_threads(1)
+ for (int i = 0; i < 2; ++i)
+#pragma omp interchange
+ for (Reporter c{"C"}; auto &&v : Reporter("A"))
+ for (Reporter d{"D"}; auto &&w : Reporter("B"))
+ for (int k = 0; k < 2; ++k)
+ printf("i=%d v=%d w=%d k=%d\n", i, v, w, k);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: [C] ctor
+// CHECK-NEXT: [A] ctor
+// CHECK-NEXT: [A] end()
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] begin()
+// CHECK-NEXT: [A] iterator distance: 3
+// CHECK-NEXT: [D] ctor
+// CHECK-NEXT: [B] ctor
+// CHECK-NEXT: [B] end()
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] begin()
+// CHECK-NEXT: [B] iterator distance: 3
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=0 v=0 w=0 k=0
+// CHECK-NEXT: i=0 v=0 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=0 v=1 w=0 k=0
+// CHECK-NEXT: i=0 v=1 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=0 v=2 w=0 k=0
+// CHECK-NEXT: i=0 v=2 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=0 v=0 w=1 k=0
+// CHECK-NEXT: i=0 v=0 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=0 v=1 w=1 k=0
+// CHECK-NEXT: i=0 v=1 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=0 v=2 w=1 k=0
+// CHECK-NEXT: i=0 v=2 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=0 v=0 w=2 k=0
+// CHECK-NEXT: i=0 v=0 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=0 v=1 w=2 k=0
+// CHECK-NEXT: i=0 v=1 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=0 v=2 w=2 k=0
+// CHECK-NEXT: i=0 v=2 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=1 v=0 w=0 k=0
+// CHECK-NEXT: i=1 v=0 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=1 v=1 w=0 k=0
+// CHECK-NEXT: i=1 v=1 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 0
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 0
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=1 v=2 w=0 k=0
+// CHECK-NEXT: i=1 v=2 w=0 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=1 v=0 w=1 k=0
+// CHECK-NEXT: i=1 v=0 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=1 v=1 w=1 k=0
+// CHECK-NEXT: i=1 v=1 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 1
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 1
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=1 v=2 w=1 k=0
+// CHECK-NEXT: i=1 v=2 w=1 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 0
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 0
+// CHECK-NEXT: i=1 v=0 w=2 k=0
+// CHECK-NEXT: i=1 v=0 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 1
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 1
+// CHECK-NEXT: i=1 v=1 w=2 k=0
+// CHECK-NEXT: i=1 v=1 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator advance: 0 += 2
+// CHECK-NEXT: [B] iterator move assign
+// CHECK-NEXT: [B] iterator deref: 2
+// CHECK-NEXT: [A] iterator advance: 0 += 2
+// CHECK-NEXT: [A] iterator move assign
+// CHECK-NEXT: [A] iterator deref: 2
+// CHECK-NEXT: i=1 v=2 w=2 k=0
+// CHECK-NEXT: i=1 v=2 w=2 k=1
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] iterator dtor
+// CHECK-NEXT: [B] dtor
+// CHECK-NEXT: [D] dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] iterator dtor
+// CHECK-NEXT: [A] dtor
+// CHECK-NEXT: [C] dtor
+// CHECK-NEXT: done
diff --git a/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-intfor.cpp b/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-intfor.cpp
new file mode 100644
index 0000000000000..a4520afdb0f9c
--- /dev/null
+++ b/openmp/runtime/test/transform/interchange/parallel-wsloop-collapse-intfor.cpp
@@ -0,0 +1,106 @@
+// RUN: %libomp-cxx-compile-and-run | FileCheck %s --match-full-lines
+
+#ifndef HEADER
+#define HEADER
+
+#include <cstdlib>
+#include <cstdio>
+
+int main() {
+ printf("do\n");
+#pragma omp parallel for collapse(4) num_threads(1)
+ for (int i = 0; i < 3; ++i)
+#pragma omp interchange
+ for (int j = 0; j < 3; ++j)
+ for (int k = 0; k < 3; ++k)
+ for (int l = 0; l < 3; ++l)
+ printf("i=%d j=%d k=%d l=%d\n", i, j, k, l);
+ printf("done\n");
+ return EXIT_SUCCESS;
+}
+
+#endif /* HEADER */
+
+// CHECK: do
+// CHECK-NEXT: i=0 j=0 k=0 l=0
+// CHECK-NEXT: i=0 j=0 k=0 l=1
+// CHECK-NEXT: i=0 j=0 k=0 l=2
+// CHECK-NEXT: i=0 j=1 k=0 l=0
+// CHECK-NEXT: i=0 j=1 k=0 l=1
+// CHECK-NEXT: i=0 j=1 k=0 l=2
+// CHECK-NEXT: i=0 j=2 k=0 l=0
+// CHECK-NEXT: i=0 j=2 k=0 l=1
+// CHECK-NEXT: i=0 j=2 k=0 l=2
+// CHECK-NEXT: i=0 j=0 k=1 l=0
+// CHECK-NEXT: i=0 j=0 k=1 l=1
+// CHECK-NEXT: i=0 j=0 k=1 l=2
+// CHECK-NEXT: i=0 j=1 k=1 l=0
+// CHECK-NEXT: i=0 j=1 k=1 l=1
+// CHECK-NEXT: i=0 j=1 k=1 l=2
+// CHECK-NEXT: i=0 j=2 k=1 l=0
+// CHECK-NEXT: i=0 j=2 k=1 l=1
+// CHECK-NEXT: i=0 j=2 k=1 l=2
+// CHECK-NEXT: i=0 j=0 k=2 l=0
+// CHECK-NEXT: i=0 j=0 k=2 l=1
+// CHECK-NEXT: i=0 j=0 k=2 l=2
+// CHECK-NEXT: i=0 j=1 k=2 l=0
+// CHECK-NEXT: i=0 j=1 k=2 l=1
+// CHECK-NEXT: i=0 j=1 k=2 l=2
+// CHECK-NEXT: i=0 j=2 k=2 l=0
+// CHECK-NEXT: i=0 j=2 k=2 l=1
+// CHECK-NEXT: i=0 j=2 k=2 l=2
+// CHECK-NEXT: i=1 j=0 k=0 l=0
+// CHECK-NEXT: i=1 j=0 k=0 l=1
+// CHECK-NEXT: i=1 j=0 k=0 l=2
+// CHECK-NEXT: i=1 j=1 k=0 l=0
+// CHECK-NEXT: i=1 j=1 k=0 l=1
+// CHECK-NEXT: i=1 j=1 k=0 l=2
+// CHECK-NEXT: i=1 j=2 k=0 l=0
+// CHECK-NEXT: i=1 j=2 k=0 l=1
+// CHECK-NEXT: i=1 j=2 k=0 l=2
+// CHECK-NEXT: i=1 j=0 k=1 l=0
+// CHECK-NEXT: i=1 j=0 k=1 l=1
+// CHECK-NEXT: i=1 j=0 k=1 l=2
+// CHECK-NEXT: i=1 j=1 k=1 l=0
+// CHECK-NEXT: i=1 j=1 k=1 l=1
+// CHECK-NEXT: i=1 j=1 k=1 l=2
+// CHECK-NEXT: i=1 j=2 k=1 l=0
+// CHECK-NEXT: i=1 j=2 k=1 l=1
+// CHECK-NEXT: i=1 j=2 k=1 l=2
+// CHECK-NEXT: i=1 j=0 k=2 l=0
+// CHECK-NEXT: i=1 j=0 k=2 l=1
+// CHECK-NEXT: i=1 j=0 k=2 l=2
+// CHECK-NEXT: i=1 j=1 k=2 l=0
+// CHECK-NEXT: i=1 j=1 k=2 l=1
+// CHECK-NEXT: i=1 j=1 k=2 l=2
+// CHECK-NEXT: i=1 j=2 k=2 l=0
+// CHECK-NEXT: i=1 j=2 k=2 l=1
+// CHECK-NEXT: i=1 j=2 k=2 l=2
+// CHECK-NEXT: i=2 j=0 k=0 l=0
+// CHECK-NEXT: i=2 j=0 k=0 l=1
+// CHECK-NEXT: i=2 j=0 k=0 l=2
+// CHECK-NEXT: i=2 j=1 k=0 l=0
+// CHECK-NEXT: i=2 j=1 k=0 l=1
+// CHECK-NEXT: i=2 j=1 k=0 l=2
+// CHECK-NEXT: i=2 j=2 k=0 l=0
+// CHECK-NEXT: i=2 j=2 k=0 l=1
+// CHECK-NEXT: i=2 j=2 k=0 l=2
+// CHECK-NEXT: i=2 j=0 k=1 l=0
+// CHECK-NEXT: i=2 j=0 k=1 l=1
+// CHECK-NEXT: i=2 j=0 k=1 l=2
+// CHECK-NEXT: i=2 j=1 k=1 l=0
+// CHECK-NEXT: i=2 j=1 k=1 l=1
+// CHECK-NEXT: i=2 j=1 k=1 l=2
+// CHECK-NEXT: i=2 j=2 k=1 l=0
+// CHECK-NEXT: i=2 j=2 k=1 l=1
+// CHECK-NEXT: i=2 j=2 k=1 l=2
+// CHECK-NEXT: i=2 j=0 k=2 l=0
+// CHECK-NEXT: i=2 j=0 k=2 l=1
+// CHECK-NEXT: i=2 j=0 k=2 l=2
+// CHECK-NEXT: i=2 j=1 k=2 l=0
+// CHECK-NEXT: i=2 j=1 k=2 l=1
+// CHECK-NEXT: i=2 j=1 k=2 l=2
+// CHECK-NEXT: i=2 j=2 k=2 l=0
+// CHECK-NEXT: i=2 j=2 k=2 l=1
+// CHECK-NEXT: i=2 j=2 k=2 l=2
+// CHECK-NEXT: done
>From fa159565e336c142cbc55a0f26793414df55dcfc Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Wed, 22 May 2024 13:45:25 +0200
Subject: [PATCH 2/2] [Clang][OpenMP] Add permutation clause
---
clang/include/clang/AST/OpenMPClause.h | 100 +
clang/include/clang/AST/RecursiveASTVisitor.h | 8 +
.../clang/Basic/DiagnosticSemaKinds.td | 4 +
clang/include/clang/Parse/Parser.h | 3 +
clang/include/clang/Sema/SemaOpenMP.h | 5 +
clang/lib/AST/OpenMPClause.cpp | 31 +
clang/lib/AST/StmtProfile.cpp | 7 +
clang/lib/Basic/OpenMPKinds.cpp | 2 +
clang/lib/Parse/ParseOpenMP.cpp | 20 +
clang/lib/Sema/SemaOpenMP.cpp | 146 +-
clang/lib/Sema/TreeTransform.h | 35 +
clang/lib/Serialization/ASTReader.cpp | 11 +
clang/lib/Serialization/ASTWriter.cpp | 7 +
clang/test/OpenMP/interchange_ast_print.cpp | 98 +
clang/test/OpenMP/interchange_codegen.cpp | 3359 ++++++++++++++++-
clang/test/OpenMP/interchange_messages.cpp | 154 +
clang/tools/libclang/CIndex.cpp | 6 +
flang/lib/Lower/OpenMP/Clauses.cpp | 6 +
flang/lib/Lower/OpenMP/Clauses.h | 1 +
flang/lib/Parser/openmp-parsers.cpp | 2 +
flang/lib/Semantics/check-omp-structure.cpp | 1 +
llvm/include/llvm/Frontend/OpenMP/ClauseT.h | 14 +-
llvm/include/llvm/Frontend/OpenMP/OMP.td | 8 +
23 files changed, 3979 insertions(+), 49 deletions(-)
diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h
index 325a1baa44614..239dac08c2a68 100644
--- a/clang/include/clang/AST/OpenMPClause.h
+++ b/clang/include/clang/AST/OpenMPClause.h
@@ -870,6 +870,106 @@ class OMPSizesClause final
}
};
+/// This class represents the 'permutation' clause in the
+/// '#pragma omp interchange' directive.
+///
+/// \code{c}
+/// #pragma omp interchange permutation(2,1)
+/// for (int i = 0; i < 64; ++i)
+/// for (int j = 0; j < 64; ++j)
+/// \endcode
+class OMPPermutationClause final
+ : public OMPClause,
+ private llvm::TrailingObjects<OMPSizesClause, Expr *> {
+ friend class OMPClauseReader;
+ friend class llvm::TrailingObjects<OMPSizesClause, Expr *>;
+
+ /// Location of '('.
+ SourceLocation LParenLoc;
+
+ /// Number of arguments in the clause, and hence also the number of loops to
+ /// be permuted.
+ unsigned NumLoops;
+
+ /// Sets the permutation index expressions.
+ void setArgRefs(ArrayRef<Expr *> VL) {
+ assert(VL.size() == NumLoops);
+ std::copy(VL.begin(), VL.end(),
+ static_cast<OMPPermutationClause *>(this)
+ ->template getTrailingObjects<Expr *>());
+ }
+
+ /// Build an empty clause.
+ explicit OMPPermutationClause(int NumLoops)
+ : OMPClause(llvm::omp::OMPC_permutation, SourceLocation(),
+ SourceLocation()),
+ NumLoops(NumLoops) {}
+
+public:
+ /// Build a 'permutation' clause AST node.
+ ///
+ /// \param C Context of the AST.
+ /// \param StartLoc Location of the 'permutation' identifier.
+ /// \param LParenLoc Location of '('.
+ /// \param EndLoc Location of ')'.
+ /// \param Args Content of the clause.
+ static OMPPermutationClause *
+ Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc,
+ SourceLocation EndLoc, ArrayRef<Expr *> Args);
+
+ /// Build an empty 'permutation' AST node for deserialization.
+ ///
+ /// \param C Context of the AST.
+ /// \param NumLoops Number of arguments in the clause.
+ static OMPPermutationClause *CreateEmpty(const ASTContext &C,
+ unsigned NumLoops);
+
+ /// Sets the location of '('.
+ void setLParenLoc(SourceLocation Loc) { LParenLoc = Loc; }
+
+ /// Returns the location of '('.
+ SourceLocation getLParenLoc() const { return LParenLoc; }
+
+ /// Returns the number of list items.
+ unsigned getNumLoops() const { return NumLoops; }
+
+ /// Returns the permutation index expressions.
+ ///@{
+ MutableArrayRef<Expr *> getArgsRefs() {
+ return MutableArrayRef<Expr *>(static_cast<OMPPermutationClause *>(this)
+ ->template getTrailingObjects<Expr *>(),
+ NumLoops);
+ }
+ ArrayRef<Expr *> getArgsRefs() const {
+ return ArrayRef<Expr *>(static_cast<const OMPPermutationClause *>(this)
+ ->template getTrailingObjects<Expr *>(),
+ NumLoops);
+ }
+ ///@}
+
+ child_range children() {
+ MutableArrayRef<Expr *> Args = getArgsRefs();
+ return child_range(reinterpret_cast<Stmt **>(Args.begin()),
+ reinterpret_cast<Stmt **>(Args.end()));
+ }
+ const_child_range children() const {
+ ArrayRef<Expr *> Args = getArgsRefs();
+ return const_child_range(reinterpret_cast<Stmt *const *>(Args.begin()),
+ reinterpret_cast<Stmt *const *>(Args.end()));
+ }
+
+ child_range used_children() {
+ return child_range(child_iterator(), child_iterator());
+ }
+ const_child_range used_children() const {
+ return const_child_range(const_child_iterator(), const_child_iterator());
+ }
+
+ static bool classof(const OMPClause *T) {
+ return T->getClauseKind() == llvm::omp::OMPC_permutation;
+ }
+};
+
/// Representation of the 'full' clause of the '#pragma omp unroll' directive.
///
/// \code
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index 1bb167d7ddc3c..68dc8b7965955 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -3325,6 +3325,14 @@ bool RecursiveASTVisitor<Derived>::VisitOMPSizesClause(OMPSizesClause *C) {
return true;
}
+template <typename Derived>
+bool RecursiveASTVisitor<Derived>::VisitOMPPermutationClause(
+ OMPPermutationClause *C) {
+ for (Expr *E : C->getArgsRefs())
+ TRY_TO(TraverseStmt(E));
+ return true;
+}
+
template <typename Derived>
bool RecursiveASTVisitor<Derived>::VisitOMPFullClause(OMPFullClause *C) {
return true;
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index c7dea1d54d063..a04784a9015c0 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11521,6 +11521,10 @@ def err_omp_dispatch_statement_call
" to a target function or an assignment to one">;
def err_omp_unroll_full_variable_trip_count : Error<
"loop to be fully unrolled must have a constant trip count">;
+def err_omp_interchange_permutation_value_range : Error<
+ "permutation index must be at least 1 and at most %0">;
+def err_omp_interchange_permutation_value_repeated : Error<
+ "index %0 must appear exactly once in the permutation clause">;
def note_omp_directive_here : Note<"'%0' directive found here">;
def err_omp_instantiation_not_supported
: Error<"instantiation of '%0' not supported yet">;
diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h
index 3c4ab649e3b4c..4837eef3ab113 100644
--- a/clang/include/clang/Parse/Parser.h
+++ b/clang/include/clang/Parse/Parser.h
@@ -3542,6 +3542,9 @@ class Parser : public CodeCompletionHandler {
/// Parses the 'sizes' clause of a '#pragma omp tile' directive.
OMPClause *ParseOpenMPSizesClause();
+ /// Parses the 'permutation' clause of a '#pragma omp interchange' directive.
+ OMPClause *ParseOpenMPPermutationClause();
+
/// Parses clause without any additional arguments.
///
/// \param Kind Kind of current clause.
diff --git a/clang/include/clang/Sema/SemaOpenMP.h b/clang/include/clang/Sema/SemaOpenMP.h
index 06376f173e8df..89e7ad84d63d9 100644
--- a/clang/include/clang/Sema/SemaOpenMP.h
+++ b/clang/include/clang/Sema/SemaOpenMP.h
@@ -868,6 +868,11 @@ class SemaOpenMP : public SemaBase {
SourceLocation StartLoc,
SourceLocation LParenLoc,
SourceLocation EndLoc);
+ /// Called on well-form 'permutation' clause after parsing its arguments.
+ OMPClause *ActOnOpenMPPermutationClause(ArrayRef<Expr *> PermExprs,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc);
/// Called on well-form 'full' clauses.
OMPClause *ActOnOpenMPFullClause(SourceLocation StartLoc,
SourceLocation EndLoc);
diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp
index 042a5df5906ca..c94310769ed9e 100644
--- a/clang/lib/AST/OpenMPClause.cpp
+++ b/clang/lib/AST/OpenMPClause.cpp
@@ -971,6 +971,25 @@ OMPSizesClause *OMPSizesClause::CreateEmpty(const ASTContext &C,
return new (Mem) OMPSizesClause(NumSizes);
}
+OMPPermutationClause *OMPPermutationClause::Create(const ASTContext &C,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc,
+ ArrayRef<Expr *> Args) {
+ OMPPermutationClause *Clause = CreateEmpty(C, Args.size());
+ Clause->setLocStart(StartLoc);
+ Clause->setLParenLoc(LParenLoc);
+ Clause->setLocEnd(EndLoc);
+ Clause->setArgRefs(Args);
+ return Clause;
+}
+
+OMPPermutationClause *OMPPermutationClause::CreateEmpty(const ASTContext &C,
+ unsigned NumLoops) {
+ void *Mem = C.Allocate(totalSizeToAlloc<Expr *>(NumLoops));
+ return new (Mem) OMPPermutationClause(NumLoops);
+}
+
OMPFullClause *OMPFullClause::Create(const ASTContext &C,
SourceLocation StartLoc,
SourceLocation EndLoc) {
@@ -1774,6 +1793,18 @@ void OMPClausePrinter::VisitOMPSizesClause(OMPSizesClause *Node) {
OS << ")";
}
+void OMPClausePrinter::VisitOMPPermutationClause(OMPPermutationClause *Node) {
+ OS << "permutation(";
+ bool First = true;
+ for (Expr *Size : Node->getArgsRefs()) {
+ if (!First)
+ OS << ", ";
+ Size->printPretty(OS, nullptr, Policy, 0);
+ First = false;
+ }
+ OS << ")";
+}
+
void OMPClausePrinter::VisitOMPFullClause(OMPFullClause *Node) { OS << "full"; }
void OMPClausePrinter::VisitOMPPartialClause(OMPPartialClause *Node) {
diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 1ae99d43575a7..bacc03bbe9337 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -493,6 +493,13 @@ void OMPClauseProfiler::VisitOMPSizesClause(const OMPSizesClause *C) {
Profiler->VisitExpr(E);
}
+void OMPClauseProfiler::VisitOMPPermutationClause(
+ const OMPPermutationClause *C) {
+ for (Expr *E : C->getArgsRefs())
+ if (E)
+ Profiler->VisitExpr(E);
+}
+
void OMPClauseProfiler::VisitOMPFullClause(const OMPFullClause *C) {}
void OMPClauseProfiler::VisitOMPPartialClause(const OMPPartialClause *C) {
diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp
index ff5d5c8bdc981..b95045cc0409f 100644
--- a/clang/lib/Basic/OpenMPKinds.cpp
+++ b/clang/lib/Basic/OpenMPKinds.cpp
@@ -188,6 +188,7 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind, StringRef Str,
case OMPC_safelen:
case OMPC_simdlen:
case OMPC_sizes:
+ case OMPC_permutation:
case OMPC_allocator:
case OMPC_allocate:
case OMPC_collapse:
@@ -512,6 +513,7 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
case OMPC_safelen:
case OMPC_simdlen:
case OMPC_sizes:
+ case OMPC_permutation:
case OMPC_allocator:
case OMPC_allocate:
case OMPC_collapse:
diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp
index 0e3e604203c86..87ff91b594018 100644
--- a/clang/lib/Parse/ParseOpenMP.cpp
+++ b/clang/lib/Parse/ParseOpenMP.cpp
@@ -3124,6 +3124,18 @@ OMPClause *Parser::ParseOpenMPSizesClause() {
OpenLoc, CloseLoc);
}
+OMPClause *Parser::ParseOpenMPPermutationClause() {
+ SourceLocation ClauseNameLoc, OpenLoc, CloseLoc;
+ SmallVector<Expr *> ArgExprs;
+ if (ParseOpenMPExprListClause(OMPC_permutation, ClauseNameLoc, OpenLoc,
+ CloseLoc, ArgExprs,
+ /*ReqIntConst=*/true))
+ return nullptr;
+
+ return Actions.OpenMP().ActOnOpenMPPermutationClause(ArgExprs, ClauseNameLoc,
+ OpenLoc, CloseLoc);
+}
+
OMPClause *Parser::ParseOpenMPUsesAllocatorClause(OpenMPDirectiveKind DKind) {
SourceLocation Loc = Tok.getLocation();
ConsumeAnyToken();
@@ -3412,6 +3424,14 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind,
Clause = ParseOpenMPSizesClause();
break;
+ case OMPC_permutation:
+ if (!FirstClause) {
+ Diag(Tok, diag::err_omp_more_one_clause)
+ << getOpenMPDirectiveName(DKind) << getOpenMPClauseName(CKind) << 0;
+ ErrorFound = true;
+ }
+ Clause = ParseOpenMPPermutationClause();
+ break;
case OMPC_uses_allocators:
Clause = ParseOpenMPUsesAllocatorClause(DKind);
break;
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index ef141003b7d61..96fe52de9b737 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -9827,25 +9827,6 @@ static Stmt *buildPreInits(ASTContext &Context,
return nullptr;
}
-/// Append the \p Item or the content of a CompoundStmt to the list \p
-/// TargetList.
-///
-/// A CompoundStmt is used as container in case multiple statements need to be
-/// stored in lieu of using an explicit list. Flattening is necessary because
-/// contained DeclStmts need to be visible after the execution of the list. Used
-/// for OpenMP pre-init declarations/statements.
-static void appendFlattendedStmtList(SmallVectorImpl<Stmt *> &TargetList,
- Stmt *Item) {
- // nullptr represents an empty list.
- if (!Item)
- return;
-
- if (auto *CS = dyn_cast<CompoundStmt>(Item))
- llvm::append_range(TargetList, CS->body());
- else
- TargetList.push_back(Item);
-}
-
/// Build preinits statement for the given declarations.
static Stmt *
buildPreInits(ASTContext &Context,
@@ -9861,13 +9842,19 @@ buildPreInits(ASTContext &Context,
/// Build pre-init statement for the given statements.
static Stmt *buildPreInits(ASTContext &Context, ArrayRef<Stmt *> PreInits) {
- if (PreInits.empty())
- return nullptr;
-
- SmallVector<Stmt *> Stmts;
- for (Stmt *S : PreInits)
- appendFlattendedStmtList(Stmts, S);
- return CompoundStmt::Create(Context, PreInits, FPOptionsOverride(), {}, {});
+ if (!PreInits.empty()) {
+ SmallVector<Stmt *> Stmts;
+ for (Stmt *S : PreInits) {
+ // Do not nest CompoundStmts.
+ if (auto *CS = dyn_cast<CompoundStmt>(S)) {
+ llvm::append_range(Stmts, CS->body());
+ continue;
+ }
+ Stmts.push_back(S);
+ }
+ return CompoundStmt::Create(Context, PreInits, FPOptionsOverride(), {}, {});
+ }
+ return nullptr;
}
/// Build postupdate expression for the given list of postupdates expressions.
@@ -9970,9 +9957,12 @@ checkOpenMPLoop(OpenMPDirectiveKind DKind, Expr *CollapseLoopCountExpr,
// Search for pre-init declared variables that need to be captured
// to be referenceable inside the directive.
SmallVector<Stmt *> Constituents;
- appendFlattendedStmtList(Constituents, DependentPreInits);
+ if (auto *CS = dyn_cast<CompoundStmt>(DependentPreInits))
+ llvm::append_range(Constituents, CS->body());
+ else
+ Constituents.push_back(DependentPreInits);
for (Stmt *S : Constituents) {
- if (auto *DC = dyn_cast<DeclStmt>(S)) {
+ if (DeclStmt *DC = dyn_cast<DeclStmt>(S)) {
for (Decl *C : DC->decls()) {
auto *D = cast<VarDecl>(C);
DeclRefExpr *Ref = buildDeclRefExpr(
@@ -15149,8 +15139,15 @@ bool SemaOpenMP::checkTransformableLoopNest(
DependentPreInits = Dir->getPreInits();
else
llvm_unreachable("Unhandled loop transformation");
-
- appendFlattendedStmtList(OriginalInits.back(), DependentPreInits);
+ if (!DependentPreInits)
+ return;
+ // CompoundStmts are used as lists of other statements, add their
+ // contents, not the lists themselves to avoid nesting. This is
+ // necessary because DeclStmts need to be visible after the pre-init.
+ else if (auto *CS = dyn_cast<CompoundStmt>(DependentPreInits))
+ llvm::append_range(OriginalInits.back(), CS->body());
+ else
+ OriginalInits.back().push_back(DependentPreInits);
});
assert(OriginalInits.back().empty() && "No preinit after innermost loop");
OriginalInits.pop_back();
@@ -15209,7 +15206,7 @@ static void collectLoopStmts(Stmt *AStmt, MutableArrayRef<Stmt *> LoopStmts) {
LoopStmts[Cnt] = CurStmt;
return false;
});
- assert(!is_contained(LoopStmts, nullptr) &&
+ assert(llvm::all_of(LoopStmts, [](Stmt *LoopStmt) { return LoopStmt; }) &&
"Expecting a loop statement for each affected loop");
}
@@ -15957,7 +15954,9 @@ StmtResult SemaOpenMP::ActOnOpenMPInterchangeDirective(
return StmtError();
// interchange without permutation clause swaps two loops.
- constexpr size_t NumLoops = 2;
+ const OMPPermutationClause *PermutationClause =
+ OMPExecutableDirective::getSingleClause<OMPPermutationClause>(Clauses);
+ size_t NumLoops = PermutationClause ? PermutationClause->getNumLoops() : 2;
// Verify and diagnose loop nest.
SmallVector<OMPLoopBasedDirective::HelperExprs, 4> LoopHelpers(NumLoops);
@@ -15972,6 +15971,12 @@ StmtResult SemaOpenMP::ActOnOpenMPInterchangeDirective(
return OMPInterchangeDirective::Create(Context, StartLoc, EndLoc, Clauses,
NumLoops, AStmt, nullptr, nullptr);
+ // An invalid expression in the permutation clause is set to nullptr in
+ // ActOnOpenMPPermutationClause.
+ if (PermutationClause && llvm::any_of(PermutationClause->getArgsRefs(),
+ [](Expr *E) { return !E; }))
+ return StmtError();
+
assert(LoopHelpers.size() == NumLoops &&
"Expecting loop iteration space dimensionaly to match number of "
"affected loops");
@@ -15980,7 +15985,44 @@ StmtResult SemaOpenMP::ActOnOpenMPInterchangeDirective(
"affected loops");
// Decode the permutation clause.
- constexpr uint64_t Permutation[] = {1, 0};
+ SmallVector<uint64_t, 2> Permutation;
+ if (!PermutationClause) {
+ Permutation = {1, 0};
+ } else {
+ ArrayRef<Expr *> PermArgs = PermutationClause->getArgsRefs();
+ llvm::BitVector Flags(PermArgs.size());
+ for (Expr *PermArg : PermArgs) {
+ std::optional<llvm::APSInt> PermCstExpr =
+ PermArg->getIntegerConstantExpr(Context);
+ if (!PermCstExpr)
+ continue;
+ uint64_t PermInt = PermCstExpr->getZExtValue();
+ assert(1 <= PermInt && PermInt <= NumLoops &&
+ "Must be a permutation; diagnostic emitted in "
+ "ActOnOpenMPPermutationClause");
+ if (Flags[PermInt - 1]) {
+ SourceRange ExprRange(PermArg->getBeginLoc(), PermArg->getEndLoc());
+ Diag(PermArg->getExprLoc(),
+ diag::err_omp_interchange_permutation_value_repeated)
+ << PermInt << ExprRange;
+ continue;
+ }
+ Flags[PermInt - 1] = true;
+
+ Permutation.push_back(PermInt - 1);
+ }
+
+ if (Permutation.size() != NumLoops)
+ return StmtError();
+ }
+
+ // Nothing to transform with trivial permutation.
+ if (NumLoops <= 1 || llvm::all_of(llvm::enumerate(Permutation), [](auto p) {
+ auto [Idx, Arg] = p;
+ return Idx == Arg;
+ }))
+ return OMPInterchangeDirective::Create(Context, StartLoc, EndLoc, Clauses,
+ NumLoops, AStmt, AStmt, nullptr);
// Find the affected loops.
SmallVector<Stmt *> LoopStmts(NumLoops, nullptr);
@@ -17948,6 +17990,44 @@ OMPClause *SemaOpenMP::ActOnOpenMPSizesClause(ArrayRef<Expr *> SizeExprs,
SanitizedSizeExprs);
}
+OMPClause *SemaOpenMP::ActOnOpenMPPermutationClause(ArrayRef<Expr *> PermExprs,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc) {
+ size_t NumLoops = PermExprs.size();
+ SmallVector<Expr *> SanitizedPermExprs;
+ llvm::append_range(SanitizedPermExprs, PermExprs);
+
+ for (Expr *&PermExpr : SanitizedPermExprs) {
+ // Skip if template-dependent or already sanitized, e.g. during a partial
+ // template instantiation.
+ if (!PermExpr || PermExpr->isInstantiationDependent())
+ continue;
+
+ llvm::APSInt PermVal;
+ ExprResult PermEvalExpr = SemaRef.VerifyIntegerConstantExpression(
+ PermExpr, &PermVal, Sema::AllowFold);
+ bool IsValid = PermEvalExpr.isUsable();
+ if (IsValid)
+ PermExpr = PermEvalExpr.get();
+
+ if (IsValid && (PermVal < 1 || NumLoops < PermVal)) {
+ SourceRange ExprRange(PermEvalExpr.get()->getBeginLoc(),
+ PermEvalExpr.get()->getEndLoc());
+ Diag(PermEvalExpr.get()->getExprLoc(),
+ diag::err_omp_interchange_permutation_value_range)
+ << NumLoops << ExprRange;
+ IsValid = false;
+ }
+
+ if (!PermExpr->isInstantiationDependent() && !IsValid)
+ PermExpr = nullptr;
+ }
+
+ return OMPPermutationClause::Create(getASTContext(), StartLoc, LParenLoc,
+ EndLoc, SanitizedPermExprs);
+}
+
OMPClause *SemaOpenMP::ActOnOpenMPFullClause(SourceLocation StartLoc,
SourceLocation EndLoc) {
return OMPFullClause::Create(getASTContext(), StartLoc, EndLoc);
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index 8da35f522d8ff..f70eabc3e9346 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -1746,6 +1746,15 @@ class TreeTransform {
EndLoc);
}
+ /// Build a new OpenMP 'permutation' clause.
+ OMPClause *RebuildOMPPermutationClause(ArrayRef<Expr *> PermExprs,
+ SourceLocation StartLoc,
+ SourceLocation LParenLoc,
+ SourceLocation EndLoc) {
+ return getSema().OpenMP().ActOnOpenMPPermutationClause(PermExprs, StartLoc,
+ LParenLoc, EndLoc);
+ }
+
/// Build a new OpenMP 'full' clause.
OMPClause *RebuildOMPFullClause(SourceLocation StartLoc,
SourceLocation EndLoc) {
@@ -10028,6 +10037,32 @@ OMPClause *TreeTransform<Derived>::TransformOMPSizesClause(OMPSizesClause *C) {
C->getLParenLoc(), C->getEndLoc());
}
+template <typename Derived>
+OMPClause *
+TreeTransform<Derived>::TransformOMPPermutationClause(OMPPermutationClause *C) {
+ SmallVector<Expr *> TransformedArgs;
+ TransformedArgs.reserve(C->getNumLoops());
+ bool Changed = false;
+ for (Expr *E : C->getArgsRefs()) {
+ if (!E) {
+ TransformedArgs.push_back(nullptr);
+ continue;
+ }
+
+ ExprResult T = getDerived().TransformExpr(E);
+ if (T.isInvalid())
+ return nullptr;
+ if (E != T.get())
+ Changed = true;
+ TransformedArgs.push_back(T.get());
+ }
+
+ if (!Changed && !getDerived().AlwaysRebuild())
+ return C;
+ return RebuildOMPPermutationClause(TransformedArgs, C->getBeginLoc(),
+ C->getLParenLoc(), C->getEndLoc());
+}
+
template <typename Derived>
OMPClause *TreeTransform<Derived>::TransformOMPFullClause(OMPFullClause *C) {
if (!getDerived().AlwaysRebuild())
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index d7fc6697eaf74..932386567e4d8 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -10305,6 +10305,11 @@ OMPClause *OMPClauseReader::readClause() {
C = OMPSizesClause::CreateEmpty(Context, NumSizes);
break;
}
+ case llvm::omp::OMPC_permutation: {
+ unsigned NumLoops = Record.readInt();
+ C = OMPPermutationClause::CreateEmpty(Context, NumLoops);
+ break;
+ }
case llvm::omp::OMPC_full:
C = OMPFullClause::CreateEmpty(Context);
break;
@@ -10671,6 +10676,12 @@ void OMPClauseReader::VisitOMPSizesClause(OMPSizesClause *C) {
C->setLParenLoc(Record.readSourceLocation());
}
+void OMPClauseReader::VisitOMPPermutationClause(OMPPermutationClause *C) {
+ for (Expr *&E : C->getArgsRefs())
+ E = Record.readSubExpr();
+ C->setLParenLoc(Record.readSourceLocation());
+}
+
void OMPClauseReader::VisitOMPFullClause(OMPFullClause *C) {}
void OMPClauseReader::VisitOMPPartialClause(OMPPartialClause *C) {
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 00b0e48083217..6c4b066e11ce9 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -7032,6 +7032,13 @@ void OMPClauseWriter::VisitOMPSizesClause(OMPSizesClause *C) {
Record.AddSourceLocation(C->getLParenLoc());
}
+void OMPClauseWriter::VisitOMPPermutationClause(OMPPermutationClause *C) {
+ Record.push_back(C->getNumLoops());
+ for (Expr *Size : C->getArgsRefs())
+ Record.AddStmt(Size);
+ Record.AddSourceLocation(C->getLParenLoc());
+}
+
void OMPClauseWriter::VisitOMPFullClause(OMPFullClause *C) {}
void OMPClauseWriter::VisitOMPPartialClause(OMPPartialClause *C) {
diff --git a/clang/test/OpenMP/interchange_ast_print.cpp b/clang/test/OpenMP/interchange_ast_print.cpp
index f8bf075cd300f..4b0818ff6eb7f 100644
--- a/clang/test/OpenMP/interchange_ast_print.cpp
+++ b/clang/test/OpenMP/interchange_ast_print.cpp
@@ -35,6 +35,35 @@ void foo1() {
}
+// PRINT-LABEL: void foo2(
+// DUMP-LABEL: FunctionDecl {{.*}} foo2
+void foo2(int start1, int start2, int start3, int end1, int end2, int end3) {
+ // PRINT: #pragma omp interchange permutation(2, 3, 1)
+ // DUMP: OMPInterchangeDirective
+ // DUMP-NEXT: OMPPermutationClause
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 2
+ // DUMP-NEXT: IntegerLiteral {{.*}} 2
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 3
+ // DUMP-NEXT: IntegerLiteral {{.*}} 3
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 1
+ // DUMP-NEXT: IntegerLiteral {{.*}} 1
+ #pragma omp interchange permutation(2,3,1)
+ // PRINT: for (int i = start1; i < end1; i += 1)
+ // DUMP-NEXT: ForStmt
+ for (int i = start1; i < end1; i += 1)
+ // PRINT: for (int j = start2; j < end2; j += 1)
+ // DUMP: ForStmt
+ for (int j = start2; j < end2; j += 1)
+ // PRINT: for (int k = start3; k < end3; k += 1)
+ // DUMP: ForStmt
+ for (int k = start3; k < end3; k += 1)
+ // PRINT: body(i, j, k);
+ // DUMP: CallExpr
+ body(i, j, k);
+}
// PRINT-LABEL: void foo3(
@@ -67,6 +96,75 @@ void foo3() {
}
+// PRINT-LABEL: void foo4(
+// DUMP-LABEL: FunctionDecl {{.*}} foo4
+void foo4(int start, int end, int step) {
+ // PRINT: #pragma omp for collapse(3)
+ // DUMP: OMPForDirective
+ // DUMP-NEXT: OMPCollapseClause
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 3
+ // DUMP-NEXT: IntegerLiteral {{.*}} 3
+ // DUMP-NEXT: CapturedStmt
+ // DUMP-NEXT: CapturedDecl
+ #pragma omp for collapse(3)
+ // PRINT: for (int i = 7; i < 17; i += 1)
+ // DUMP-NEXT: ForStmt
+ for (int i = 7; i < 17; i += 1)
+ // PRINT: #pragma omp interchange permutation(1)
+ // DUMP: OMPInterchangeDirective
+ // DUMP-NEXT: OMPPermutationClause
+ // DUMP-NEXT: ConstantExpr
+ // DUMP-NEXT: value: Int 1
+ // DUMP-NEXT: IntegerLiteral {{.*}} 1
+ #pragma omp interchange permutation(1)
+ // PRINT: for (int j = 7; j < 17; j += 1)
+ // DUMP-NEXT: ForStmt
+ for (int j = 7; j < 17; j += 1)
+ // PRINT: for (int k = 7; k < 17; k += 1)
+ // DUMP: ForStmt
+ for (int k = 7; k < 17; k += 1)
+ // PRINT: body(i, j, k);
+ // DUMP: CallExpr
+ body(i, j, k);
+}
+
+
+// PRINT-LABEL: void foo5(
+// DUMP-LABEL: FunctionTemplateDecl {{.*}} foo5
+template<typename T, T P>
+void foo5(T start, T end) {
+ // PRINT: #pragma omp for
+ // DUMP: OMPForDirective
+ #pragma omp for
+ // PRINT: #pragma omp interchange permutation(P + 1, 2 - P)
+ // DUMP: OMPInterchangeDirective
+ // DUMP-NEXT: OMPPermutationClause
+ // DUMP-NEXT: BinaryOperator {{.*}} '+'
+ // DUMP-NEXT: DeclRefExpr {{.*}} 'P' 'T'
+ // DUMP-NEXT: IntegerLiteral {{.*}} 'int' 1
+ // DUMP-NEXT: BinaryOperator {{.*}} '-'
+ // DUMP-NEXT: IntegerLiteral {{.*}} 'int' 2
+ // DUMP-NEXT: DeclRefExpr {{.*}} 'P' 'T'
+ #pragma omp interchange permutation(P + 1, 2 - P)
+ // PRINT-NEXT: for (T i = start; i < end; i += 2)
+ // DUMP-NEXT: ForStmt
+ for (T i = start; i < end; i += 2)
+ // PRINT-NEXT: for (T j = start; j < end; j += 2)
+ // DUMP: ForStmt
+ for (T j = start; j < end; j += 2)
+ // PRINT-NEXT: body(i, j);
+ // DUMP: CallExpr
+ body(i,j);
+}
+
+// Also test instantiating the template.
+void tfoo5() {
+ foo5<int,0>(0, 42);
+ foo5<int,1>(0, 42);
+}
+
+
// PRINT-LABEL: void foo6(
// DUMP-LABEL: FunctionTemplateDecl {{.*}} foo6
template<int Tile>
diff --git a/clang/test/OpenMP/interchange_codegen.cpp b/clang/test/OpenMP/interchange_codegen.cpp
index 9c1782183cf98..f21b4db379465 100644
--- a/clang/test/OpenMP/interchange_codegen.cpp
+++ b/clang/test/OpenMP/interchange_codegen.cpp
@@ -17,6 +17,12 @@
extern "C" void body(...) {}
+extern "C" void foo1(int start, int end, int step) {
+ int i;
+#pragma omp interchange permutation(1)
+ for (i = start; i < end; i += step)
+ body(i);
+}
extern "C" void foo2(int start1, int start2, int end1, int end2, int step1, int step2) {
@@ -46,6 +52,16 @@ extern "C" void foo4() {
}
+extern "C" void foo5() {
+#pragma omp for collapse(3)
+ for (int i = 7; i < 17; i += 3)
+#pragma omp interchange permutation(1)
+ for (int j = 7; j < 17; j += 3)
+ for (int k = 7; k < 17; k += 3)
+ body(i, j, k);
+}
+
+
extern "C" void foo6() {
#pragma omp for collapse(4)
for (int i = 7; i < 17; i += 3)
@@ -57,6 +73,34 @@ extern "C" void foo6() {
}
+extern "C" void foo7() {
+#pragma omp interchange permutation(2,3,4,1)
+ for (int i = 7; i < 17; i += 3)
+ for (int j = 7; j < 17; j += 3)
+ for (int k = 7; k < 17; k += 3)
+ for (int l = 7; l < 17; l += 3)
+ body(i, j, k, l);
+}
+
+
+template<int TILESIZE>
+void foo8(int start, int end, int step) {
+ #pragma omp for collapse(4)
+ for (int i = start; i < end; i += step)
+ #pragma omp interchange permutation(1)
+ for (int j = start; j < end; j += step)
+ #pragma omp tile sizes(TILESIZE)
+ for (int k = start; k < end; k += step)
+ body(i, j, k);
+}
+
+// Also test instantiating the template.
+extern "C" void tfoo8() {
+ foo8<32>(0, 42, 1);
+ foo8<64>(0, 42, 3);
+}
+
+
extern "C" void foo9() {
double arr[128];
#pragma omp interchange
@@ -78,13 +122,44 @@ extern "C" void foo10() {
}
#endif /* HEADER */
-
// CHECK1-LABEL: define {{[^@]+}}@body
// CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: ret void
//
//
+// CHECK1-LABEL: define {{[^@]+}}@foo1
+// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: ret void
+//
+//
// CHECK1-LABEL: define {{[^@]+}}@foo2
// CHECK1-SAME: (i32 noundef [[START1:%.*]], i32 noundef [[START2:%.*]], i32 noundef [[END1:%.*]], i32 noundef [[END2:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry:
@@ -186,14 +261,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
// CHECK1: for.inc22:
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK1: for.end24:
// CHECK1-NEXT: ret void
//
@@ -266,7 +341,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -363,7 +438,7 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
@@ -381,6 +456,96 @@ extern "C" void foo10() {
// CHECK1-NEXT: ret void
//
//
+// CHECK1-LABEL: define {{[^@]+}}@foo5
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 63
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 16
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 16
+// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 16
+// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]]
+// CHECK1-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 4
+// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 3
+// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 16
+// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 16
+// CHECK1-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 16
+// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 16
+// CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]]
+// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 4
+// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 4
+// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]]
+// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 3
+// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]
+// CHECK1-NEXT: store i32 [[ADD19]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 1
+// CHECK1-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
// CHECK1-LABEL: define {{[^@]+}}@foo6
// CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry:
@@ -519,6 +684,1529 @@ extern "C" void foo10() {
// CHECK1-NEXT: ret void
//
//
+// CHECK1-LABEL: define {{[^@]+}}@foo7
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[L:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[K]], align 4
+// CHECK1-NEXT: store i32 7, ptr [[L]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: br label [[FOR_COND:%.*]]
+// CHECK1: for.cond:
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
+// CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]
+// CHECK1: for.body:
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 3
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK1: for.cond1:
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 4
+// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]]
+// CHECK1: for.body3:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 3
+// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[K]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK1-NEXT: br label [[FOR_COND6:%.*]]
+// CHECK1: for.cond6:
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 4
+// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]]
+// CHECK1: for.body8:
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK1-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 3
+// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]]
+// CHECK1-NEXT: store i32 [[ADD10]], ptr [[L]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND11:%.*]]
+// CHECK1: for.cond11:
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK1-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 4
+// CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]
+// CHECK1: for.body13:
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK1-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 3
+// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]]
+// CHECK1-NEXT: store i32 [[ADD15]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]])
+// CHECK1-NEXT: br label [[FOR_INC:%.*]]
+// CHECK1: for.inc:
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1: for.end:
+// CHECK1-NEXT: br label [[FOR_INC16:%.*]]
+// CHECK1: for.inc16:
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK1-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK1-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK1: for.end18:
+// CHECK1-NEXT: br label [[FOR_INC19:%.*]]
+// CHECK1: for.inc19:
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK1-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK1-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK1: for.end21:
+// CHECK1-NEXT: br label [[FOR_INC22:%.*]]
+// CHECK1: for.inc22:
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK1: for.end24:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@tfoo8
+// CHECK1-SAME: () #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1)
+// CHECK1-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3)
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii
+// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]
+// CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]
+// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1
+// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32
+// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
+// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
+// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31
+// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32
+// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
+// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
+// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
+// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
+// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
+// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
+// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
+// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
+// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
+// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK1: land.lhs.true:
+// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
+// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true45:
+// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
+// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true47:
+// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
+// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.then:
+// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
+// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
+// CHECK1: cond.true54:
+// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: br label [[COND_END56:%.*]]
+// CHECK1: cond.false55:
+// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: br label [[COND_END56]]
+// CHECK1: cond.end56:
+// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
+// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
+// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
+// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
+// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
+// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
+// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
+// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31
+// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32
+// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
+// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
+// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
+// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
+// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
+// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
+// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
+// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
+// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
+// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
+// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
+// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
+// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
+// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
+// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
+// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
+// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
+// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31
+// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32
+// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
+// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
+// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
+// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
+// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
+// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
+// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
+// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
+// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
+// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
+// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
+// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31
+// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32
+// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
+// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
+// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
+// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
+// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
+// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
+// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
+// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
+// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31
+// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32
+// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
+// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
+// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
+// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
+// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
+// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
+// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
+// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
+// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
+// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
+// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
+// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
+// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
+// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
+// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
+// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
+// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
+// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
+// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31
+// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32
+// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
+// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
+// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
+// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
+// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
+// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
+// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
+// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
+// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
+// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
+// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
+// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
+// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31
+// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32
+// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
+// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
+// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
+// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
+// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
+// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
+// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
+// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
+// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
+// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
+// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
+// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
+// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31
+// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32
+// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
+// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
+// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
+// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
+// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
+// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
+// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
+// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
+// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
+// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
+// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
+// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
+// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31
+// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32
+// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
+// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
+// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
+// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
+// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
+// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
+// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
+// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
+// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
+// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31
+// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32
+// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
+// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
+// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
+// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
+// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
+// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
+// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
+// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31
+// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32
+// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
+// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
+// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
+// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
+// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
+// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
+// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
+// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
+// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
+// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
+// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
+// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
+// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
+// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
+// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
+// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
+// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32
+// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
+// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
+// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
+// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
+// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
+// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
+// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
+// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
+// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
+// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31
+// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32
+// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
+// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
+// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
+// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
+// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
+// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
+// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
+// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
+// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
+// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
+// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
+// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
+// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
+// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31
+// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32
+// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
+// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
+// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
+// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
+// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
+// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
+// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
+// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
+// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
+// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
+// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
+// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
+// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
+// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31
+// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32
+// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
+// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
+// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
+// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
+// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
+// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
+// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
+// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
+// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
+// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
+// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
+// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
+// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
+// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31
+// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32
+// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
+// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
+// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
+// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
+// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
+// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
+// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
+// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
+// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
+// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31
+// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32
+// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
+// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
+// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
+// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
+// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
+// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
+// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
+// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
+// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31
+// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32
+// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
+// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
+// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
+// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
+// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
+// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
+// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
+// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
+// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
+// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
+// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
+// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
+// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
+// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
+// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31
+// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32
+// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
+// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
+// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
+// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
+// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
+// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
+// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
+// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
+// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
+// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
+// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
+// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
+// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
+// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31
+// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32
+// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
+// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
+// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
+// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
+// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
+// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
+// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
+// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
+// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
+// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
+// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
+// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
+// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
+// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
+// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31
+// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32
+// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
+// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
+// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
+// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
+// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
+// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
+// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
+// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
+// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
+// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
+// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
+// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
+// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
+// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31
+// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32
+// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
+// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
+// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
+// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
+// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
+// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
+// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
+// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
+// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
+// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31
+// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32
+// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
+// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
+// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
+// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
+// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
+// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
+// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
+// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
+// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31
+// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32
+// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
+// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
+// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
+// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
+// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
+// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
+// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
+// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
+// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
+// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
+// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
+// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
+// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
+// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
+// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
+// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
+// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
+// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
+// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
+// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
+// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
+// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
+// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
+// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
+// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
+// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
+// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
+// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
+// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
+// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
+// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
+// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.end:
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii
+// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP7]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]
+// CHECK1-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]
+// CHECK1-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1
+// CHECK1-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1
+// CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64
+// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
+// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK1: cond.true:
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
+// CHECK1-NEXT: br label [[COND_END:%.*]]
+// CHECK1: cond.false:
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64
+// CHECK1-NEXT: br label [[COND_END]]
+// CHECK1: cond.end:
+// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
+// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
+// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
+// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
+// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63
+// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64
+// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
+// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
+// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
+// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
+// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
+// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
+// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
+// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
+// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
+// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
+// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
+// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK1: land.lhs.true:
+// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
+// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true45:
+// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
+// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: land.lhs.true47:
+// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
+// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.then:
+// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
+// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
+// CHECK1: cond.true54:
+// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK1-NEXT: br label [[COND_END56:%.*]]
+// CHECK1: cond.false55:
+// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: br label [[COND_END56]]
+// CHECK1: cond.end56:
+// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
+// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK1: omp.inner.for.cond:
+// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
+// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK1: omp.inner.for.body:
+// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
+// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
+// CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
+// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
+// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
+// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63
+// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64
+// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
+// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
+// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
+// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
+// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
+// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
+// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
+// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
+// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
+// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
+// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
+// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
+// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
+// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
+// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
+// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
+// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
+// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63
+// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64
+// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
+// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
+// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
+// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
+// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
+// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
+// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
+// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
+// CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
+// CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
+// CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
+// CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63
+// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64
+// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
+// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
+// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
+// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
+// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
+// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
+// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
+// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
+// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63
+// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64
+// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
+// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
+// CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
+// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
+// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
+// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
+// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
+// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
+// CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
+// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
+// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
+// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
+// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
+// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
+// CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
+// CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
+// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
+// CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
+// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63
+// CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64
+// CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
+// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
+// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
+// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
+// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
+// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
+// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
+// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
+// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
+// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
+// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
+// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
+// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63
+// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64
+// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
+// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
+// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
+// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
+// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
+// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
+// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
+// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
+// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
+// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
+// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
+// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
+// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63
+// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64
+// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
+// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
+// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
+// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
+// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
+// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
+// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
+// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
+// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
+// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
+// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
+// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
+// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63
+// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64
+// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
+// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
+// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
+// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
+// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
+// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
+// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
+// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
+// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
+// CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63
+// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64
+// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
+// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
+// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
+// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
+// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
+// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
+// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
+// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63
+// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64
+// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
+// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
+// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
+// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
+// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
+// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
+// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
+// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
+// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
+// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
+// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
+// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
+// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
+// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
+// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
+// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
+// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64
+// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
+// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
+// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
+// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
+// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
+// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
+// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
+// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
+// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
+// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63
+// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64
+// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
+// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
+// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
+// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
+// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
+// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
+// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
+// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
+// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
+// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
+// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
+// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
+// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
+// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63
+// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64
+// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
+// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
+// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
+// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
+// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
+// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
+// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
+// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
+// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
+// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
+// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
+// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
+// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
+// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63
+// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64
+// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
+// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
+// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
+// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
+// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
+// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
+// CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
+// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
+// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
+// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
+// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
+// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
+// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
+// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63
+// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64
+// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
+// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
+// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
+// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
+// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
+// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
+// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
+// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
+// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
+// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63
+// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64
+// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
+// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
+// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
+// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
+// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
+// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
+// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
+// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
+// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63
+// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64
+// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
+// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
+// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
+// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
+// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
+// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
+// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
+// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
+// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
+// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
+// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
+// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
+// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
+// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
+// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63
+// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64
+// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
+// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
+// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
+// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
+// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
+// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
+// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
+// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
+// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
+// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
+// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
+// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
+// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
+// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63
+// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64
+// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
+// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
+// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
+// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
+// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
+// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
+// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
+// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
+// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
+// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
+// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
+// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
+// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
+// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
+// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63
+// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64
+// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
+// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
+// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
+// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
+// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
+// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
+// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
+// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
+// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
+// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
+// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
+// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
+// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
+// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63
+// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64
+// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
+// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
+// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
+// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
+// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
+// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
+// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
+// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
+// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
+// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63
+// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64
+// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
+// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
+// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
+// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
+// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
+// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
+// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
+// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
+// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63
+// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64
+// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
+// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
+// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
+// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
+// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
+// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
+// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
+// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
+// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
+// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
+// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
+// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
+// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
+// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
+// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
+// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
+// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
+// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
+// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
+// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
+// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
+// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
+// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
+// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
+// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
+// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
+// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
+// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
+// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
+// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
+// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
+// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
+// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
+// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK1: omp.inner.for.inc:
+// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
+// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp.loop.exit:
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK1: omp.precond.end:
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK1-NEXT: ret void
+//
+//
// CHECK1-LABEL: define {{[^@]+}}@foo9
// CHECK1-SAME: () #[[ATTR0]] {
// CHECK1-NEXT: entry:
@@ -597,14 +2285,14 @@ extern "C" void foo10() {
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
// CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
// CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
-// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK1: for.end:
// CHECK1-NEXT: br label [[FOR_INC13:%.*]]
// CHECK1: for.inc13:
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
// CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
// CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
-// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK1: for.end15:
// CHECK1-NEXT: ret void
//
@@ -1040,6 +2728,38 @@ extern "C" void foo10() {
// CHECK2-NEXT: ret void
//
//
+// CHECK2-LABEL: define {{[^@]+}}@foo1
+// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP3]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: ret void
+//
+//
// CHECK2-LABEL: define {{[^@]+}}@foo10
// CHECK2-SAME: () #[[ATTR0]] {
// CHECK2-NEXT: entry:
@@ -1566,14 +3286,14 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP3:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
// CHECK2: for.inc22:
// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
// CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1
// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK2: for.end24:
// CHECK2-NEXT: ret void
//
@@ -1646,7 +3366,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -1743,7 +3463,7 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4
// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
@@ -1761,6 +3481,96 @@ extern "C" void foo10() {
// CHECK2-NEXT: ret void
//
//
+// CHECK2-LABEL: define {{[^@]+}}@foo5
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 63
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 16
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP8]], 16
+// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 16
+// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL5]]
+// CHECK2-NEXT: [[DIV6:%.*]] = sdiv i32 [[SUB]], 4
+// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 3
+// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV9:%.*]] = sdiv i32 [[TMP10]], 16
+// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 16
+// CHECK2-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP9]], [[MUL10]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[DIV12:%.*]] = sdiv i32 [[TMP12]], 16
+// CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 16
+// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP11]], [[MUL13]]
+// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 4
+// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 4
+// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]]
+// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 3
+// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]
+// CHECK2-NEXT: store i32 [[ADD19]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]], i32 noundef [[TMP14]], i32 noundef [[TMP15]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 1
+// CHECK2-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
// CHECK2-LABEL: define {{[^@]+}}@foo6
// CHECK2-SAME: () #[[ATTR0]] {
// CHECK2-NEXT: entry:
@@ -1899,6 +3709,101 @@ extern "C" void foo10() {
// CHECK2-NEXT: ret void
//
//
+// CHECK2-LABEL: define {{[^@]+}}@foo7
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[L:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_0_IV_J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_1_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_2_IV_L:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTPERMUTED_3_IV_I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 7, ptr [[I]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[J]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[K]], align 4
+// CHECK2-NEXT: store i32 7, ptr [[L]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: br label [[FOR_COND:%.*]]
+// CHECK2: for.cond:
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
+// CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END24:%.*]]
+// CHECK2: for.body:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], 3
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1:%.*]]
+// CHECK2: for.cond1:
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP2]], 4
+// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END21:%.*]]
+// CHECK2: for.body3:
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP3]], 3
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[K]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK2-NEXT: br label [[FOR_COND6:%.*]]
+// CHECK2: for.cond6:
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP4]], 4
+// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END18:%.*]]
+// CHECK2: for.body8:
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK2-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP5]], 3
+// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 7, [[MUL9]]
+// CHECK2-NEXT: store i32 [[ADD10]], ptr [[L]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND11:%.*]]
+// CHECK2: for.cond11:
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK2-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP6]], 4
+// CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]
+// CHECK2: for.body13:
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK2-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP7]], 3
+// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 7, [[MUL14]]
+// CHECK2-NEXT: store i32 [[ADD15]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[L]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]], i32 noundef [[TMP9]], i32 noundef [[TMP10]], i32 noundef [[TMP11]])
+// CHECK2-NEXT: br label [[FOR_INC:%.*]]
+// CHECK2: for.inc:
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4
+// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2: for.end:
+// CHECK2-NEXT: br label [[FOR_INC16:%.*]]
+// CHECK2: for.inc16:
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK2-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
+// CHECK2-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4
+// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]]
+// CHECK2: for.end18:
+// CHECK2-NEXT: br label [[FOR_INC19:%.*]]
+// CHECK2: for.inc19:
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK2-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1
+// CHECK2-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4
+// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]]
+// CHECK2: for.end21:
+// CHECK2-NEXT: br label [[FOR_INC22:%.*]]
+// CHECK2: for.inc22:
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
+// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
+// CHECK2: for.end24:
+// CHECK2-NEXT: ret void
+//
+//
// CHECK2-LABEL: define {{[^@]+}}@foo9
// CHECK2-SAME: () #[[ATTR0]] {
// CHECK2-NEXT: entry:
@@ -1977,14 +3882,1442 @@ extern "C" void foo10() {
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
// CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1
// CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8
-// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK2: for.end:
// CHECK2-NEXT: br label [[FOR_INC13:%.*]]
// CHECK2: for.inc13:
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4
// CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1
// CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4
-// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
// CHECK2: for.end15:
// CHECK2-NEXT: ret void
//
+//
+// CHECK2-LABEL: define {{[^@]+}}@tfoo8
+// CHECK2-SAME: () #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: call void @_Z4foo8ILi32EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 1)
+// CHECK2-NEXT: call void @_Z4foo8ILi64EEviii(i32 noundef 0, i32 noundef 42, i32 noundef 3)
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi32EEviii
+// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]
+// CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]
+// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1
+// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32
+// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
+// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
+// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
+// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
+// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31
+// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32
+// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
+// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
+// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
+// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
+// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
+// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
+// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
+// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
+// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
+// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
+// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK2: land.lhs.true:
+// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
+// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true45:
+// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
+// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true47:
+// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
+// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.then:
+// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
+// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
+// CHECK2: cond.true54:
+// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: br label [[COND_END56:%.*]]
+// CHECK2: cond.false55:
+// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: br label [[COND_END56]]
+// CHECK2: cond.end56:
+// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
+// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
+// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
+// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
+// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
+// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
+// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
+// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31
+// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32
+// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
+// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
+// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
+// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
+// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
+// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
+// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
+// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
+// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
+// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
+// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
+// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
+// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
+// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
+// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
+// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
+// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
+// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31
+// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32
+// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
+// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
+// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
+// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
+// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
+// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
+// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
+// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
+// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
+// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
+// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
+// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31
+// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32
+// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
+// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
+// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
+// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
+// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
+// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
+// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
+// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
+// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31
+// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32
+// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
+// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
+// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
+// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
+// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
+// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
+// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
+// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
+// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
+// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
+// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
+// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
+// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
+// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
+// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
+// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
+// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
+// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
+// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31
+// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32
+// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
+// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
+// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
+// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
+// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
+// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
+// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
+// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
+// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
+// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
+// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
+// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
+// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31
+// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32
+// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
+// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
+// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
+// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
+// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
+// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
+// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
+// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
+// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
+// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
+// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
+// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
+// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31
+// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32
+// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
+// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
+// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
+// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
+// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
+// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
+// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
+// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
+// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
+// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
+// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
+// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
+// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31
+// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32
+// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
+// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
+// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
+// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
+// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
+// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
+// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
+// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
+// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
+// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31
+// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32
+// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
+// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
+// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
+// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
+// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
+// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
+// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
+// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31
+// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32
+// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
+// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
+// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
+// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
+// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
+// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
+// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
+// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
+// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
+// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
+// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
+// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
+// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
+// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
+// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
+// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
+// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32
+// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
+// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
+// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
+// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
+// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
+// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
+// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
+// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
+// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
+// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31
+// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32
+// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
+// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
+// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
+// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
+// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
+// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
+// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
+// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
+// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
+// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
+// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
+// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
+// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
+// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31
+// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32
+// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
+// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
+// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
+// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
+// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
+// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
+// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
+// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
+// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
+// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
+// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
+// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
+// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
+// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31
+// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32
+// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
+// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
+// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
+// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
+// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
+// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
+// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
+// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
+// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
+// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
+// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
+// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
+// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
+// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31
+// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32
+// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
+// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
+// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
+// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
+// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
+// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
+// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
+// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
+// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
+// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31
+// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32
+// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
+// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
+// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
+// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
+// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
+// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
+// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
+// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
+// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31
+// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32
+// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
+// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
+// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
+// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
+// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
+// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
+// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
+// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
+// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
+// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
+// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
+// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
+// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
+// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
+// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31
+// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32
+// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
+// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
+// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
+// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
+// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
+// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
+// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
+// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
+// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
+// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
+// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
+// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
+// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
+// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31
+// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32
+// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
+// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
+// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
+// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
+// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
+// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
+// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
+// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
+// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
+// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
+// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
+// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
+// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
+// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
+// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31
+// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32
+// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
+// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
+// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
+// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
+// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
+// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
+// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
+// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
+// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
+// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
+// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
+// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
+// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
+// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31
+// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32
+// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
+// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
+// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
+// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
+// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
+// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
+// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
+// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
+// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
+// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31
+// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32
+// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
+// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
+// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
+// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
+// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
+// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
+// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
+// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
+// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31
+// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32
+// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
+// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
+// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
+// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
+// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
+// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
+// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
+// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
+// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
+// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
+// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
+// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
+// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
+// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
+// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
+// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
+// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
+// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
+// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
+// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
+// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
+// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
+// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
+// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
+// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
+// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
+// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
+// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
+// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
+// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
+// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
+// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.end:
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_Z4foo8ILi64EEviii
+// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] comdat {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP7:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
+// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+// CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP7]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[START_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[END_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[STEP_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_9]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP11]], [[TMP12]]
+// CHECK2-NEXT: [[SUB12:%.*]] = sub i32 [[SUB]], 1
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB12]], [[TMP13]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP14]]
+// CHECK2-NEXT: [[SUB13:%.*]] = sub i32 [[DIV]], 1
+// CHECK2-NEXT: store i32 [[SUB13]], ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1
+// CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64
+// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]]
+// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK2: cond.true:
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4
+// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1
+// CHECK2-NEXT: br label [[COND_END:%.*]]
+// CHECK2: cond.false:
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4
+// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64
+// CHECK2-NEXT: br label [[COND_END]]
+// CHECK2: cond.end:
+// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ]
+// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]]
+// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]]
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]]
+// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]]
+// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1
+// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]]
+// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]]
+// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]]
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63
+// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64
+// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64
+// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]]
+// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]]
+// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1
+// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1
+// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
+// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64
+// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]]
+// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1
+// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4
+// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4
+// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4
+// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
+// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]]
+// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK2: land.lhs.true:
+// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
+// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true45:
+// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]]
+// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: land.lhs.true47:
+// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]]
+// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.then:
+// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
+// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]]
+// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]]
+// CHECK2: cond.true54:
+// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8
+// CHECK2-NEXT: br label [[COND_END56:%.*]]
+// CHECK2: cond.false55:
+// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: br label [[COND_END56]]
+// CHECK2: cond.end56:
+// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ]
+// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
+// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK2: omp.inner.for.cond:
+// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
+// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]]
+// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK2: omp.inner.for.body:
+// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64
+// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]]
+// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1
+// CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]]
+// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]]
+// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]]
+// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63
+// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64
+// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]]
+// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1
+// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1
+// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1
+// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]]
+// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64
+// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]]
+// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4
+// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64
+// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]]
+// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]]
+// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32
+// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64
+// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]]
+// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1
+// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]]
+// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]]
+// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]]
+// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63
+// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64
+// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]]
+// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]]
+// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1
+// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1
+// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
+// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]]
+// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64
+// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]]
+// CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]]
+// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1
+// CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]]
+// CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]]
+// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]]
+// CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63
+// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64
+// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]]
+// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]]
+// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1
+// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1
+// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1
+// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]]
+// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64
+// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]]
+// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]]
+// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63
+// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64
+// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]]
+// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]]
+// CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1
+// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1
+// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1
+// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]]
+// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64
+// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]]
+// CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64
+// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]]
+// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]]
+// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32
+// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4
+// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]]
+// CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1
+// CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]]
+// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]]
+// CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]]
+// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63
+// CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64
+// CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]]
+// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]]
+// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1
+// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1
+// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1
+// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]]
+// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64
+// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]]
+// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]]
+// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1
+// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]]
+// CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]]
+// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]]
+// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63
+// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64
+// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]]
+// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]]
+// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1
+// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1
+// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1
+// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]]
+// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64
+// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]]
+// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]]
+// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]]
+// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1
+// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]]
+// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]]
+// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]]
+// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63
+// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64
+// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]]
+// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]]
+// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1
+// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1
+// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1
+// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]]
+// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64
+// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]]
+// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]]
+// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1
+// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]]
+// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]]
+// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]]
+// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63
+// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64
+// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]]
+// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]]
+// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1
+// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1
+// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1
+// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]]
+// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64
+// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]]
+// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]]
+// CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63
+// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64
+// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]]
+// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]]
+// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1
+// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1
+// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1
+// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]]
+// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64
+// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]]
+// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63
+// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64
+// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]]
+// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]]
+// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1
+// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1
+// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1
+// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]]
+// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64
+// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]]
+// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]]
+// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]]
+// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1
+// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1
+// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1
+// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]]
+// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64
+// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]]
+// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64
+// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]]
+// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32
+// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4
+// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64
+// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]]
+// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1
+// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]]
+// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]]
+// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]]
+// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63
+// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64
+// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]]
+// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]]
+// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1
+// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1
+// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1
+// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]]
+// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64
+// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]]
+// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]]
+// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1
+// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]]
+// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]]
+// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]]
+// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63
+// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64
+// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]]
+// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]]
+// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1
+// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1
+// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1
+// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]]
+// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64
+// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]]
+// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]]
+// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]]
+// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1
+// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]]
+// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]]
+// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]]
+// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63
+// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64
+// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]]
+// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]]
+// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1
+// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1
+// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1
+// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]]
+// CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64
+// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]]
+// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]]
+// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1
+// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]]
+// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]]
+// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]]
+// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63
+// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64
+// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]]
+// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]]
+// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1
+// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1
+// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1
+// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]]
+// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64
+// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]]
+// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]]
+// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63
+// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64
+// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]]
+// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]]
+// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1
+// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1
+// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1
+// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]]
+// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64
+// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]]
+// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63
+// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64
+// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]]
+// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]]
+// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1
+// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1
+// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1
+// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]]
+// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64
+// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]]
+// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]]
+// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]]
+// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1
+// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]]
+// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]]
+// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]]
+// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63
+// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64
+// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]]
+// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]]
+// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1
+// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1
+// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1
+// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]]
+// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64
+// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]]
+// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]]
+// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1
+// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]]
+// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]]
+// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]]
+// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63
+// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64
+// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]]
+// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]]
+// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1
+// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1
+// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1
+// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]]
+// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64
+// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]]
+// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]]
+// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]]
+// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1
+// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]]
+// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]]
+// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]]
+// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63
+// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64
+// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]]
+// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]]
+// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1
+// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1
+// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1
+// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]]
+// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64
+// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]]
+// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
+// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
+// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]]
+// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1
+// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]]
+// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4
+// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]]
+// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]]
+// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63
+// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64
+// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]]
+// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]]
+// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1
+// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1
+// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1
+// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]]
+// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64
+// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]]
+// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]]
+// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63
+// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64
+// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]]
+// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]]
+// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1
+// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1
+// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1
+// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]]
+// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64
+// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]]
+// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4
+// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63
+// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64
+// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]]
+// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]]
+// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1
+// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1
+// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1
+// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]]
+// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64
+// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]]
+// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]]
+// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]]
+// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1
+// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1
+// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1
+// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]]
+// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64
+// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]]
+// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
+// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4
+// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]]
+// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1
+// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1
+// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1
+// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]]
+// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64
+// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]]
+// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]]
+// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1
+// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]]
+// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32
+// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4
+// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4
+// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4
+// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]]
+// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]]
+// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4
+// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4
+// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4
+// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4
+// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]])
+// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK2: omp.body.continue:
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK2: omp.inner.for.inc:
+// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1
+// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp.loop.exit:
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK2: omp.precond.end:
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
+// CHECK2-NEXT: ret void
+
diff --git a/clang/test/OpenMP/interchange_messages.cpp b/clang/test/OpenMP/interchange_messages.cpp
index 175c2f1efa744..7b9a4963445e4 100644
--- a/clang/test/OpenMP/interchange_messages.cpp
+++ b/clang/test/OpenMP/interchange_messages.cpp
@@ -2,12 +2,102 @@
void func() {
+ // expected-error at +1 {{expected '('}}
+ #pragma omp interchange permutation
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +2 {{expected expression}}
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp interchange permutation(
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{expected expression}}
+ #pragma omp interchange permutation()
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp interchange permutation(1
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +2 {{expected expression}}
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp interchange permutation(1,
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{expected expression}}
+ #pragma omp interchange permutation(1,)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +2 {{expected expression}}
+ // expected-error at +1 {{expected ')'}} expected-note at +1 {{to match this '('}}
+ #pragma omp interchange permutation(5+
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{expected expression}}
+ #pragma omp interchange permutation(5+)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{expected expression}}
+ #pragma omp interchange permutation(for)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{permutation index must be at least 1 and at most 1}}
+ #pragma omp interchange permutation(0)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{permutation index must be at least 1 and at most 2}}
+ #pragma omp interchange permutation(1,3)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +1 {{index 1 must appear exactly once in the permutation clause}}
+ #pragma omp interchange permutation(1,1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
+ // expected-error at +4 {{expression is not an integral constant expression}}
+ // expected-note at +3 {{read of non-const variable 'a' is not allowed in a constant expression}}
+ // expected-note at +1 {{declared here}}
+ int a;
+ #pragma omp interchange permutation(a)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
// expected-warning at +1 {{extra tokens at the end of '#pragma omp interchange' are ignored}}
#pragma omp interchange foo
for (int i = 0; i < 7; ++i)
for (int j = 0; j < 13; ++j)
;
+ // expected-error at +1 {{directive '#pragma omp interchange' cannot contain more than one 'permutation' clause}}
+ #pragma omp interchange permutation(2,1) permutation(2,1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j < 13; ++j)
+ ;
+
// expected-error at +1 {{unexpected OpenMP clause 'collapse' in directive '#pragma omp interchange'}}
#pragma omp interchange collapse(2)
for (int i = 0; i < 7; ++i)
@@ -75,3 +165,67 @@ void func() {
;
}
+
+
+template <typename T>
+static void templated_func() {
+ // In a template context, but expression itself not instantiation-dependent
+
+ // expected-error at +1 {{permutation index must be at least 1 and at most 2}}
+ #pragma omp interchange permutation(0,1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+
+ // expected-error at +1 {{index 1 must appear exactly once in the permutation clause}}
+ #pragma omp interchange permutation(1,1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+}
+
+
+
+template <int S>
+static void templated_func_value_dependent() {
+ // expected-error at +1 {{permutation index must be at least 1 and at most 2}}
+ #pragma omp interchange permutation(S,S+1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+
+ // expected-error at +1 {{index 1 must appear exactly once in the permutation clause}}
+ #pragma omp interchange permutation(S+1,S+1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+}
+
+
+template <typename T>
+static void templated_func_type_dependent() {
+ constexpr T s = 0;
+
+ // expected-error at +1 {{permutation index must be at least 1 and at most 2}}
+ #pragma omp interchange permutation(s,s+1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+
+ // expected-error at +1 {{index 1 must appear exactly once in the permutation clause}}
+ #pragma omp interchange permutation(s+1,s+1)
+ for (int i = 0; i < 7; ++i)
+ for (int j = 0; j<7; ++j)
+ ;
+}
+
+
+void template_inst() {
+ // expected-note at +1 {{in instantiation of function template specialization 'templated_func<int>' requested here}}
+ templated_func<int>();
+ // expected-note at +1 {{in instantiation of function template specialization 'templated_func_value_dependent<0>' requested here}}
+ templated_func_value_dependent<0>();
+ // expected-note at +1 {{in instantiation of function template specialization 'templated_func_type_dependent<int>' requested here}}
+ templated_func_type_dependent<int>();
+}
+
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index a6a002533936f..ec01092a06c2d 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -2373,6 +2373,12 @@ void OMPClauseEnqueue::VisitOMPSizesClause(const OMPSizesClause *C) {
Visitor->AddStmt(E);
}
+void OMPClauseEnqueue::VisitOMPPermutationClause(
+ const OMPPermutationClause *C) {
+ for (auto E : C->getArgsRefs())
+ Visitor->AddStmt(E);
+}
+
void OMPClauseEnqueue::VisitOMPFullClause(const OMPFullClause *C) {}
void OMPClauseEnqueue::VisitOMPPartialClause(const OMPPartialClause *C) {
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp b/flang/lib/Lower/OpenMP/Clauses.cpp
index 1e3fea7c4cdc7..d43c490770668 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -1136,6 +1136,12 @@ Sizes make(const parser::OmpClause::Sizes &inp,
return Sizes{/*SizeList=*/makeList(inp.v, makeExprFn(semaCtx))};
}
+Permutation make(const parser::OmpClause::Permutation &inp,
+ semantics::SemanticsContext &semaCtx) {
+ // inp.v -> std::list<parser::ScalarIntConstantExpr>
+ return Permutation{/*ArgList=*/makeList(inp.v, makeExprFn(semaCtx))};
+}
+
TaskReduction make(const parser::OmpClause::TaskReduction &inp,
semantics::SemanticsContext &semaCtx) {
// inp.v -> parser::OmpReductionClause
diff --git a/flang/lib/Lower/OpenMP/Clauses.h b/flang/lib/Lower/OpenMP/Clauses.h
index 5391b134e979d..c2d18f08e4ad5 100644
--- a/flang/lib/Lower/OpenMP/Clauses.h
+++ b/flang/lib/Lower/OpenMP/Clauses.h
@@ -205,6 +205,7 @@ using Shared = tomp::clause::SharedT<TypeTy, IdTy, ExprTy>;
using Simdlen = tomp::clause::SimdlenT<TypeTy, IdTy, ExprTy>;
using Simd = tomp::clause::SimdT<TypeTy, IdTy, ExprTy>;
using Sizes = tomp::clause::SizesT<TypeTy, IdTy, ExprTy>;
+using Permutation = tomp::clause::PermutationT<TypeTy, IdTy, ExprTy>;
using TaskReduction = tomp::clause::TaskReductionT<TypeTy, IdTy, ExprTy>;
using ThreadLimit = tomp::clause::ThreadLimitT<TypeTy, IdTy, ExprTy>;
using Threads = tomp::clause::ThreadsT<TypeTy, IdTy, ExprTy>;
diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp
index e67dbcca30e7d..154baa24742a8 100644
--- a/flang/lib/Parser/openmp-parsers.cpp
+++ b/flang/lib/Parser/openmp-parsers.cpp
@@ -343,6 +343,8 @@ TYPE_PARSER(
parenthesized(scalarIntConstantExpr))) ||
"SIZES" >> construct<OmpClause>(construct<OmpClause::Sizes>(
parenthesized(nonemptyList(scalarIntExpr)))) ||
+ "PERMUTATION" >> construct<OmpClause>(construct<OmpClause::Permutation>(
+ parenthesized(nonemptyList(scalarIntExpr)))) ||
"THREADS" >> construct<OmpClause>(construct<OmpClause::Threads>()) ||
"THREAD_LIMIT" >> construct<OmpClause>(construct<OmpClause::ThreadLimit>(
parenthesized(scalarIntExpr))) ||
diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp
index e9637b7bb591f..94af05d811a15 100644
--- a/flang/lib/Semantics/check-omp-structure.cpp
+++ b/flang/lib/Semantics/check-omp-structure.cpp
@@ -2260,6 +2260,7 @@ CHECK_SIMPLE_CLAUSE(Relaxed, OMPC_relaxed)
CHECK_SIMPLE_CLAUSE(SeqCst, OMPC_seq_cst)
CHECK_SIMPLE_CLAUSE(Simd, OMPC_simd)
CHECK_SIMPLE_CLAUSE(Sizes, OMPC_sizes)
+CHECK_SIMPLE_CLAUSE(Permutation, OMPC_permutation)
CHECK_SIMPLE_CLAUSE(TaskReduction, OMPC_task_reduction)
CHECK_SIMPLE_CLAUSE(To, OMPC_to)
CHECK_SIMPLE_CLAUSE(Uniform, OMPC_uniform)
diff --git a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h
index 13a37265762a5..97ea69ca61070 100644
--- a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+++ b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h
@@ -1067,6 +1067,14 @@ struct SizesT {
SizeList v;
};
+// V6.0: `permutation` clause
+template <typename T, typename I, typename E> //
+struct PermutationT {
+ using ArgList = ListT<E>;
+ using WrapperTrait = std::true_type;
+ ArgList v;
+};
+
// V5.2: [5.5.9] `task_reduction` clause
template <typename T, typename I, typename E> //
struct TaskReductionT {
@@ -1255,9 +1263,9 @@ using WrapperClausesT = std::variant<
NovariantsT<T, I, E>, NumTeamsT<T, I, E>, NumThreadsT<T, I, E>,
OrderedT<T, I, E>, PartialT<T, I, E>, PriorityT<T, I, E>, PrivateT<T, I, E>,
ProcBindT<T, I, E>, SafelenT<T, I, E>, SeverityT<T, I, E>, SharedT<T, I, E>,
- SimdlenT<T, I, E>, SizesT<T, I, E>, ThreadLimitT<T, I, E>,
- UniformT<T, I, E>, UpdateT<T, I, E>, UseDeviceAddrT<T, I, E>,
- UseDevicePtrT<T, I, E>, UsesAllocatorsT<T, I, E>>;
+ SimdlenT<T, I, E>, SizesT<T, I, E>, PermutationT<T, I, E>,
+ ThreadLimitT<T, I, E>, UniformT<T, I, E>, UpdateT<T, I, E>,
+ UseDeviceAddrT<T, I, E>, UseDevicePtrT<T, I, E>, UsesAllocatorsT<T, I, E>>;
template <typename T, typename I, typename E>
using UnionOfAllClausesT = typename type::Union< //
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td
index 3395f82ce1ba2..b1b58e7e99921 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMP.td
+++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td
@@ -72,6 +72,11 @@ def OMPC_Sizes: Clause<"sizes"> {
let flangClass = "ScalarIntExpr";
let isValueList = true;
}
+def OMPC_Permutation: Clause<"permutation"> {
+ let clangClass = "OMPPermutationClause";
+ let flangClass = "ScalarIntExpr";
+ let isValueList = true;
+ }
def OMPC_Full: Clause<"full"> {
let clangClass = "OMPFullClause";
}
@@ -541,6 +546,9 @@ def OMP_Reverse : Directive<"reverse"> {
let association = AS_Loop;
}
def OMP_Interchange : Directive<"interchange"> {
+ let allowedOnceClauses = [
+ VersionedClause<OMPC_Permutation, 60>,
+ ];
let association = AS_Loop;
}
def OMP_For : Directive<"for"> {
More information about the llvm-branch-commits
mailing list