[llvm-branch-commits] [llvm] 2a4a0bf - Update llvm/test/Transforms/InstCombine/bit_ceil.ll

Tom Stellard via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Thu May 16 11:43:34 PDT 2024


Author: Tom Stellard
Date: 2024-05-16T11:42:50-07:00
New Revision: 2a4a0bf1db8b828f104123de52d9f9cace020ed0

URL: https://github.com/llvm/llvm-project/commit/2a4a0bf1db8b828f104123de52d9f9cace020ed0
DIFF: https://github.com/llvm/llvm-project/commit/2a4a0bf1db8b828f104123de52d9f9cace020ed0.diff

LOG: Update llvm/test/Transforms/InstCombine/bit_ceil.ll

Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/bit_ceil.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll b/llvm/test/Transforms/InstCombine/bit_ceil.ll
index 63a5ae012eeb6..2c459a8c9d6db 100644
--- a/llvm/test/Transforms/InstCombine/bit_ceil.ll
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -287,7 +287,7 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
 define i32 @pr91691(i32 %0) {
 ; CHECK-LABEL: @pr91691(
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false), !range [[RNG0]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 31
 ; CHECK-NEXT:    [[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
@@ -305,7 +305,7 @@ define i32 @pr91691(i32 %0) {
 define i32 @pr91691_keep_nsw(i32 %0) {
 ; CHECK-LABEL: @pr91691_keep_nsw(
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1 false), !range [[RNG0]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 31
 ; CHECK-NEXT:    [[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]


        


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