[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)

[via llvm-branch-commits]

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/92129

Backport d422e90fcbdddd68749918ddd86c94188807efce

Requested by: @DianQK

>From 273eaada783556afddbcbdbbf1b3399d73de5343 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Tue, 14 May 2024 15:54:05 +0200
Subject: [PATCH] [GlobalIsel][AArch64] fix out of range access in
 regbankselect (#92072)

Fixes https://github.com/llvm/llvm-project/issues/92062

(cherry picked from commit d422e90fcbdddd68749918ddd86c94188807efce)
---
 .../AArch64/GISel/AArch64RegisterBankInfo.cpp |  5 ++++-
 llvm/test/CodeGen/AArch64/pr92062.ll          | 21 +++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/pr92062.ll

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const MachineInstr &MI) const {
     EltTy = GV->getValueType();
     // Look at the first element of the struct to determine the type we are
     // loading
-    while (StructType *StructEltTy = dyn_cast<StructType>(EltTy))
+    while (StructType *StructEltTy = dyn_cast<StructType>(EltTy)) {
+      if (StructEltTy->getNumElements() == 0)
+        break;
       EltTy = StructEltTy->getTypeAtIndex(0U);
+    }
     // Look at the first element of the array to determine its type
     if (isa<ArrayType>(EltTy))
       EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0000000000000..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+ at p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0: // %bb
+; CHECK-NEXT:    adrp x8, :got:p
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:    ldr x8, [x8]
+; CHECK-NEXT:    mov x9, xzr
+; CHECK-NEXT:    str x8, [x9]
+; CHECK-NEXT:    ret
+bb:
+  %i1 = load ptr, ptr @p, align 8
+  store ptr %i1, ptr null, align 8
+  ret void
+}