[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

[Wang Pengcheng via llvm-branch-commits]

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@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
+class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
+    : RegisterClass<"RISCV", regTypes, align, regList> {
+  bit IsVRegClass = 0;
+  int VLMul = 1;
+  int NF = 1;
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wangpc-pp wrote:

VLMul can't be 0 because `!logtwo(VLMul=0)` is illegal.
We use `bits<3>` to store `NF-1` (which is in range `[1, 7]`). NF is in range `[2, 8]`, but we will need 4 bits if we store its raw value. The default NF being 1 (NF-1==0) is a compromise, which is OK I think.
These fields are legal iff `IsVegClass` is true. 

https://github.com/llvm/llvm-project/pull/84894