[llvm-branch-commits] [llvm] release/18.x: [ARM] Update IsRestored for LR based on all returns (#82745) (PR #83129)
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Sat Mar 23 15:35:01 PDT 2024
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/83129
>From 6f8016fda7d56013a26d6f9bf2bd157aff4b13fa Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Fri, 23 Feb 2024 09:31:25 +0000
Subject: [PATCH 1/2] Pre-commit test showing bug #80287
This test shows the bug where LR is used as a general-purpose register
on a code path where it is not spilled to the stack.
(cherry picked from commit 8779cf68e80dcc0b15e8034f39e6ce18b08352b6)
---
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
diff --git a/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
new file mode 100644
index 00000000000000..883a812139ded1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple thumbv7a-none-eabi < %s | FileCheck %s
+
+ at val0 = global i32 0, align 4
+ at val1 = global i32 0, align 4
+ at val2 = global i32 0, align 4
+
+define i32 @foo(ptr %ctx) {
+; CHECK-LABEL: foo:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: cbz r0, .LBB0_2
+; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT: movw r2, :lower16:val0
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: movw r12, :lower16:val2
+; CHECK-NEXT: movw r3, :lower16:val1
+; CHECK-NEXT: movt r2, :upper16:val0
+; CHECK-NEXT: add.w lr, r1, #4
+; CHECK-NEXT: movt r12, :upper16:val2
+; CHECK-NEXT: movt r3, :upper16:val1
+; CHECK-NEXT: stm.w lr, {r2, r3, r12}
+; CHECK-NEXT: str r0, [r1, #16]
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .LBB0_2: @ %if.then
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: bl bar
+; CHECK-NEXT: mov.w r0, #-1
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %tobool.not = icmp eq ptr %ctx, null
+ br i1 %tobool.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() #2
+ br label %return
+
+if.end: ; preds = %entry
+ %cmd_a = getelementptr inbounds i8, ptr %ctx, i32 4
+ store ptr @val0, ptr %cmd_a, align 4
+ %cmd_b = getelementptr inbounds i8, ptr %ctx, i32 8
+ store ptr @val1, ptr %cmd_b, align 4
+ %cmd_c = getelementptr inbounds i8, ptr %ctx, i32 12
+ store ptr @val2, ptr %cmd_c, align 4
+ %cmd_d = getelementptr inbounds i8, ptr %ctx, i32 16
+ store ptr null, ptr %cmd_d, align 4
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %retval.0 = phi i32 [ 0, %if.end ], [ -1, %if.then ]
+ ret i32 %retval.0
+}
+
+declare void @bar()
>From 0e16af8e4cf3a66ad5d078d52744ae2776f9c4b2 Mon Sep 17 00:00:00 2001
From: ostannard <oliver.stannard at arm.com>
Date: Mon, 26 Feb 2024 12:23:25 +0000
Subject: [PATCH 2/2] [ARM] Update IsRestored for LR based on all returns
(#82745)
PR #75527 fixed ARMFrameLowering to set the IsRestored flag for LR based
on all of the return instructions in the function, not just one.
However, there is also code in ARMLoadStoreOptimizer which changes
return instructions, but it set IsRestored based on the one instruction
it changed, not the whole function.
The fix is to factor out the code added in #75527, and also call it from
ARMLoadStoreOptimizer if it made a change to return instructions.
Fixes #80287.
(cherry picked from commit 749384c08e042739342c88b521c8ba5dac1b9276)
---
llvm/lib/Target/ARM/ARMFrameLowering.cpp | 11 +++++----
llvm/lib/Target/ARM/ARMFrameLowering.h | 4 ++++
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 23 ++++++++-----------
llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll | 11 +++++----
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index eeb7f64aa5810e..9b54dd4e4e618d 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -2781,10 +2781,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
}
-void ARMFrameLowering::processFunctionBeforeFrameFinalized(
- MachineFunction &MF, RegScavenger *RS) const {
- TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
-
+void ARMFrameLowering::updateLRRestored(MachineFunction &MF) {
MachineFrameInfo &MFI = MF.getFrameInfo();
if (!MFI.isCalleeSavedInfoValid())
return;
@@ -2808,6 +2805,12 @@ void ARMFrameLowering::processFunctionBeforeFrameFinalized(
}
}
+void ARMFrameLowering::processFunctionBeforeFrameFinalized(
+ MachineFunction &MF, RegScavenger *RS) const {
+ TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);
+ updateLRRestored(MF);
+}
+
void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,
BitVector &SavedRegs) const {
TargetFrameLowering::getCalleeSaves(MF, SavedRegs);
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.h b/llvm/lib/Target/ARM/ARMFrameLowering.h
index 8d2b8beb9a58fb..3c7358d8cd53e2 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.h
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.h
@@ -59,6 +59,10 @@ class ARMFrameLowering : public TargetFrameLowering {
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS) const override;
+ /// Update the IsRestored flag on LR if it is spilled, based on the return
+ /// instructions.
+ static void updateLRRestored(MachineFunction &MF);
+
void processFunctionBeforeFrameFinalized(
MachineFunction &MF, RegScavenger *RS = nullptr) const override;
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index ed9d30c3c3ab90..6121055eb02176 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2062,17 +2062,6 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
MO.setReg(ARM::PC);
PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
MBB.erase(MBBI);
- // We now restore LR into PC so it is not live-out of the return block
- // anymore: Clear the CSI Restored bit.
- MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
- // CSI should be fixed after PrologEpilog Insertion
- assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
- for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
- if (Info.getReg() == ARM::LR) {
- Info.setRestored(false);
- break;
- }
- }
return true;
}
}
@@ -2120,14 +2109,22 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
isThumb2 = AFI->isThumb2Function();
isThumb1 = AFI->isThumbFunction() && !isThumb2;
- bool Modified = false;
+ bool Modified = false, ModifiedLDMReturn = false;
for (MachineBasicBlock &MBB : Fn) {
Modified |= LoadStoreMultipleOpti(MBB);
if (STI->hasV5TOps() && !AFI->shouldSignReturnAddress())
- Modified |= MergeReturnIntoLDM(MBB);
+ ModifiedLDMReturn |= MergeReturnIntoLDM(MBB);
if (isThumb1)
Modified |= CombineMovBx(MBB);
}
+ Modified |= ModifiedLDMReturn;
+
+ // If we merged a BX instruction into an LDM, we need to re-calculate whether
+ // LR is restored. This check needs to consider the whole function, not just
+ // the instruction(s) we changed, because there may be other BX returns which
+ // still need LR to be restored.
+ if (ModifiedLDMReturn)
+ ARMFrameLowering::updateLRRestored(Fn);
Allocator.DestroyAll();
return Modified;
diff --git a/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
index 883a812139ded1..9494880f990258 100644
--- a/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
+++ b/llvm/test/CodeGen/ARM/ldst-opt-lr-restored.ll
@@ -10,16 +10,17 @@ define i32 @foo(ptr %ctx) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cbz r0, .LBB0_2
; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT: movw r12, :lower16:val2
+; CHECK-NEXT: movw r3, :lower16:val1
; CHECK-NEXT: movw r2, :lower16:val0
; CHECK-NEXT: mov r1, r0
; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: movw r12, :lower16:val2
-; CHECK-NEXT: movw r3, :lower16:val1
-; CHECK-NEXT: movt r2, :upper16:val0
-; CHECK-NEXT: add.w lr, r1, #4
; CHECK-NEXT: movt r12, :upper16:val2
; CHECK-NEXT: movt r3, :upper16:val1
-; CHECK-NEXT: stm.w lr, {r2, r3, r12}
+; CHECK-NEXT: movt r2, :upper16:val0
+; CHECK-NEXT: str r2, [r1, #4]
+; CHECK-NEXT: str r3, [r1, #8]
+; CHECK-NEXT: str.w r12, [r1, #12]
; CHECK-NEXT: str r0, [r1, #16]
; CHECK-NEXT: bx lr
; CHECK-NEXT: .LBB0_2: @ %if.then
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