[llvm-branch-commits] [mlir] [MLIR][LLVM][SROA] Support incorrectly typed memory accesses (PR #85813)

[Christian Ulmann via llvm-branch-commits]

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@@ -384,16 +468,17 @@ bool LLVM::GEPOp::canRewire(const DestructurableMemorySlot &slot,
   // dynamic indices can never be properly rewired.
   if (!getDynamicIndices().empty())
     return false;
+  //// TODO: This is not necessary, I think.
+  // if (slot.elemType != getElemType())
+  //   return false;
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Dinistro wrote:

Whups, this is indeed a rebase/stash artefact.
I have some changes in the pipeline that will cover this case. 

https://github.com/llvm/llvm-project/pull/85813