[llvm-branch-commits] [llvm] [AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (PR #96162)

[Matt Arsenault via llvm-branch-commits]

arsenm wrote:

I'm still not sure why we have so much in this pass. The load and store vectorization should have happened in the IR. This pass originally was for the multi offset DS instructions 

https://github.com/llvm/llvm-project/pull/96162