[llvm-branch-commits] [llvm] AMDGPU: Fix buffer load/store of pointers (PR #95379)

[Krzysztof Drewniak via llvm-branch-commits]

krzysz00 wrote:

Yeah, makes sense.

... what prevents a match-bitwidth operator from existing?

Context from where I'm standing is that you should be able to `raw.buffer.load/store` any (non-aggregate, let's say, since that could be better handled in `addrspace(7)` handling) type you could `load` or `store`.

That is, `raw.ptr.buffer.load.i15` should work (as an i16 load that truncates) as should `raw.ptr.buffer.store.v8f32` (or `raw.ptr.buffer.store.i256`). Sure, the latter are two instructions long, but regular loads can regularize to multiple instructions just fine. 

My thoughts on how to implement that second behavior were to split the type into legal chunks and add in the offsets, and then merge/bitcast the values back.

https://github.com/llvm/llvm-project/pull/95379