[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/94313

>From 6e3d6329300e27a23481df3e6e01b9763a34d9d2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 6 Jun 2024 15:05:20 +0800
Subject: [PATCH 1/2] Address comments

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp   | 17 +++++++----------
 llvm/test/MC/RISCV/rvv/vsetvl.s                 |  6 +++---
 2 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4091f9d5e9f8a..49f21e46f34ea 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2160,10 +2160,9 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State,
       unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
       unsigned MinLMUL = ELEN / 8;
       if (Lmul > MinLMUL)
-        Warning(
-            Tok.getLoc(),
-            Twine("The use of vtype encodings with LMUL < SEWMIN/ELEN == mf") +
-                Twine(MinLMUL) + Twine(" is reserved"));
+        Warning(Tok.getLoc(),
+                "use of vtype encodings with LMUL < SEWMIN/ELEN == mf" +
+                    Twine(MinLMUL) + " is reserved");
     }
 
     State = VTypeState_TailPolicy;
@@ -2228,12 +2227,10 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
       unsigned MaxSEW = ELEN / Lmul;
       // If MaxSEW < 8, we should have printed warning about reserved LMUL.
       if (MaxSEW >= 8 && Sew > MaxSEW)
-        Warning(
-            SEWLoc,
-            Twine("The use of vtype encodings with SEW > ") + Twine(MaxSEW) +
-                Twine(" and LMUL == ") + Twine(Fractional ? "mf" : "m") +
-                Twine(Lmul) +
-                Twine(" may not be compatible with all RVV implementations"));
+        Warning(SEWLoc,
+                "use of vtype encodings with SEW > " + Twine(MaxSEW) +
+                    " and LMUL == " + (Fractional ? "mf" : "m") + Twine(Lmul) +
+                    " may not be compatible with all RVV implementations");
     }
 
     unsigned VTypeI =
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
index 207daf392bd50..2741def0eeff2 100644
--- a/llvm/test/MC/RISCV/rvv/vsetvl.s
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -73,21 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
 
 vsetvli a2, a0, e32, mf2, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
-# CHECK-ZVE32X: :[[#@LINE-2]]:17: warning: The use of vtype encodings with SEW > 16 and LMUL == mf2 may not be compatible with all RVV implementations{{$}}
+# CHECK-ZVE32X: :[[#@LINE-2]]:17: warning: use of vtype encodings with SEW > 16 and LMUL == mf2 may not be compatible with all RVV implementations{{$}}
 # CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
 # CHECK-UNKNOWN: 0d757657 <unknown>
 
 vsetvli a2, a0, e32, mf4, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
-# CHECK-ZVE32X: :[[#@LINE-2]]:17: warning: The use of vtype encodings with SEW > 8 and LMUL == mf4 may not be compatible with all RVV implementations{{$}}
+# CHECK-ZVE32X: :[[#@LINE-2]]:17: warning: use of vtype encodings with SEW > 8 and LMUL == mf4 may not be compatible with all RVV implementations{{$}}
 # CHECK-ENCODING: [0x57,0x76,0x65,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
 # CHECK-UNKNOWN: 0d657657 <unknown>
 
 vsetvli a2, a0, e32, mf8, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma
-# CHECK-ZVE32X: :[[#@LINE-2]]:22: warning: The use of vtype encodings with LMUL < SEWMIN/ELEN == mf4 is reserved{{$}}
+# CHECK-ZVE32X: :[[#@LINE-2]]:22: warning: use of vtype encodings with LMUL < SEWMIN/ELEN == mf4 is reserved{{$}}
 # CHECK-ENCODING: [0x57,0x76,0x55,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
 # CHECK-UNKNOWN: 0d557657 <unknown>

>From 6b44742cfcc24a07408bbe20070f57ebaa4e9066 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 7 Jun 2024 11:27:13 +0800
Subject: [PATCH 2/2] Remove Fractional

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 49f21e46f34ea..ca11d155ec7c6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2229,7 +2229,7 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
       if (MaxSEW >= 8 && Sew > MaxSEW)
         Warning(SEWLoc,
                 "use of vtype encodings with SEW > " + Twine(MaxSEW) +
-                    " and LMUL == " + (Fractional ? "mf" : "m") + Twine(Lmul) +
+                    " and LMUL == mf" + Twine(Lmul) +
                     " may not be compatible with all RVV implementations");
     }