[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/82322

>From f8415de83823cd5b244fcb288b29d4afc7ea10db Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Tue, 20 Feb 2024 18:20:03 +0800
Subject: [PATCH 1/2] Fix typo and address comments

Created using spr 1.3.4
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 32d47a669020f1..1814928c5ca159 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -625,7 +625,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.is64Bit())
     setOperationAction(ISD::Constant, MVT::i64, Custom);
 
-  // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
+  // TODO: On M-mode only targets, the cycle[h]/time[h] CSR may not be present.
   // Unfortunately this can't be determined just from the ISA naming string.
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
@@ -11739,7 +11739,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
           RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding, DL, XLenVT);
       HiCounter = DAG.getConstant(
           RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding, DL, XLenVT);
-    } else if (N->getOpcode() == ISD::READSTEADYCOUNTER) {
+    } else {
       LoCounter = DAG.getConstant(
           RISCVSysReg::lookupSysRegByName("TIME")->Encoding, DL, XLenVT);
       HiCounter = DAG.getConstant(
@@ -16929,9 +16929,9 @@ static MachineBasicBlock *emitReadCounterWidePseudo(MachineInstr &MI,
   // For example:
   // ```
   // read:
-  //   csrrs x3, counter # load high word of counter
-  //   csrrs x2, counterh # load low word of counter
-  //   csrrs x4, counter # load high word of counter
+  //   csrrs x3, counterh # load high word of counter
+  //   csrrs x2, counter # load low word of counter
+  //   csrrs x4, counterh # load high word of counter
   //   bne x3, x4, read # check if high word reads match, otherwise try again
   // ```
 

>From 95acdc7abbc5b85e6370b83a9efe961ccfb54e27 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 21 Feb 2024 13:03:08 +0800
Subject: [PATCH 2/2] Remove duplicated comments

Created using spr 1.3.4
---
 llvm/lib/Target/RISCV/RISCVISelLowering.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 879af0ecdf8bc0..83b1c68eea61ac 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -126,9 +126,10 @@ enum NodeType : unsigned {
   // Floating point fmax and fmin matching the RISC-V instruction semantics.
   FMAX, FMIN,
 
-  // READ_COUNTER_WIDE - A read of the 64-bit counter CSR on a 32-bit target
-  // (returns (Lo, Hi)). It takes a chain operand.
+  // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
+  // It takes a chain operand.
   READ_COUNTER_WIDE,
+
   // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
   // XLenVT.
   BREV8,