[llvm-branch-commits] [clang] [llvm] release/18.x: [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744) (PR #81857)
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llvm-branch-commits at lists.llvm.org
Thu Feb 15 05:20:54 PST 2024
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/81857
Backport a52eea66795018550e95c4b060165a7250899298 fbba818a78f591d89f25768ba31783714d526532 dd1897c6cb028bda7d4d541d1bb33965eccf0a68 3369e341288b3d9bb59827f9a2911ebf3d36408d
Requested by: @ptomsich
>From 618c35f6a848e81e519ac388abe708220c163e31 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: Thu, 1 Feb 2024 19:23:55 +0300
Subject: [PATCH 1/4] [AArch64] Make +pauth enabled in Armv8.3-a by default
(#78027)
Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.
After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.
The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.
(cherry picked from commit a52eea66795018550e95c4b060165a7250899298)
---
clang/lib/Basic/Targets/AArch64.cpp | 1 -
clang/test/CodeGen/aarch64-targetattr.c | 10 ++--
.../Preprocessor/aarch64-target-features.c | 35 +++++++-----
.../llvm/TargetParser/AArch64TargetParser.h | 2 +-
.../TargetParser/TargetParserTest.cpp | 54 +++++++++++--------
5 files changed, 60 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 336b7a5e3d727d..72270167118390 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -258,7 +258,6 @@ void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
- Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
// Also include the Armv8.2 defines
getTargetDefinesARMV82A(Opts, Builder);
}
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 02da18264da0a3..1a3a84a73dbad1 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -97,19 +97,19 @@ void minusarch() {}
// CHECK: attributes #0 = { {{.*}} "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #1 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #2 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
-// CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
+// CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
// CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
// CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
// CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" }
// CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" }
-// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" }
+// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" }
+// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" }
// CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
// CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
// CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
-// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #17 = { {{.*}} "target-features"="-neon" }
// CHECK: attributes #18 = { {{.*}} "target-features"="-v9.3a" }
diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
index 9914775097e579..1e9aec3fdf2373 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -318,15 +318,15 @@
// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
+// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
-// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "apple-a13" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon"
+// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "apple-a13" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon"
// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+neon" "-target-feature" "+ssbs"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+neon" "-target-feature" "+ssbs"
// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon"
@@ -335,10 +335,10 @@
// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
// RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon"
+// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon"
// RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s
-// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
+// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon"
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
@@ -501,9 +501,10 @@
// CHECK-MEMTAG: __ARM_FEATURE_MEMORY_TAGGING 1
// ================== Check Pointer Authentication Extension (PAuth).
-// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
-// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
-// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-ON %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-OFF,CHECK-CPU-NOPAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a+nopauth -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-OFF,CHECK-CPU-NOPAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-OFF,CHECK-CPU-PAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-OFF,CHECK-CPU-PAUTH %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH %s
@@ -511,12 +512,18 @@
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-BKEY %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-ALL %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-BKEY-ALL %s
-// CHECK-PAUTH-OFF-NOT: __ARM_FEATURE_PAC_DEFAULT
-// CHECK-PAUTH: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAUTH-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
-// CHECK-PAUTH-ALL: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAUTH-BKEY-ALL: #define __ARM_FEATURE_PAC_DEFAULT 6
-// CHECK-PAUTH-ON: #define __ARM_FEATURE_PAUTH 1
+//
+// Note: PAUTH-OFF - pac-ret is disabled
+// CPU-NOPAUTH - FEAT_PAUTH support is disabled (but pac-ret can still use HINT-encoded instructions)
+//
+// CHECK-CPU-NOPAUTH-NOT: __ARM_FEATURE_PAUTH
+// CHECK-PAUTH-OFF-NOT: __ARM_FEATURE_PAC_DEFAULT
+// CHECK-PAUTH: #define __ARM_FEATURE_PAC_DEFAULT 1
+// CHECK-PAUTH-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
+// CHECK-PAUTH-ALL: #define __ARM_FEATURE_PAC_DEFAULT 5
+// CHECK-PAUTH-BKEY-ALL: #define __ARM_FEATURE_PAC_DEFAULT 6
+// CHECK-CPU-PAUTH: #define __ARM_FEATURE_PAUTH 1
+// CHECK-CPU-NOPAUTH-NOT: __ARM_FEATURE_PAUTH
// ================== Check Branch Target Identification (BTI).
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 6d82748d8004be..703c95cf9785fa 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -478,7 +478,7 @@ inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile, "armv8.1-a
inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_RAS}))};
inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_RCPC, AArch64::AEK_JSCVT, AArch64::AEK_FCMA}))};
+ AArch64::ExtensionBitset({AArch64::AEK_FCMA, AArch64::AEK_JSCVT, AArch64::AEK_PAUTH, AArch64::AEK_RCPC}))};
inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_DOTPROD}))};
inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 2fde5b4e642c5f..cbd8fe18cd181c 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -133,8 +133,8 @@ template <ARM::ISAKind ISAKind> struct AssertSameExtensionFlags {
return testing::AssertionFailure() << llvm::formatv(
"CPU: {4}\n"
- "Expected extension flags: {0} ({1:x})\n"
- " Got extension flags: {2} ({3:x})\n",
+ "Expected extension flags: {0} ({1})\n"
+ " Got extension flags: {2} ({3})\n",
FormatExtensionFlags(ExpectedFlags),
SerializeExtensionFlags(ExpectedFlags),
FormatExtensionFlags(GotFlags),
@@ -1260,7 +1260,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16,
AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.4-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-v2", "armv9-a", "neon-fp-armv8",
@@ -1275,7 +1276,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SVE2, AArch64::AEK_PROFILE,
AArch64::AEK_FP16FML, AArch64::AEK_I8MM,
AArch64::AEK_SVE2BITPERM, AArch64::AEK_RAND,
- AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"9-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
@@ -1284,7 +1286,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_SIMD,
AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS,
AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB,
- AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8-R"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
@@ -1389,7 +1391,8 @@ INSTANTIATE_TEST_SUITE_P(
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a13", "armv8.4-a", "crypto-neon-fp-armv8",
@@ -1399,7 +1402,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA})),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.4-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a14", "armv8.5-a", "crypto-neon-fp-armv8",
@@ -1409,7 +1412,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA})),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.5-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a15", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1419,7 +1422,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a16", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1429,7 +1433,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-a17", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1439,7 +1444,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-m1", "armv8.5-a", "crypto-neon-fp-armv8",
@@ -1449,7 +1455,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA})),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.5-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-m2", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1459,7 +1465,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-m3", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1469,7 +1476,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM,
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-s4", "armv8.3-a", "crypto-neon-fp-armv8",
@@ -1477,7 +1485,8 @@ INSTANTIATE_TEST_SUITE_P(
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"apple-s5", "armv8.3-a", "crypto-neon-fp-armv8",
@@ -1485,7 +1494,8 @@ INSTANTIATE_TEST_SUITE_P(
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE,
AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC,
- AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
@@ -1550,7 +1560,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SB, AArch64::AEK_SVE2,
AArch64::AEK_SVE2BITPERM, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA})),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.5-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1561,7 +1571,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2,
AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS,
AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA})),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"ampere1a", "armv8.6-a", "crypto-neon-fp-armv8",
@@ -1572,7 +1582,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
- AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.6-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
@@ -1584,7 +1595,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16,
AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
- AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH})),
"8.4-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
@@ -1599,7 +1611,7 @@ INSTANTIATE_TEST_SUITE_P(
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP,
AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_RCPC,
- AArch64::AEK_JSCVT, AArch64::AEK_FCMA})),
+ AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH})),
"8.3-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"thunderx", "armv8-a", "crypto-neon-fp-armv8",
>From f75ec423c5b025b7588ecfd68635ed1f6a5b0113 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: Fri, 9 Feb 2024 15:22:09 -0800
Subject: [PATCH 2/4] [AArch64] Add the Ampere1B core (#81297)
The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.
Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.
(cherry picked from commit fbba818a78f591d89f25768ba31783714d526532)
---
clang/test/Driver/aarch64-cssc.c | 1 +
clang/test/Misc/target-invalid-cpu-note.c | 4 +--
.../llvm/TargetParser/AArch64TargetParser.h | 6 +++++
llvm/lib/Target/AArch64/AArch64.td | 26 +++++++++++++++++++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 +
llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 +
llvm/lib/TargetParser/Host.cpp | 1 +
llvm/test/CodeGen/AArch64/cpus.ll | 1 +
llvm/test/CodeGen/AArch64/neon-dot-product.ll | 1 +
llvm/test/CodeGen/AArch64/remat.ll | 1 +
llvm/test/MC/AArch64/armv8.2a-dotprod.s | 3 +++
.../MC/Disassembler/AArch64/armv8.3a-rcpc.txt | 1 +
llvm/unittests/TargetParser/Host.cpp | 3 +++
.../TargetParser/TargetParserTest.cpp | 14 +++++++++-
14 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/aarch64-cssc.c b/clang/test/Driver/aarch64-cssc.c
index a3e18663279bbd..5df0ea79d7c850 100644
--- a/clang/test/Driver/aarch64-cssc.c
+++ b/clang/test/Driver/aarch64-cssc.c
@@ -9,6 +9,7 @@
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a %s 2>&1 | FileCheck %s
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b %s 2>&1 | FileCheck %s
// CHECK: "target-features"="{{.*}},+cssc
// NO_CSSC: "target-features"="{{.*}},-cssc
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 2f10bfb1fd82fe..39ed02f50950dd 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
+// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 703c95cf9785fa..c10f92e2871747 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -805,6 +805,12 @@ inline constexpr CpuInfo CpuInfos[] = {
{AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES,
AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))},
+ {"ampere1b", ARMV8_7A,
+ (AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND,
+ AArch64::AEK_SM4, AArch64::AEK_SHA3,
+ AArch64::AEK_SHA2, AArch64::AEK_AES,
+ AArch64::AEK_MTE, AArch64::AEK_SB,
+ AArch64::AEK_SSBS, AArch64::AEK_CSSC}))},
};
// An alias for a CPU.
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 36700f73df4b20..3a2a01388cabcb 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1376,6 +1376,24 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
FeatureLdpAlignedOnly,
FeatureStpAlignedOnly]>;
+def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B",
+ "Ampere Computing Ampere-1B processors", [
+ FeaturePostRAScheduler,
+ FeatureFuseAES,
+ FeatureFuseAdrpAdd,
+ FeatureAddrLSLFast,
+ FeatureALULSLFast,
+ FeatureAggressiveFMA,
+ FeatureArithmeticBccFusion,
+ FeatureCmpBccFusion,
+ FeatureFuseAddress,
+ FeatureFuseLiterals,
+ FeatureStorePairSuppress,
+ FeatureEnableSelectOptimize,
+ FeaturePredictableSelectIsExpensive,
+ FeatureLdpAlignedOnly,
+ FeatureStpAlignedOnly]>;
+
def ProcessorFeatures {
list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
@@ -1529,6 +1547,11 @@ def ProcessorFeatures {
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES];
+ list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
+ FeatureMTE, FeatureSSBS, FeatureRandGen,
+ FeatureSB, FeatureSM4, FeatureSHA2,
+ FeatureSHA3, FeatureAES, FeatureCSSC,
+ FeatureWFxT];
// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
@@ -1696,6 +1719,9 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
[TuneAmpere1A]>;
+def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
+ [TuneAmpere1B]>;
+
//===----------------------------------------------------------------------===//
// Assembly parser
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index e3a0606331db1c..dd4c0e2eb64249 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -296,6 +296,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
break;
case Ampere1:
case Ampere1A:
+ case Ampere1B:
CacheLineSize = 64;
PrefFunctionAlignment = Align(64);
PrefLoopAlignment = Align(64);
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 16864102df59b0..f8dcbe97b6321a 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -42,6 +42,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
A64FX,
Ampere1,
Ampere1A,
+ Ampere1B,
AppleA7,
AppleA10,
AppleA11,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index f1197c29655380..4466d50458e198 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -321,6 +321,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
return StringSwitch<const char *>(Part)
.Case("0xac3", "ampere1")
.Case("0xac4", "ampere1a")
+ .Case("0xac5", "ampere1b")
.Default("generic");
}
diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll
index b24866064efaea..7b45d0f30bcdd4 100644
--- a/llvm/test/CodeGen/AArch64/cpus.ll
+++ b/llvm/test/CodeGen/AArch64/cpus.ll
@@ -37,6 +37,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1b 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
; CHECK-NOT: {{.*}} is not a recognized processor for this target
diff --git a/llvm/test/CodeGen/AArch64/neon-dot-product.ll b/llvm/test/CodeGen/AArch64/neon-dot-product.ll
index 23d1e43a5cab1b..cf09a46000dab9 100644
--- a/llvm/test/CodeGen/AArch64/neon-dot-product.ll
+++ b/llvm/test/CodeGen/AArch64/neon-dot-product.ll
@@ -7,6 +7,7 @@
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1 < %s | FileCheck %s
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1a < %s | FileCheck %s
+; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1b < %s | FileCheck %s
declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/AArch64/remat.ll b/llvm/test/CodeGen/AArch64/remat.ll
index 483c4d71ee21fb..704c87feb6a9b8 100644
--- a/llvm/test/CodeGen/AArch64/remat.ll
+++ b/llvm/test/CodeGen/AArch64/remat.ll
@@ -26,6 +26,7 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1a -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1b -o - %s | FileCheck %s
%X = type { i64, i64, i64 }
declare void @f(ptr)
diff --git a/llvm/test/MC/AArch64/armv8.2a-dotprod.s b/llvm/test/MC/AArch64/armv8.2a-dotprod.s
index 9c4a6cad7e07a6..26afbe149dd00b 100644
--- a/llvm/test/MC/AArch64/armv8.2a-dotprod.s
+++ b/llvm/test/MC/AArch64/armv8.2a-dotprod.s
@@ -15,6 +15,7 @@
// RUN: llvm-mc -triple aarch64 -mattr=+v8r -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=ampere1b -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
@@ -42,6 +43,8 @@
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1a -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
+// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1b -mattr=-dotprod -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
udot v0.2s, v1.8b, v2.8b
sdot v0.2s, v1.8b, v2.8b
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
index 907d0c319efd57..259cb9dbc52a46 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
@@ -14,6 +14,7 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1b --disassemble < %s | FileCheck %s
# CHECK: ldaprb w0, [x0]
# CHECK: ldaprh w0, [x0]
diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp
index 5f151616d7ca6a..6aa1d7a087ebf0 100644
--- a/llvm/unittests/TargetParser/Host.cpp
+++ b/llvm/unittests/TargetParser/Host.cpp
@@ -122,6 +122,9 @@ TEST(getLinuxHostCPUName, AArch64) {
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
"CPU part : 0xac4"),
"ampere1a");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
+ "CPU part : 0xac5"),
+ "ampere1b");
// MSM8992/4 weirdness
StringRef MSM8992ProcCpuInfo = R"(
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index cbd8fe18cd181c..131741ff7fd07a 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1585,6 +1585,18 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH})),
"8.6-A"),
+ ARMCPUTestParams<AArch64::ExtensionBitset>(
+ "ampere1b", "armv8.7-a", "crypto-neon-fp-armv8",
+ (AArch64::ExtensionBitset(
+ {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE,
+ AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD,
+ AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
+ AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
+ AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
+ AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH, AArch64::AEK_CSSC})),
+ "8.7-A"),
ARMCPUTestParams<AArch64::ExtensionBitset>(
"neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
(AArch64::ExtensionBitset(
@@ -1663,7 +1675,7 @@ INSTANTIATE_TEST_SUITE_P(
"8.2-A")));
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 68;
+static constexpr unsigned NumAArch64CPUArchs = 69;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
>From 87adb9163d981225bab266c246d0c46ee152719a Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: Wed, 14 Feb 2024 06:23:14 -0800
Subject: [PATCH 3/4] [AArch64] Initial Ampere1B scheduling model (#81341)
The Ampere1B core is enabled with a new scheduling/pipeline model, as it
provides significant updates over the Ampere1 core; it reduces latencies
on many instructions, has some micro-ops reassigned between the XY and X
units, and provides modelling for the instructions added since Ampere1
and Ampere1A.
As this is the first model implementing the CSSC instructions, we update
the UnsupportedFeatures on all other models (that have CompleteModel
set).
Testcases are added under llvm-mca: these showed the FullFP16 feature
missing, so we are adding it in as part of this commit.
This *adds tests and additional fixes* compared to the reverted #81338.
(cherry picked from commit dd1897c6cb028bda7d4d541d1bb33965eccf0a68)
---
llvm/lib/Target/AArch64/AArch64.td | 5 +-
llvm/lib/Target/AArch64/AArch64SchedA53.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedA57.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 3 +-
.../Target/AArch64/AArch64SchedAmpere1B.td | 1149 +++++
.../lib/Target/AArch64/AArch64SchedCyclone.td | 2 +-
.../Target/AArch64/AArch64SchedExynosM3.td | 2 +-
.../Target/AArch64/AArch64SchedExynosM4.td | 2 +-
.../Target/AArch64/AArch64SchedExynosM5.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedFalkor.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedKryo.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN1.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 3 +-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 3 +-
llvm/lib/Target/AArch64/AArch64SchedTSV110.td | 2 +-
.../Target/AArch64/AArch64SchedThunderX.td | 2 +-
.../AArch64/AArch64SchedThunderX2T99.td | 2 +-
.../AArch64/AArch64SchedThunderX3T110.td | 2 +-
.../Ampere/Ampere1B/basic-instructions.s | 3724 +++++++++++++++++
.../Ampere/Ampere1B/cssc-instructions.s | 76 +
.../Ampere/Ampere1B/mte-instructions.s | 349 ++
.../Ampere/Ampere1B/neon-instructions.s | 3235 ++++++++++++++
.../Ampere/Ampere1B/shifted-register.s | 31 +
24 files changed, 8587 insertions(+), 19 deletions(-)
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 3a2a01388cabcb..feabd137c0cf1d 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -837,6 +837,7 @@ include "AArch64SchedA64FX.td"
include "AArch64SchedThunderX3T110.td"
include "AArch64SchedTSV110.td"
include "AArch64SchedAmpere1.td"
+include "AArch64SchedAmpere1B.td"
include "AArch64SchedNeoverseN1.td"
include "AArch64SchedNeoverseN2.td"
include "AArch64SchedNeoverseV1.td"
@@ -1551,7 +1552,7 @@ def ProcessorFeatures {
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES, FeatureCSSC,
- FeatureWFxT];
+ FeatureWFxT, FeatureFullFP16];
// ETE and TRBE are future architecture extensions. We temporarily enable them
// by default for users targeting generic AArch64. The extensions do not
@@ -1719,7 +1720,7 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
[TuneAmpere1A]>;
-def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
+def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B,
[TuneAmpere1B]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index 3e4168f5f445f5..c714bad92b7fbb 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -29,7 +29,7 @@ def CortexA53Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index 277ec772cf0f10..ebbc3b72b50609 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -34,7 +34,7 @@ def CortexA57Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 7edce4b61605d2..d6fe84a2c9c9b4 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -22,7 +22,8 @@ def A64FXModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
[HasMTE, HasMatMulInt8, HasBF16,
- HasPAuth, HasPAuthLR, HasCPA]);
+ HasPAuth, HasPAuthLR, HasCPA,
+ HasCSSC]);
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
new file mode 100644
index 00000000000000..9c4f000cf351b2
--- /dev/null
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
@@ -0,0 +1,1149 @@
+//=- AArch64SchedAmpere1B.td - Ampere-1B scheduling def -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for the Ampere Computing Ampere-1B to
+// support instruction scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+// The Ampere-1B core is an out-of-order micro-architecture. The front
+// end has branch prediction, with a 10-cycle recovery time from a
+// mispredicted branch. Instructions coming out of the front end are
+// decoded into internal micro-ops (uops).
+
+def Ampere1BModel : SchedMachineModel {
+ let IssueWidth = 12; // Maximum micro-ops dispatch rate.
+ let MicroOpBufferSize = 192; // micro-op re-order buffer size
+ let LoadLatency = 3; // Optimistic load latency
+ let MispredictPenalty = 10; // Branch mispredict penalty
+ let LoopMicroOpBufferSize = 32; // Instruction queue size
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ SMEUnsupported.F,
+ PAUnsupported.F);
+}
+
+let SchedModel = Ampere1BModel in {
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available on Ampere-1B.
+
+def Ampere1BUnitA : ProcResource<2>; // integer single-cycle, branch, and flags r/w
+def Ampere1BUnitB : ProcResource<2>; // integer single-cycle, and complex shifts
+def Ampere1BUnitBS : ProcResource<1>; // integer multi-cycle
+def Ampere1BUnitL : ProcResource<2>; // load
+def Ampere1BUnitS : ProcResource<2>; // store address calculation
+def Ampere1BUnitX : ProcResource<1>; // FP and vector operations, and flag write
+def Ampere1BUnitY : ProcResource<1>; // FP and vector operations, and crypto
+def Ampere1BUnitZ : ProcResource<1>; // FP store data and FP-to-integer moves
+
+def Ampere1BUnitAB : ProcResGroup<[Ampere1BUnitA, Ampere1BUnitB]>;
+def Ampere1BUnitXY : ProcResGroup<[Ampere1BUnitX, Ampere1BUnitY]>;
+
+//===----------------------------------------------------------------------===//
+// Define customized scheduler read/write types specific to the Ampere-1.
+
+def Ampere1BWrite_1cyc_1A : SchedWriteRes<[Ampere1BUnitA]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_2A : SchedWriteRes<[Ampere1BUnitA, Ampere1BUnitA]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_1cyc_1B : SchedWriteRes<[Ampere1BUnitB]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_1BS : SchedWriteRes<[Ampere1BUnitBS]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_1BS_1B : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitB]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_1cyc_1AB : SchedWriteRes<[Ampere1BUnitAB]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_1AB_1A : SchedWriteRes<[Ampere1BUnitAB, Ampere1BUnitA]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_1cyc_1L : SchedWriteRes<[Ampere1BUnitL]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_1S : SchedWriteRes<[Ampere1BUnitS]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_1cyc_2S : SchedWriteRes<[Ampere1BUnitS, Ampere1BUnitS]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_2cyc_1Y : SchedWriteRes<[Ampere1BUnitY]> {
+ let Latency = 2;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_2cyc_2AB : SchedWriteRes<[Ampere1BUnitAB, Ampere1BUnitAB]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_2cyc_1B_1AB : SchedWriteRes<[Ampere1BUnitB, Ampere1BUnitAB]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_2cyc_1B_1S : SchedWriteRes<[Ampere1BUnitB, Ampere1BUnitS]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_2cyc_1B_1S_1AB : SchedWriteRes<[Ampere1BUnitB,
+ Ampere1BUnitS,
+ Ampere1BUnitAB]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_2cyc_1S_2Z : SchedWriteRes<[Ampere1BUnitS,
+ Ampere1BUnitZ,
+ Ampere1BUnitZ]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_2cyc_1XY : SchedWriteRes<[Ampere1BUnitXY]> {
+ let Latency = 2;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_2cyc_1S_1Z : SchedWriteRes<[Ampere1BUnitS, Ampere1BUnitZ]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_3cyc_1BS : SchedWriteRes<[Ampere1BUnitBS]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_3cyc_1L : SchedWriteRes<[Ampere1BUnitL]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_3cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_3cyc_1XY : SchedWriteRes<[Ampere1BUnitXY]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_3cyc_1Z : SchedWriteRes<[Ampere1BUnitZ]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_3cyc_1S_1Z : SchedWriteRes<[Ampere1BUnitS,
+ Ampere1BUnitZ]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_3cyc_1S_2Z : SchedWriteRes<[Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_3cyc_2S_2Z : SchedWriteRes<[Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 3;
+ let NumMicroOps = 4;
+}
+
+def Ampere1BWrite_4cyc_1BS_1AB : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitAB]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_4cyc_1L : SchedWriteRes<[Ampere1BUnitL]> {
+ let Latency = 4;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_4cyc_2L : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_4cyc_1L_1B : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitB]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_4cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 4;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_4cyc_1XY : SchedWriteRes<[Ampere1BUnitXY]> {
+ let Latency = 4;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_4cyc_2XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_5cyc_1BS : SchedWriteRes<[Ampere1BUnitBS]> {
+ let Latency = 5;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_4cyc_1XY_1S_1Z : SchedWriteRes<[Ampere1BUnitXY,
+ Ampere1BUnitS,
+ Ampere1BUnitZ]> {
+ let Latency = 4;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_4cyc_3S_3Z : SchedWriteRes<[Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitS, Ampere1BUnitZ,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 4;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_5cyc_4S_4Z : SchedWriteRes<[Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 5;
+ let NumMicroOps = 8;
+}
+
+def Ampere1BWrite_5cyc_1L_1BS : SchedWriteRes<[Ampere1BUnitL,
+ Ampere1BUnitBS]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_5cyc_3L : SchedWriteRes<[Ampere1BUnitL,
+ Ampere1BUnitL,
+ Ampere1BUnitL]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_5cyc_4L : SchedWriteRes<[Ampere1BUnitL,
+ Ampere1BUnitL,
+ Ampere1BUnitL,
+ Ampere1BUnitL]> {
+ let Latency = 5;
+ let NumMicroOps = 4;
+}
+
+def Ampere1BWrite_5cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 5;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_5cyc_2XY_2S_2Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 5;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_6cyc_1BS_1A : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitA]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_6cyc_1BS_2A : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitA,
+ Ampere1BUnitA]> {
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_6cyc_1L_1XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitXY]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_6cyc_2L_2XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 6;
+ let NumMicroOps = 4;
+}
+
+def Ampere1BWrite_6cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_6cyc_2XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_6cyc_3XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY]> {
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_6cyc_2XY_2S_2Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 6;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_6cyc_3XY_3S_3Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitS, Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 6;
+ let NumMicroOps = 9;
+}
+
+def Ampere1BWrite_7cyc_1BS_1XY : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitXY]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_7cyc_1XY_1Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitZ]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_7cyc_1X_1Z : SchedWriteRes<[Ampere1BUnitX, Ampere1BUnitZ]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_7cyc_3L_3XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 7;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_7cyc_4L_4XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 7;
+ let NumMicroOps = 8;
+}
+
+def Ampere1BWrite_7cyc_4XY_4S_4Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 7;
+ let NumMicroOps = 12;
+}
+
+def Ampere1BWrite_8cyc_1BS_1L : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitL]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_8cyc_1BS_1XY : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_8cyc_2L_3XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 5;
+}
+
+def Ampere1BWrite_8cyc_3L_3XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_8cyc_4L_4XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 8;
+}
+
+def Ampere1BWrite_8cyc_2XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_8cyc_4XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 8;
+ let NumMicroOps = 4;
+}
+
+def Ampere1BWrite_9cyc_6XY_4S_4Z : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitS, Ampere1BUnitS,
+ Ampere1BUnitZ, Ampere1BUnitZ,
+ Ampere1BUnitZ, Ampere1BUnitZ]> {
+ let Latency = 9;
+ let NumMicroOps = 14;
+}
+
+def Ampere1BWrite_9cyc_1A_1BS_1X : SchedWriteRes<[Ampere1BUnitA, Ampere1BUnitBS, Ampere1BUnitX]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_9cyc_1A_1BS_1XY : SchedWriteRes<[Ampere1BUnitA, Ampere1BUnitBS, Ampere1BUnitXY]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_9cyc_3L_3XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 9;
+ let NumMicroOps = 6;
+}
+
+def Ampere1BWrite_9cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 9;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_9cyc_3XY : SchedWriteRes<[Ampere1BUnitXY, Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_10cyc_4L_8XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 10;
+ let NumMicroOps = 12;
+}
+
+def Ampere1BWrite_11cyc_1BS_2XY : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 11;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_11cyc_4L_8XY : SchedWriteRes<[Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitL, Ampere1BUnitL,
+ Ampere1BUnitXY, Ampere1BUnitXY,
+ Ampere1BUnitXY, Ampere1BUnitXY]> {
+ let Latency = 11;
+ let NumMicroOps = 12;
+}
+
+def Ampere1BWrite_12cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 12;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_13cyc_1BS_1X : SchedWriteRes<[Ampere1BUnitBS, Ampere1BUnitX]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+
+def Ampere1BWrite_17cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 17;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_19cyc_2BS_1X : SchedWriteRes<[Ampere1BUnitBS,
+ Ampere1BUnitBS,
+ Ampere1BUnitX]> {
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+
+def Ampere1BWrite_19cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 19;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_21cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 21;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_33cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 33;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_39cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 39;
+ let NumMicroOps = 1;
+}
+
+def Ampere1BWrite_63cyc_1X : SchedWriteRes<[Ampere1BUnitX]> {
+ let Latency = 63;
+ let NumMicroOps = 1;
+}
+
+// For basic arithmetic, we have more flexibility for short shifts (LSL shift <= 4),
+// which are a single uop, and for extended registers, which have full flexibility
+// across Unit A or B for both uops.
+def Ampere1BWrite_Arith : SchedWriteVariant<[
+ SchedVar<RegExtendedPred, [Ampere1BWrite_2cyc_2AB]>,
+ SchedVar<IsCheapLSL, [Ampere1BWrite_1cyc_1AB]>,
+ SchedVar<NoSchedPred, [Ampere1BWrite_2cyc_1B_1AB]>]>;
+
+def Ampere1BWrite_ArithFlagsetting : SchedWriteVariant<[
+ SchedVar<RegExtendedPred, [Ampere1BWrite_2cyc_2AB]>,
+ SchedVar<IsCheapLSL, [Ampere1BWrite_1cyc_1AB]>,
+ SchedVar<NoSchedPred, [Ampere1BWrite_2cyc_1B_1AB]>]>;
+
+//===----------------------------------------------------------------------===//
+// Map the target-defined scheduler read/write resources and latencies for Ampere-1.
+// This provides a coarse model, which is then specialised below.
+
+def : WriteRes<WriteImm, [Ampere1BUnitAB]>; // MOVN, MOVZ
+def : WriteRes<WriteI, [Ampere1BUnitAB]>; // ALU
+def : WriteRes<WriteISReg, [Ampere1BUnitB, Ampere1BUnitAB]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+} // ALU of Shifted-Reg
+def : WriteRes<WriteIEReg, [Ampere1BUnitAB, Ampere1BUnitAB]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+} // ALU of Extended-Reg
+def : WriteRes<WriteExtr, [Ampere1BUnitB]>; // EXTR shifts a reg pair
+def : WriteRes<WriteIS, [Ampere1BUnitB]>; // Shift/Scale
+def : WriteRes<WriteID32, [Ampere1BUnitBS, Ampere1BUnitX]> {
+ let Latency = 13;
+} // 32-bit Divide
+def : WriteRes<WriteID64, [Ampere1BUnitBS, Ampere1BUnitX]> {
+ let Latency = 19;
+} // 64-bit Divide
+def : WriteRes<WriteIM32, [Ampere1BUnitBS]> {
+ let Latency = 3;
+} // 32-bit Multiply
+def : WriteRes<WriteIM64, [Ampere1BUnitBS, Ampere1BUnitAB]> {
+ let Latency = 3;
+} // 64-bit Multiply
+def : WriteRes<WriteBr, [Ampere1BUnitA]>;
+def : WriteRes<WriteBrReg, [Ampere1BUnitA, Ampere1BUnitA]>;
+def : WriteRes<WriteLD, [Ampere1BUnitL]> {
+ let Latency = 3;
+} // Load from base addr plus immediate offset
+def : WriteRes<WriteST, [Ampere1BUnitS]> {
+ let Latency = 1;
+} // Store to base addr plus immediate offset
+def : WriteRes<WriteSTP, [Ampere1BUnitS, Ampere1BUnitS]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+} // Store a register pair.
+def : WriteRes<WriteAdr, [Ampere1BUnitAB]>;
+def : WriteRes<WriteLDIdx, [Ampere1BUnitAB, Ampere1BUnitS]> {
+ let Latency = 3;
+ let NumMicroOps = 1;
+} // Load from a register index (maybe scaled).
+def : WriteRes<WriteSTIdx, [Ampere1BUnitS, Ampere1BUnitS]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+} // Store to a register index (maybe scaled).
+def : WriteRes<WriteF, [Ampere1BUnitXY]> {
+ let Latency = 2;
+} // General floating-point ops.
+def : WriteRes<WriteFCmp, [Ampere1BUnitX]> {
+ let Latency = 3;
+} // Floating-point compare.
+def : WriteRes<WriteFCvt, [Ampere1BUnitXY]> {
+ let Latency = 3;
+} // Float conversion.
+def : WriteRes<WriteFCopy, [Ampere1BUnitXY]> {
+} // Float-int register copy.
+def : WriteRes<WriteFImm, [Ampere1BUnitXY]> {
+ let Latency = 2;
+} // Float-int register copy.
+def : WriteRes<WriteFMul, [Ampere1BUnitXY]> {
+ let Latency = 4;
+} // Floating-point multiply.
+def : WriteRes<WriteFDiv, [Ampere1BUnitXY]> {
+ let Latency = 19;
+} // Floating-point division.
+def : WriteRes<WriteVd, [Ampere1BUnitXY]> {
+ let Latency = 3;
+} // 64bit Vector D ops.
+def : WriteRes<WriteVq, [Ampere1BUnitXY]> {
+ let Latency = 3;
+} // 128bit Vector Q ops.
+def : WriteRes<WriteVLD, [Ampere1BUnitL, Ampere1BUnitL]> {
+ let Latency = 4;
+} // Vector loads.
+def : WriteRes<WriteVST, [Ampere1BUnitS, Ampere1BUnitZ]> {
+ let Latency = 2;
+} // Vector stores.
+
+def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
+
+def : WriteRes<WriteSys, []> { let Latency = 1; }
+def : WriteRes<WriteBarrier, []> { let Latency = 1; }
+def : WriteRes<WriteHint, []> { let Latency = 1; }
+
+def : WriteRes<WriteLDHi, []> {
+ let Latency = 3;
+} // The second register of a load-pair: LDP,LDPSW,LDNP,LDXP,LDAXP
+
+// Forwarding logic.
+def : ReadAdvance<ReadI, 0>;
+def : ReadAdvance<ReadISReg, 0>;
+def : ReadAdvance<ReadIEReg, 0>;
+def : ReadAdvance<ReadIM, 0>;
+def : ReadAdvance<ReadIMA, 1, [WriteIM32, WriteIM64]>;
+def : ReadAdvance<ReadID, 0>;
+def : ReadAdvance<ReadExtrHi, 0>;
+def : ReadAdvance<ReadST, 0>;
+def : ReadAdvance<ReadAdrBase, 0>;
+def : ReadAdvance<ReadVLD, 0>;
+
+//===----------------------------------------------------------------------===//
+// Specialising the scheduling model further for Ampere-1B.
+
+def : InstRW<[Ampere1BWrite_1cyc_1AB], (instrs COPY)>;
+
+// Branch instructions
+def : InstRW<[Ampere1BWrite_1cyc_1A], (instrs Bcc, BL, RET)>;
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instrs CBZW, CBZX, CBNZW, CBNZX, TBZW, TBZX, TBNZW, TBNZX)>;
+def : InstRW<[Ampere1BWrite_1cyc_2A], (instrs BLR)>;
+
+// Common Short Sequence Compression (CSSC)
+def : InstRW<[Ampere1BWrite_1cyc_1AB], (instregex "^ABS[WX]")>;
+def : InstRW<[Ampere1BWrite_3cyc_1BS], (instregex "^CNT[WX]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instregex "^CTZ[WX]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1AB_1A], (instregex "^[SU](MAX|MIN)[WX]")>;
+
+// Cryptography instructions
+// -- AES encryption/decryption
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^AES[DE]")>;
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^AESI?MC")>;
+// -- Polynomial multiplication
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^PMUL", "^PMULL")>;
+// -- SHA-256 hash
+def : InstRW<[Ampere1BWrite_4cyc_1X], (instregex "^SHA256(H|H2)")>;
+// -- SHA-256 schedule update
+def : InstRW<[Ampere1BWrite_2cyc_1Y], (instregex "^SHA256SU[01]")>;
+// -- SHA-3 instructions
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^BCAX", "^EOR3", "^RAX1", "^XAR")>;
+// -- SHA-512 hash
+def : InstRW<[Ampere1BWrite_4cyc_1X], (instregex "^SHA512(H|H2)")>;
+// -- SHA-512 schedule update
+def : InstRW<[Ampere1BWrite_2cyc_1Y], (instregex "^SHA512SU[01]")>;
+// -- SHA1 choose/majority/parity
+def : InstRW<[Ampere1BWrite_4cyc_1X], (instregex "^SHA1[CMP]")>;
+// -- SHA1 hash/schedule update
+def : InstRW<[Ampere1BWrite_2cyc_1Y], (instregex "^SHA1SU[01]")>;
+def : InstRW<[Ampere1BWrite_2cyc_1Y], (instregex "^SHA1H")>;
+// -- SM3 hash
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SM3PARTW[12]$", "^SM3SS1$", "^SM3TT[12][AB]$")>;
+def : InstRW<[Ampere1BWrite_4cyc_1X], (instrs SM4E, SM4ENCKEY)>;
+
+// FP and vector load instructions
+// -- Load 1-element structure to one/all lanes
+// ---- all lanes
+def : InstRW<[Ampere1BWrite_6cyc_1L_1XY],
+ (instregex "^LD1Rv(8b|4h|2s|16b|8h|4s|2d)")>;
+// ---- one lane
+def : InstRW<[Ampere1BWrite_6cyc_1L_1XY],
+ (instregex "^LD1i(8|16|32|64)")>;
+// -- Load 1-element structure to one/all lanes, 1D size
+def : InstRW<[Ampere1BWrite_4cyc_1L],
+ (instregex "^LD1Rv1d")>;
+// -- Load 1-element structures to 1 register
+def : InstRW<[Ampere1BWrite_4cyc_1L],
+ (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Load 1-element structures to 2 registers
+def : InstRW<[Ampere1BWrite_4cyc_2L],
+ (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Load 1-element structures to 3 registers
+def : InstRW<[Ampere1BWrite_5cyc_3L],
+ (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Load 1-element structures to 4 registers
+def : InstRW<[Ampere1BWrite_5cyc_4L],
+ (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Load 2-element structure to all lanes of 2 registers, 1D size
+def : InstRW<[Ampere1BWrite_4cyc_2L],
+ (instregex "^LD2Rv1d")>;
+// -- Load 2-element structure to all lanes of 2 registers, other sizes
+def : InstRW<[Ampere1BWrite_6cyc_2L_2XY],
+ (instregex "^LD2Rv(8b|4h|2s|16b|8h|4s|2d)")>;
+// -- Load 2-element structure to one lane of 2 registers
+def : InstRW<[Ampere1BWrite_6cyc_2L_2XY],
+ (instregex "^LD2i(8|16|32|64)")>;
+// -- Load 2-element structures to 2 registers, 16B/8H/4S/2D size
+def : InstRW<[Ampere1BWrite_6cyc_2L_2XY],
+ (instregex "^LD2Twov(16b|8h|4s|2d)")>;
+// -- Load 2-element structures to 2 registers, 8B/4H/2S size
+def : InstRW<[Ampere1BWrite_8cyc_2L_3XY],
+ (instregex "^LD2Twov(8b|4h|2s)")>;
+// -- Load 3-element structure to all lanes of 3 registers, 1D size
+def : InstRW<[Ampere1BWrite_5cyc_3L],
+ (instregex "^LD3Rv1d")>;
+// -- Load 3-element structure to all lanes of 3 registers, other sizes
+def : InstRW<[Ampere1BWrite_7cyc_3L_3XY],
+ (instregex "^LD3Rv(8b|4h|2s|16b|8h|4s|2d)")>;
+// -- Load 3-element structure to one lane of 3 registers
+def : InstRW<[Ampere1BWrite_7cyc_3L_3XY],
+ (instregex "^LD3i(8|16|32|64)")>;
+// -- Load 3-element structures to 3 registers, 16B/8H/4S sizes
+def : InstRW<[Ampere1BWrite_8cyc_3L_3XY],
+ (instregex "^LD3Threev(16b|8h|4s)")>;
+// -- Load 3-element structures to 3 registers, 2D size
+def : InstRW<[Ampere1BWrite_7cyc_3L_3XY],
+ (instregex "^LD3Threev2d")>;
+// -- Load 3-element structures to 3 registers, 8B/4H/2S sizes
+def : InstRW<[Ampere1BWrite_9cyc_3L_3XY],
+ (instregex "^LD3Threev(8b|4h|2s)")>;
+// -- Load 4-element structure to all lanes of 4 registers, 1D size
+def : InstRW<[Ampere1BWrite_5cyc_4L],
+ (instregex "^LD4Rv1d")>;
+// -- Load 4-element structure to all lanes of 4 registers, other sizes
+def : InstRW<[Ampere1BWrite_7cyc_4L_4XY],
+ (instregex "^LD4Rv(8b|4h|2s|16b|8h|4s|2d)")>;
+// -- Load 4-element structure to one lane of 4 registers
+def : InstRW<[Ampere1BWrite_7cyc_4L_4XY],
+ (instregex "^LD4i(8|16|32|64)")>;
+// -- Load 4-element structures to 4 registers, 2D size
+def : InstRW<[Ampere1BWrite_8cyc_4L_4XY],
+ (instregex "^LD4Fourv2d")>;
+// -- Load 4-element structures to 4 registers, 2S size
+def : InstRW<[Ampere1BWrite_11cyc_4L_8XY],
+ (instregex "^LD4Fourv2s")>;
+// -- Load 4-element structures to 4 registers, other sizes
+def : InstRW<[Ampere1BWrite_10cyc_4L_8XY],
+ (instregex "^LD4Fourv(8b|4h|16b|8h|4s)")>;
+// -- Load pair, Q-form
+def : InstRW<[Ampere1BWrite_4cyc_2L], (instregex "LDN?PQ")>;
+// -- Load pair, S/D-form
+def : InstRW<[Ampere1BWrite_5cyc_1L_1BS], (instregex "LDN?P(S|D)")>;
+// -- Load register
+def : InstRW<[Ampere1BWrite_4cyc_1L], (instregex "LDU?R[BHSDQ]i")>;
+// -- Load register, sign-extended register
+def : InstRW<[Ampere1BWrite_4cyc_1L], (instregex "LDR[BHSDQ]ro(W|X)")>;
+
+// FP and vector store instructions
+// -- Store 1-element structure from one lane of 1 register
+def : InstRW<[Ampere1BWrite_4cyc_1XY_1S_1Z],
+ (instregex "^ST1i(8|16|32|64)")>;
+// -- Store 1-element structures from 1 register
+def : InstRW<[Ampere1BWrite_2cyc_1S_1Z],
+ (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Store 1-element structures from 2 registers
+def : InstRW<[Ampere1BWrite_3cyc_2S_2Z],
+ (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Store 1-element structures from 3 registers
+def : InstRW<[Ampere1BWrite_4cyc_3S_3Z],
+ (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Store 1-element structures from 4 registers
+def : InstRW<[Ampere1BWrite_5cyc_4S_4Z],
+ (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Store 2-element structure from one lane of 2 registers
+def : InstRW<[Ampere1BWrite_5cyc_2XY_2S_2Z],
+ (instregex "^ST2i(8|16|32|64)")>;
+// -- Store 2-element structures from 2 registers, 16B/8H/4S/2D sizes
+def : InstRW<[Ampere1BWrite_5cyc_2XY_2S_2Z],
+ (instregex "^ST2Twov(16b|8h|4s|2d)")>;
+// -- Store 2-element structures from 2 registers, 8B/4H/2S sizes
+def : InstRW<[Ampere1BWrite_6cyc_2XY_2S_2Z],
+ (instregex "^ST2Twov(8b|4h|2s)")>;
+// -- Store 3-element structure from one lane of 3 registers
+def : InstRW<[Ampere1BWrite_6cyc_3XY_3S_3Z],
+ (instregex "^ST3i(8|16|32|64)")>;
+// -- Store 3-element structures from 3 registers
+def : InstRW<[Ampere1BWrite_6cyc_3XY_3S_3Z],
+ (instregex "^ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)")>;
+// -- Store 4-element structure from one lane of 4 registers
+def : InstRW<[Ampere1BWrite_7cyc_4XY_4S_4Z],
+ (instregex "^ST4i(8|16|32|64)")>;
+// -- Store 4-element structures from 4 registers, 16B/8H/4S sizes
+def : InstRW<[Ampere1BWrite_7cyc_4XY_4S_4Z],
+ (instregex "^ST4Fourv(16b|8h|4s)")>;
+// -- Store 4-element structures from 4 registers, 2D sizes
+def : InstRW<[Ampere1BWrite_7cyc_4XY_4S_4Z],
+ (instregex "^ST4Fourv2d")>;
+// -- Store 4-element structures from 4 registers, 8B/4H/2S sizes
+def : InstRW<[Ampere1BWrite_9cyc_6XY_4S_4Z],
+ (instregex "^ST4Fourv(8b|4h|2s)")>;
+// -- Store pair, Q-form
+def : InstRW<[Ampere1BWrite_3cyc_2S_2Z], (instregex "^STN?PQ")>;
+// -- Store pair, S/D-form
+def : InstRW<[Ampere1BWrite_3cyc_2S_2Z], (instregex "^STN?P[SD]")>;
+// -- Store register
+def : InstRW<[Ampere1BWrite_2cyc_1S_1Z], (instregex "^STU?R[BHSDQ](ui|i)")>;
+// -- Store register, sign-extended register offset
+def : InstRW<[Ampere1BWrite_2cyc_1S_1Z], (instregex "^STR[BHSDQ]ro[XW]")>;
+
+// FP data processing, bfloat16 format
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instrs BFCVT)>;
+def : InstRW<[Ampere1BWrite_8cyc_2XY], (instrs BFCVTN, BFCVTN2)>;
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^BFDOTv", "^BF16DOT")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instrs BFMMLA)>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^BFMLAL")>;
+
+// FP data processing, scalar/vector, half precision
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^F(ABD|ABS)v.[fi]16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(ADD|ADDP|CADD|NEG|NMUL|SUB)v.[fi]16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v.[fi]16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1X],
+ (instregex "^FCMPE?H")>;
+def : InstRW<[Ampere1BWrite_9cyc_1A_1BS_1X],
+ (instregex "^FCCMPE?H")>;
+def : InstRW<[Ampere1BWrite_9cyc_1A_1BS_1XY],
+ (instregex "^FCSELH")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if]16")>;
+// Convert FP to integer, H-form
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^[SUd]CVTFv.[fi]16")>;
+// Convert to FP from GPR, H-form
+def : InstRW<[Ampere1BWrite_8cyc_1BS_1XY], (instregex "^[SU]CVTF_ZPmZ_[DSH]toH$")>;
+// Convert to FP from GPR, fixed-point, H-form
+def : InstRW<[Ampere1BWrite_11cyc_1BS_2XY], (instregex "^[SU]CVTF[SU][WX]Hri$")>;
+def : InstRW<[Ampere1BWrite_9cyc_1X], (instrs FDIVHrr)>;
+def : InstRW<[Ampere1BWrite_17cyc_1X], (instregex "^FDIVv.[if]16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^F(MAX|MIN)(NM)?P?v.[if]16")>;
+def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv4[if]16")>;
+def : InstRW<[Ampere1BWrite_9cyc_3XY], (instregex "^F(MAX|MIN)(NM)?Vv8[if]16")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FMULX?v.[if]16")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instrs FMULX16)>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FN?M(ADD|SUB)[H]rrr")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FML[AS]v.[if]16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRECPXv.[if]16")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^F(RECP|RSQRT)S16")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if]16")>;
+// FP square root, H-form
+def : InstRW<[Ampere1BWrite_21cyc_1X], (instrs FSQRTHr)>;
+// FP square root, vector-form, F16
+def : InstRW<[Ampere1BWrite_39cyc_1X], (instregex "^FSQRTv.f16")>;
+
+// FP data processing, scalar/vector, single/double precision
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^F(ABD|ABS)v.[fi](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(ADD|ADDP|CADD|NEG|NMUL|SUB)v.[fi](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v.[fi](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1X],
+ (instregex "^FCMPE?(S|D)")>;
+def : InstRW<[Ampere1BWrite_9cyc_1A_1BS_1X],
+ (instregex "^FCCMPE?(S|D)")>;
+def : InstRW<[Ampere1BWrite_9cyc_1A_1BS_1XY],
+ (instregex "^FCSEL(S|D)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if](32|64)")>;
+// Convert FP to integer, S/D-form
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^[SUd]CVTFv.[fi](32|64)")>;
+// Convert to FP from GPR, S/D-form
+def : InstRW<[Ampere1BWrite_8cyc_1BS_1XY], (instregex "^[SU]CVTF_ZPmZ_[DSH]to[DS]$")>;
+// Convert to FP from GPR, fixed-point, S/D-form
+def : InstRW<[Ampere1BWrite_11cyc_1BS_2XY], (instregex "^[SU]CVTF[SU][WX][SD]ri$")>;
+def : InstRW<[Ampere1BWrite_19cyc_1X], (instregex "^FDIVv.[if](64)", "FDIVD")>;
+def : InstRW<[Ampere1BWrite_12cyc_1X], (instregex "^FDIVv.[if](32)", "FDIVS")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^F(MAX|MIN)(NM)?P?v.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FMULX?v.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instrs FMULX32, FMULX64)>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instrs FMULSrr, FNMULSrr)>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instrs FMULDrr, FNMULDrr)>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FN?M(ADD|SUB)[SD]rrr")>;
+def : InstRW<[Ampere1BWrite_4cyc_1XY], (instregex "^FML[AS]v.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRECPXv.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^F(RECP|RSQRT)S(32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if](32|64)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT(32|64)")>;
+def : InstRW<[Ampere1BWrite_63cyc_1X], (instregex "^FSQRTv.f64", "^FSQRTDr")>;
+def : InstRW<[Ampere1BWrite_33cyc_1X], (instregex "^FSQRTv.f32", "^FSQRTSr")>;
+
+// FP miscellaneous instructions
+def : InstRW<[Ampere1BWrite_7cyc_1XY_1Z], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[HSD]Hr")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[HSD][SD]r")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVTLv")>;
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT(N|XN)v")>;
+def : InstRW<[Ampere1BWrite_7cyc_1X_1Z], (instrs FJCVTZS)>;
+def : InstRW<[Ampere1BWrite_5cyc_1BS], (instregex "^FMOV[HSD][WX]r")>;
+def : InstRW<[Ampere1BWrite_7cyc_1BS_1XY], (instregex "^FMOVDXHighr")>;
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^FMOV[HSD][ri]")>;
+def : InstRW<[Ampere1BWrite_5cyc_1X], (instregex "^FMOVXDHighr")>;
+def : InstRW<[Ampere1BWrite_3cyc_1Z], (instregex "^FMOV[WX][HSD]r")>;
+
+// Integer arithmetic and logical instructions
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instregex "ADC(W|X)r", "SBC(W|X)r")>;
+def : InstRW<[Ampere1BWrite_Arith],
+ (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[sx]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1AB],
+ (instregex "(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[ri]")>;
+def : InstRW<[Ampere1BWrite_ArithFlagsetting],
+ (instregex "(ADD|AND|BIC|SUB)S[WX]r[sx]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instregex "(ADD|AND|BIC|SUB)S[WX]r[ri]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instregex "(ADC|SBC)S[WX]r")>;
+def : InstRW<[Ampere1BWrite_1cyc_1A], (instrs RMIF)>;
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instregex "(CCMN|CCMP)(X|W)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1A],
+ (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
+def : InstRW<[Ampere1BWrite_13cyc_1BS_1X], (instrs SDIVWr, UDIVWr)>;
+def : InstRW<[Ampere1BWrite_19cyc_2BS_1X], (instrs SDIVXr, UDIVXr)>;
+def : InstRW<[Ampere1BWrite_3cyc_1BS],
+ (instregex "(S|U)MULHr")>;
+def : InstRW<[Ampere1BWrite_4cyc_1BS_1AB],
+ (instregex "(S|U)?M(ADD|SUB)L?r")>;
+
+// Integer load instructions
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "(LDNP|LDP|LDPSW)(X|W)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDR(B|D|H|Q|S)ui")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDR(D|Q|W|X)l")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDTR(B|H|W|X)i")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDUR(BB|HH|X|W)i")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDURS(BW|BX|HW|HX|W)i")>;
+def : InstRW<[Ampere1BWrite_3cyc_1L],
+ (instregex "LDR(HH|SHW|SHX|W|X)ro(W|X)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1L],
+ (instrs PRFMl, PRFUMi, PRFUMi)>;
+def : InstRW<[Ampere1BWrite_1cyc_1L],
+ (instrs PRFMroW, PRFMroX)>;
+
+// Integer miscellaneous instructions
+def : InstRW<[Ampere1BWrite_1cyc_1A], (instrs ADR, ADRP)>;
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instregex "EXTR(W|X)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instregex "(S|U)?BFM(W|X)")>;
+def : InstRW<[Ampere1BWrite_3cyc_1BS], (instregex "^CRC32C?[BHWX]")>;
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instregex "CLS(W|X)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1A], (instrs SETF8, SETF16)>;
+def : InstRW<[Ampere1BWrite_1cyc_1AB],
+ (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>;
+def : InstRW<[Ampere1BWrite_1cyc_1B],
+ (instregex "(RBIT|REV|REV16)(W|X)r", "REV32Xr")>;
+def : InstRW<[Ampere1BWrite_1cyc_1B],
+ (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
+
+// Integer store instructions
+def : InstRW<[Ampere1BWrite_1cyc_2S], (instregex "STNP(X|W)i")>;
+def : InstRW<[Ampere1BWrite_1cyc_2S], (instrs STPXi)>;
+def : InstRW<[Ampere1BWrite_2cyc_1B_1S], (instrs STPWi)>;
+def : InstRW<[Ampere1BWrite_2cyc_1B_1S_1AB], (instregex "STP(W|X)(pre|post)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1S], (instrs STTRBi, STTRHi, STTRWi, STTRXi)>;
+def : InstRW<[Ampere1BWrite_1cyc_1S], (instregex "STUR(BB|HH|X|W)i",
+ "STR(X|W)ui",
+ "STUR(BB|HH|X|W)i")>;
+def : InstRW<[Ampere1BWrite_1cyc_2S], (instrs STRWroX, STRXroX)>;
+def : InstRW<[Ampere1BWrite_1cyc_2S], (instrs STRWroW, STRXroW)>;
+
+// Memory tagging
+
+// Insert Random Tags
+def : InstRW<[Ampere1BWrite_1cyc_1BS_1B], (instrs IRG, IRGstack)>;
+// Load allocation tag
+def : InstRW<[Ampere1BWrite_4cyc_1L_1B], (instrs LDG, LDGM)>;
+// Store allocation tags
+def : InstRW<[Ampere1BWrite_1cyc_1S],
+ (instrs STGi, STGM, STGPreIndex, STGPostIndex)>;
+// Store allocation tags and pair of registers
+def : InstRW<[Ampere1BWrite_1cyc_2S],
+ (instrs STGPi, STGPpre, STGPpost)>;
+// Store allocation tags and zero data
+def : InstRW<[Ampere1BWrite_1cyc_1S],
+ (instrs STZGi, STZGM, STZGPreIndex, STZGPostIndex)>;
+// Store two tags
+def : InstRW<[Ampere1BWrite_1cyc_2S],
+ (instrs ST2Gi, ST2GPreIndex, ST2GPostIndex)>;
+// Store two tags and zero data
+def : InstRW<[Ampere1BWrite_1cyc_2S],
+ (instrs STZ2Gi, STZ2GPreIndex, STZ2GPostIndex)>;
+// Subtract Pointer
+def : InstRW<[Ampere1BWrite_1cyc_1AB], (instrs SUBP)>;
+// Subtract Pointer, flagset
+def : InstRW<[Ampere1BWrite_1cyc_1AB], (instrs SUBPS)>;
+// Insert Tag Mask
+def : InstRW<[Ampere1BWrite_1cyc_1AB], (instrs GMI)>;
+// Arithmetic, immediate to logical address tag
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instrs ADDG, SUBG)>;
+
+// Pointer authentication
+def : InstRW<[Ampere1BWrite_5cyc_1BS], (instregex "^AUT")>;
+def : InstRW<[Ampere1BWrite_6cyc_1BS_1A],
+ (instregex "BRA(A|AZ|B|BZ)", "RETA(A|B)", "ERETA(A|B)")>;
+def : InstRW<[Ampere1BWrite_6cyc_1BS_2A],
+ (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ)>;
+def : InstRW<[Ampere1BWrite_5cyc_1BS], (instregex "^PAC")>;
+def : InstRW<[Ampere1BWrite_8cyc_1BS_1L], (instregex "^LDRA(A|B)")>;
+def : InstRW<[Ampere1BWrite_1cyc_1B], (instrs XPACD, XPACI)>;
+
+// Vector integer instructions
+// -- absolute difference
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SABAv", "^SABALv", "^SABDv", "^SABDLv",
+ "^UABAv", "^UABALv", "^UABDv", "^UABDLv")>;
+// -- arithmetic
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^ABSv", "^(ADD|SUB)v", "^SADDLv", "^SADDW", "SHADD",
+ "SHSUB", "^SRHADD", "^URHADD", "SSUBL", "SSUBW",
+ "^UADDLv", "^UADDW", "UHADD", "UHSUB", "USUBL", "USUBW")>;
+// -- arithmetic, horizontal, 16B
+def : InstRW<[Ampere1BWrite_8cyc_4XY],
+ (instregex "^ADDVv16i8v", "^SADDLVv16i8v", "^UADDLVv16i8v")>;
+def : InstRW<[Ampere1BWrite_8cyc_4XY],
+ (instregex "^[SU](MIN|MAX)Vv16i8v")>;
+// -- arithmetic, horizontal, 4H/4S
+def : InstRW<[Ampere1BWrite_4cyc_2XY],
+ (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v")>;
+def : InstRW<[Ampere1BWrite_4cyc_2XY],
+ (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v")>;
+// -- arithmetic, horizontal, 8B/8H
+def : InstRW<[Ampere1BWrite_6cyc_3XY],
+ (instregex "^[SU]?ADDL?V(v8i16|v4i32)v")>;
+def : InstRW<[Ampere1BWrite_6cyc_3XY],
+ (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v")>;
+// -- arithmetic, narrowing
+def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "(ADD|SUB)HNv.*")>;
+def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "(RADD|RSUB)HNv.*")>;
+// -- arithmetic, pairwise
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^ADDPv", "^SADALP", "^UADALP", "^SADDLPv", "^UADDLPv")>;
+// -- arithmetic, saturating
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SQADD", "^SQSUB", "^SUQADD", "^UQADD", "^UQSUB", "^USQADD")>;
+// -- bit count
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^(CLS|CLZ|CNT)v")>;
+// -- compare
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^CMEQv", "^CMGEv", "^CMGTv", "^CMLEv", "^CMLTv",
+ "^CMHIv", "^CMHSv")>;
+// -- compare non-zero
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^CMTSTv")>;
+// -- dot product
+def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^(S|SU|U|US)DOTv")>;
+// -- fp reciprocal estimate
+def : InstRW<[Ampere1BWrite_6cyc_1X], (instregex "^FRECPEv", "^FRSQRTEv")>;
+// -- integer reciprocal estimate
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^URECPEv", "^URSQRTEv")>;
+// -- logical
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>;
+// -- logical, narrowing
+def : InstRW<[Ampere1BWrite_6cyc_2XY],
+ (instregex "RSHRNv",
+ "SHRNv", "SQSHRNv", "SQSHRUNv",
+ "UQXTNv")>;
+// -- matrix multiply
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instrs SMMLA, UMMLA, USMMLA)>;
+// -- max/min
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SMAXv", "^SMINv", "^UMAXv", "^UMINv")>;
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SMAXPv", "^SMINPv", "^UMAXPv", "^UMINPv")>;
+// -- move immediate
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^MOVIv", "^MVNIv")>;
+// -- multiply
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "MULv", "SMULLv", "UMULLv", "SQDMUL(H|L)v", "SQRDMULHv")>;
+// -- multiply accumulate
+def : InstRW<[Ampere1BWrite_3cyc_1XY],
+ (instregex "MLAv", "MLSv", "(S|U|SQD)(MLAL|MLSL)v", "SQRDML(A|S)Hv")>;
+// -- negation, saturating
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^SQABS", "^SQNEG")>;
+// -- reverse bits/bytes
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^RBITv", "^REV16v", "^REV32v", "^REV64v")>;
+// -- shift
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
+// -- shift and accumulate
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "SRSRAv", "SSRAv", "URSRAv", "USRAv")>;
+// -- shift, saturating
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^SQRSHLv", "^SQRSHRNv", "^SQRSHRUNv", "^SQSHL", "^SQSHLU",
+ "^SQXTNv", "^SQXTUNv", "^UQSHRNv", "UQRSHRNv", "^UQRSHL",
+ "^UQSHL")>;
+
+// Vector miscellaneous instructions
+// -- duplicate element
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^DUPv.+lane")>;
+// -- duplicate from GPR
+def : InstRW<[Ampere1BWrite_5cyc_1BS], (instregex "^DUPv.+gpr")>;
+// -- extract narrow
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^XTNv")>;
+// -- insert/extract element
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^EXTv", "^INSv.+lane")>;
+// -- move FP immediate
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^FMOVv")>;
+// -- move element to GPR
+def : InstRW<[Ampere1BWrite_5cyc_1X], (instregex "(S|U)MOVv")>;
+// -- move from GPR to any element
+def : InstRW<[Ampere1BWrite_7cyc_1BS_1XY], (instregex "^INSv.+gpr")>;
+// -- table lookup
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instrs TBLv8i8One, TBLv16i8One, TBXv8i8One, TBXv16i8One)>;
+def : InstRW<[Ampere1BWrite_4cyc_2XY],
+ (instrs TBLv8i8Two, TBLv16i8Two, TBXv8i8Two, TBXv16i8Two)>;
+def : InstRW<[Ampere1BWrite_6cyc_3XY],
+ (instrs TBLv8i8Three, TBLv16i8Three, TBXv8i8Three, TBXv16i8Three)>;
+def : InstRW<[Ampere1BWrite_8cyc_4XY],
+ (instrs TBLv8i8Four, TBLv16i8Four, TBXv8i8Four, TBXv16i8Four)>;
+// -- transpose
+def : InstRW<[Ampere1BWrite_2cyc_1XY],
+ (instregex "^TRN1v", "^TRN2v", "^UZP1v", "^UZP2v")>;
+// -- zip/unzip
+def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^ZIP1v", "^ZIP2v")>;
+
+} // SchedModel = Ampere1BModel
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 1ef3a2a063382d..48324654949c06 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -21,7 +21,7 @@ def CycloneModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 2127a34a58d513..6fc4ec3ae41b77 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -27,7 +27,7 @@ def ExynosM3Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index 83cf56088d4ced..5163de280f2e4f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -27,7 +27,7 @@ def ExynosM4Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
index 85058af86decb5..2ccbe1614dcd79 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -27,7 +27,7 @@ def ExynosM5Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
index a765cd1cdfe347..e9172e82b099d1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
@@ -26,7 +26,7 @@ def FalkorModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
index 3551066ee7c35d..258b34c38898cd 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
@@ -30,7 +30,7 @@ def KryoModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
index 2ec9600f84f7e5..524fa33f498bb0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
@@ -25,7 +25,7 @@ def NeoverseN1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,
SMEUnsupported.F,
SVEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index a6fab5e6245f80..8ec124954362f8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1, HasPAuthLR, HasCPA]);
+ [HasSVE2p1, HasPAuthLR, HasCPA, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 75fbb85dce9d14..7e041dbd2abaea 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -28,7 +28,8 @@ def NeoverseV1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCPA]);
+ [HasMTE, HasCPA,
+ HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 658d7cdd23a63b..e7de40fdf1deb0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -22,7 +22,8 @@ def NeoverseV2Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- [HasSVE2p1, HasCPA]);
+ [HasSVE2p1, HasCPA,
+ HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
index 9e5060f1f36496..0ae9a69fd48265 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -27,7 +27,7 @@ def TSV110Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
}
// Define each kind of processor resource and number available on the TSV110,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index e1536f208e448a..8df3f56e45738c 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -28,7 +28,7 @@ def ThunderXT8XModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index 89faa92155e00d..ef4baa3dedff93 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -28,7 +28,7 @@ def ThunderX2T99Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 8685554b00d76d..796bd4b8b5c9ae 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -27,7 +27,7 @@ def ThunderX3T110Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
new file mode 100644
index 00000000000000..7dd05eb50085c8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
@@ -0,0 +1,3724 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# Add/sub (immediate)
+#------------------------------------------------------------------------------
+
+add w2, w3, #4095
+add w30, w29, #1, lsl #12
+add w13, w5, #4095, lsl #12
+add x5, x7, #1638
+add w20, wsp, #801
+add wsp, wsp, #1104
+add wsp, w30, #4084
+add x0, x24, #291
+add x3, x24, #4095, lsl #12
+add x8, sp, #1074
+add sp, x29, #3816
+sub w0, wsp, #4077
+sub w4, w20, #546, lsl #12
+sub sp, sp, #288
+sub wsp, w19, #16
+adds w13, w23, #291, lsl #12
+cmn w2, #4095
+adds w20, wsp, #0
+cmn x3, #1, lsl #12
+cmp sp, #20, lsl #12
+cmp x30, #4095
+subs x4, sp, #3822
+cmn w3, #291, lsl #12
+cmn wsp, #1365
+cmn sp, #1092, lsl #12
+mov sp, x30
+mov wsp, w20
+mov x11, sp
+mov w24, wsp
+
+#------------------------------------------------------------------------------
+# Add-subtract (shifted register)
+#------------------------------------------------------------------------------
+
+add w3, w5, w7
+add wzr, w3, w5
+add w20, wzr, w4
+add w4, w6, wzr
+add w11, w13, w15
+add w9, w3, wzr, lsl #10
+add w17, w29, w20, lsl #31
+add w21, w22, w23, lsr #0
+add w24, w25, w26, lsr #18
+add w27, w28, w29, lsr #31
+add w2, w3, w4, asr #0
+add w5, w6, w7, asr #21
+add w8, w9, w10, asr #31
+add x3, x5, x7
+add xzr, x3, x5
+add x20, xzr, x4
+add x4, x6, xzr
+add x11, x13, x15
+add x9, x3, xzr, lsl #10
+add x17, x29, x20, lsl #63
+add x21, x22, x23, lsr #0
+add x24, x25, x26, lsr #18
+add x27, x28, x29, lsr #63
+add x2, x3, x4, asr #0
+add x5, x6, x7, asr #21
+add x8, x9, x10, asr #63
+adds w3, w5, w7
+cmn w3, w5
+adds w20, wzr, w4
+adds w4, w6, wzr
+adds w11, w13, w15
+adds w9, w3, wzr, lsl #10
+adds w17, w29, w20, lsl #31
+adds w21, w22, w23, lsr #0
+adds w24, w25, w26, lsr #18
+adds w27, w28, w29, lsr #31
+adds w2, w3, w4, asr #0
+adds w5, w6, w7, asr #21
+adds w8, w9, w10, asr #31
+adds x3, x5, x7
+cmn x3, x5
+adds x20, xzr, x4
+adds x4, x6, xzr
+adds x11, x13, x15
+adds x9, x3, xzr, lsl #10
+adds x17, x29, x20, lsl #63
+adds x21, x22, x23, lsr #0
+adds x24, x25, x26, lsr #18
+adds x27, x28, x29, lsr #63
+adds x2, x3, x4, asr #0
+adds x5, x6, x7, asr #21
+adds x8, x9, x10, asr #63
+sub w3, w5, w7
+sub wzr, w3, w5
+sub w4, w6, wzr
+sub w11, w13, w15
+sub w9, w3, wzr, lsl #10
+sub w17, w29, w20, lsl #31
+sub w21, w22, w23, lsr #0
+sub w24, w25, w26, lsr #18
+sub w27, w28, w29, lsr #31
+sub w2, w3, w4, asr #0
+sub w5, w6, w7, asr #21
+sub w8, w9, w10, asr #31
+sub x3, x5, x7
+sub xzr, x3, x5
+sub x4, x6, xzr
+sub x11, x13, x15
+sub x9, x3, xzr, lsl #10
+sub x17, x29, x20, lsl #63
+sub x21, x22, x23, lsr #0
+sub x24, x25, x26, lsr #18
+sub x27, x28, x29, lsr #63
+sub x2, x3, x4, asr #0
+sub x5, x6, x7, asr #21
+sub x8, x9, x10, asr #63
+subs w3, w5, w7
+cmp w3, w5
+subs w4, w6, wzr
+subs w11, w13, w15
+subs w9, w3, wzr, lsl #10
+subs w17, w29, w20, lsl #31
+subs w21, w22, w23, lsr #0
+subs w24, w25, w26, lsr #18
+subs w27, w28, w29, lsr #31
+subs w2, w3, w4, asr #0
+subs w5, w6, w7, asr #21
+subs w8, w9, w10, asr #31
+subs x3, x5, x7
+cmp x3, x5
+subs x4, x6, xzr
+subs x11, x13, x15
+subs x9, x3, xzr, lsl #10
+subs x17, x29, x20, lsl #63
+subs x21, x22, x23, lsr #0
+subs x24, x25, x26, lsr #18
+subs x27, x28, x29, lsr #63
+subs x2, x3, x4, asr #0
+subs x5, x6, x7, asr #21
+subs x8, x9, x10, asr #63
+cmn wzr, w4
+cmn w5, wzr
+cmn w6, w7
+cmn w8, w9, lsl #15
+cmn w10, w11, lsl #31
+cmn w12, w13, lsr #0
+cmn w14, w15, lsr #21
+cmn w16, w17, lsr #31
+cmn w18, w19, asr #0
+cmn w20, w21, asr #22
+cmn w22, w23, asr #31
+cmn x0, x3
+cmn xzr, x4
+cmn x5, xzr
+cmn x6, x7
+cmn x8, x9, lsl #15
+cmn x10, x11, lsl #63
+cmn x12, x13, lsr #0
+cmn x14, x15, lsr #41
+cmn x16, x17, lsr #63
+cmn x18, x19, asr #0
+cmn x20, x21, asr #55
+cmn x22, x23, asr #63
+cmp w0, w3
+cmp wzr, w4
+cmp w5, wzr
+cmp w6, w7
+cmp w8, w9, lsl #15
+cmp w10, w11, lsl #31
+cmp w12, w13, lsr #0
+cmp w14, w15, lsr #21
+cmp w18, w19, asr #0
+cmp w20, w21, asr #22
+cmp w22, w23, asr #31
+cmp x0, x3
+cmp xzr, x4
+cmp x5, xzr
+cmp x6, x7
+cmp x8, x9, lsl #15
+cmp x10, x11, lsl #63
+cmp x12, x13, lsr #0
+cmp x14, x15, lsr #41
+cmp x16, x17, lsr #63
+cmp x18, x19, asr #0
+cmp x20, x21, asr #55
+cmp x22, x23, asr #63
+cmp wzr, w0
+cmp xzr, x0
+
+#------------------------------------------------------------------------------
+# Add-subtract (shifted register)
+#------------------------------------------------------------------------------
+
+adc w29, w27, w25
+adc wzr, w3, w4
+adc w9, wzr, w10
+adc w20, w0, wzr
+adc x29, x27, x25
+adc xzr, x3, x4
+adc x9, xzr, x10
+adc x20, x0, xzr
+adcs w29, w27, w25
+adcs wzr, w3, w4
+adcs w9, wzr, w10
+adcs w20, w0, wzr
+adcs x29, x27, x25
+adcs xzr, x3, x4
+adcs x9, xzr, x10
+adcs x20, x0, xzr
+sbc w29, w27, w25
+sbc wzr, w3, w4
+ngc w9, w10
+sbc w20, w0, wzr
+sbc x29, x27, x25
+sbc xzr, x3, x4
+ngc x9, x10
+sbc x20, x0, xzr
+sbcs w29, w27, w25
+sbcs wzr, w3, w4
+ngcs w9, w10
+sbcs w20, w0, wzr
+sbcs x29, x27, x25
+sbcs xzr, x3, x4
+ngcs x9, x10
+sbcs x20, x0, xzr
+ngc w3, w12
+ngc wzr, w9
+ngc w23, wzr
+ngc x29, x30
+ngc xzr, x0
+ngc x0, xzr
+ngcs w3, w12
+ngcs wzr, w9
+ngcs w23, wzr
+ngcs x29, x30
+ngcs xzr, x0
+ngcs x0, xzr
+
+#------------------------------------------------------------------------------
+# Compare and branch (immediate)
+#------------------------------------------------------------------------------
+
+sbfx x1, x2, #3, #2
+asr x3, x4, #63
+asr wzr, wzr, #31
+sbfx w12, w9, #0, #1
+ubfiz x4, x5, #52, #11
+ubfx xzr, x4, #0, #1
+ubfiz x4, xzr, #1, #6
+lsr x5, x6, #12
+bfi x4, x5, #52, #11
+bfxil xzr, x4, #0, #1
+bfi x4, xzr, #1, #6
+bfxil x5, x6, #12, #52
+sxtb w1, w2
+sxtb xzr, w3
+sxth w9, w10
+sxth x0, w1
+sxtw x3, w30
+uxtb w1, w2
+uxth w9, w10
+ubfx x3, x30, #0, #32
+asr w3, w2, #0
+asr w9, w10, #31
+asr x20, x21, #63
+asr w1, wzr, #3
+lsr w3, w2, #0
+lsr w9, w10, #31
+lsr x20, x21, #63
+lsr wzr, wzr, #3
+lsr w3, w2, #0
+lsl w9, w10, #31
+lsl x20, x21, #63
+lsl w1, wzr, #3
+sbfx w9, w10, #0, #1
+sbfiz x2, x3, #63, #1
+asr x19, x20, #0
+sbfiz x9, x10, #5, #59
+asr w9, w10, #0
+sbfiz w11, w12, #31, #1
+sbfiz w13, w14, #29, #3
+sbfiz xzr, xzr, #10, #11
+sbfx w9, w10, #0, #1
+asr x2, x3, #63
+asr x19, x20, #0
+asr x9, x10, #5
+asr w9, w10, #0
+asr w11, w12, #31
+asr w13, w14, #29
+sbfx xzr, xzr, #10, #11
+bfxil w9, w10, #0, #1
+bfi x2, x3, #63, #1
+bfxil x19, x20, #0, #64
+bfi x9, x10, #5, #59
+bfxil w9, w10, #0, #32
+bfi w11, w12, #31, #1
+bfi w13, w14, #29, #3
+bfi xzr, xzr, #10, #11
+bfxil w9, w10, #0, #1
+bfxil x2, x3, #63, #1
+bfxil x19, x20, #0, #64
+bfxil x9, x10, #5, #59
+bfxil w9, w10, #0, #32
+bfxil w11, w12, #31, #1
+bfxil w13, w14, #29, #3
+bfxil xzr, xzr, #10, #11
+ubfx w9, w10, #0, #1
+lsl x2, x3, #63
+lsr x19, x20, #0
+lsl x9, x10, #5
+lsr w9, w10, #0
+lsl w11, w12, #31
+lsl w13, w14, #29
+ubfiz xzr, xzr, #10, #11
+ubfx w9, w10, #0, #1
+lsr x2, x3, #63
+lsr x19, x20, #0
+lsr x9, x10, #5
+lsr w9, w10, #0
+lsr w11, w12, #31
+lsr w13, w14, #29
+ubfx xzr, xzr, #10, #11
+
+#------------------------------------------------------------------------------
+# Compare and branch (immediate)
+#------------------------------------------------------------------------------
+
+cbz w5, #4
+cbz x5, #0
+cbnz x2, #-4
+cbnz x26, #1048572
+cbz wzr, #0
+cbnz xzr, #0
+
+#------------------------------------------------------------------------------
+# Conditional branch (immediate)
+#------------------------------------------------------------------------------
+
+b.ne #4
+b.ge #1048572
+b.ge #-4
+
+#------------------------------------------------------------------------------
+# Conditional compare (immediate)
+#------------------------------------------------------------------------------
+
+ccmp w1, #31, #0, eq
+ccmp w3, #0, #15, hs
+ccmp wzr, #15, #13, hs
+ccmp x9, #31, #0, le
+ccmp x3, #0, #15, gt
+ccmp xzr, #5, #7, ne
+ccmn w1, #31, #0, eq
+ccmn w3, #0, #15, hs
+ccmn wzr, #15, #13, hs
+ccmn x9, #31, #0, le
+ccmn x3, #0, #15, gt
+ccmn xzr, #5, #7, ne
+
+#------------------------------------------------------------------------------
+# Conditional compare (register)
+#------------------------------------------------------------------------------
+
+ccmp w1, wzr, #0, eq
+ccmp w3, w0, #15, hs
+ccmp wzr, w15, #13, hs
+ccmp x9, xzr, #0, le
+ccmp x3, x0, #15, gt
+ccmp xzr, x5, #7, ne
+ccmn w1, wzr, #0, eq
+ccmn w3, w0, #15, hs
+ccmn wzr, w15, #13, hs
+ccmn x9, xzr, #0, le
+ccmn x3, x0, #15, gt
+ccmn xzr, x5, #7, ne
+
+#------------------------------------------------------------------------------
+# Conditional branch (immediate)
+#------------------------------------------------------------------------------
+
+csel w1, w0, w19, ne
+csel wzr, w5, w9, eq
+csel w9, wzr, w30, gt
+csel w1, w28, wzr, mi
+csel x19, x23, x29, lt
+csel xzr, x3, x4, ge
+csel x5, xzr, x6, hs
+csel x7, x8, xzr, lo
+csinc w1, w0, w19, ne
+csinc wzr, w5, w9, eq
+csinc w9, wzr, w30, gt
+csinc w1, w28, wzr, mi
+csinc x19, x23, x29, lt
+csinc xzr, x3, x4, ge
+csinc x5, xzr, x6, hs
+csinc x7, x8, xzr, lo
+csinv w1, w0, w19, ne
+csinv wzr, w5, w9, eq
+csinv w9, wzr, w30, gt
+csinv w1, w28, wzr, mi
+csinv x19, x23, x29, lt
+csinv xzr, x3, x4, ge
+csinv x5, xzr, x6, hs
+csinv x7, x8, xzr, lo
+csneg w1, w0, w19, ne
+csneg wzr, w5, w9, eq
+csneg w9, wzr, w30, gt
+csneg w1, w28, wzr, mi
+csneg x19, x23, x29, lt
+csneg xzr, x3, x4, ge
+csneg x5, xzr, x6, hs
+csneg x7, x8, xzr, lo
+cset w3, eq
+cset x9, pl
+csetm w20, ne
+csetm x30, ge
+csinc w2, wzr, wzr, al
+csinv x3, xzr, xzr, nv
+cinc w3, w5, gt
+cinc wzr, w4, le
+cset w9, lt
+cinc x3, x5, gt
+cinc xzr, x4, le
+cset x9, lt
+csinc w5, w6, w6, nv
+csinc x1, x2, x2, al
+cinv w3, w5, gt
+cinv wzr, w4, le
+csetm w9, lt
+cinv x3, x5, gt
+cinv xzr, x4, le
+csetm x9, lt
+csinv x1, x0, x0, al
+csinv w9, w8, w8, nv
+cneg w3, w5, gt
+cneg wzr, w4, le
+cneg w9, wzr, lt
+cneg x3, x5, gt
+cneg xzr, x4, le
+cneg x9, xzr, lt
+csneg x4, x8, x8, al
+csinv w9, w8, w8, nv
+
+#------------------------------------------------------------------------------
+# Data-processing (1 source)
+#------------------------------------------------------------------------------
+
+rbit w0, w7
+rbit x18, x3
+rev16 w17, w1
+rev16 x5, x2
+rev w18, w0
+rev32 x20, x1
+rev x22, x2
+clz w24, w3
+clz x26, x4
+cls w3, w5
+cls x20, x5
+
+#------------------------------------------------------------------------------
+# Data-processing (2 source)
+#------------------------------------------------------------------------------
+
+udiv w0, w7, w10
+udiv x9, x22, x4
+sdiv w12, w21, w0
+sdiv x13, x2, x1
+lsl w11, w12, w13
+lsl x14, x15, x16
+lsr w17, w18, w19
+lsr x20, x21, x22
+asr w23, w24, w25
+asr x26, x27, x28
+ror w0, w1, w2
+ror x3, x4, x5
+lsl w6, w7, w8
+lsl x9, x10, x11
+lsr w12, w13, w14
+lsr x15, x16, x17
+asr w18, w19, w20
+asr x21, x22, x23
+ror w24, w25, w26
+ror x27, x28, x29
+
+#------------------------------------------------------------------------------
+# Data-processing (3 sources)
+#------------------------------------------------------------------------------
+
+smulh x30, x29, x28
+smulh xzr, x27, x26
+umulh x30, x29, x28
+umulh x23, x30, xzr
+madd w1, w3, w7, w4
+madd wzr, w0, w9, w11
+madd w13, wzr, w4, w4
+madd w19, w30, wzr, w29
+mul w4, w5, w6
+madd x1, x3, x7, x4
+madd xzr, x0, x9, x11
+madd x13, xzr, x4, x4
+madd x19, x30, xzr, x29
+mul x4, x5, x6
+msub w1, w3, w7, w4
+msub wzr, w0, w9, w11
+msub w13, wzr, w4, w4
+msub w19, w30, wzr, w29
+mneg w4, w5, w6
+msub x1, x3, x7, x4
+msub xzr, x0, x9, x11
+msub x13, xzr, x4, x4
+msub x19, x30, xzr, x29
+mneg x4, x5, x6
+smaddl x3, w5, w2, x9
+smaddl xzr, w10, w11, x12
+smaddl x13, wzr, w14, x15
+smaddl x16, w17, wzr, x18
+smull x19, w20, w21
+smsubl x3, w5, w2, x9
+smsubl xzr, w10, w11, x12
+smsubl x13, wzr, w14, x15
+smsubl x16, w17, wzr, x18
+smnegl x19, w20, w21
+umaddl x3, w5, w2, x9
+umaddl xzr, w10, w11, x12
+umaddl x13, wzr, w14, x15
+umaddl x16, w17, wzr, x18
+umull x19, w20, w21
+umsubl x3, w5, w2, x9
+umsubl x16, w17, wzr, x18
+umnegl x19, w20, w21
+smulh x30, x29, x28
+smulh x23, x22, xzr
+umulh x23, x22, xzr
+mul x19, x20, xzr
+mneg w21, w22, w23
+smull x11, w13, w17
+umull x11, w13, w17
+smnegl x11, w13, w17
+umnegl x11, w13, w17
+
+#------------------------------------------------------------------------------
+# Extract (immediate)
+#------------------------------------------------------------------------------
+
+extr w3, w5, w7, #0
+extr w11, w13, w17, #31
+extr x3, x5, x7, #15
+extr x11, x13, x17, #63
+ror x19, x23, #24
+ror x29, xzr, #63
+ror w9, w13, #31
+
+#------------------------------------------------------------------------------
+# Floating-point compare
+#------------------------------------------------------------------------------
+
+fcmp s3, s5
+fcmp s31, #0.0
+fcmp s31, #0.0
+fcmpe s29, s30
+fcmpe s15, #0.0
+fcmpe s15, #0.0
+fcmp d4, d12
+fcmp d23, #0.0
+fcmp d23, #0.0
+fcmpe d26, d22
+fcmpe d29, #0.0
+fcmpe d29, #0.0
+
+#------------------------------------------------------------------------------
+# Floating-point conditional compare
+#------------------------------------------------------------------------------
+
+fccmp s1, s31, #0, eq
+fccmp s3, s0, #15, hs
+fccmp s31, s15, #13, hs
+fccmp d9, d31, #0, le
+fccmp d3, d0, #15, gt
+fccmp d31, d5, #7, ne
+fccmpe s1, s31, #0, eq
+fccmpe s3, s0, #15, hs
+fccmpe s31, s15, #13, hs
+fccmpe d9, d31, #0, le
+fccmpe d3, d0, #15, gt
+fccmpe d31, d5, #7, ne
+
+#-------------------------------------------------------------------------------
+# Floating-point conditional compare
+#-------------------------------------------------------------------------------
+
+fcsel s3, s20, s9, pl
+fcsel d9, d10, d11, mi
+
+#------------------------------------------------------------------------------
+# Floating-point data-processing (1 source)
+#------------------------------------------------------------------------------
+
+fmov s0, s1
+fabs s2, s3
+fneg s4, s5
+fsqrt s6, s7
+fcvt d8, s9
+fcvt h10, s11
+frintn s12, s13
+frintp s14, s15
+frintm s16, s17
+frintz s18, s19
+frinta s20, s21
+frintx s22, s23
+frinti s24, s25
+fmov d0, d1
+fabs d2, d3
+fneg d4, d5
+fsqrt d6, d7
+fcvt s8, d9
+fcvt h10, d11
+frintn d12, d13
+frintp d14, d15
+frintm d16, d17
+frintz d18, d19
+frinta d20, d21
+frintx d22, d23
+frinti d24, d25
+fcvt s26, h27
+fcvt d28, h29
+
+#------------------------------------------------------------------------------
+# Floating-point data-processing (2 sources)
+#------------------------------------------------------------------------------
+
+fmul s20, s19, s17
+fdiv s1, s2, s3
+fadd s4, s5, s6
+fsub s7, s8, s9
+fmax s10, s11, s12
+fmin s13, s14, s15
+fmaxnm s16, s17, s18
+fminnm s19, s20, s21
+fnmul s22, s23, s2
+fmul d20, d19, d17
+fdiv d1, d2, d3
+fadd d4, d5, d6
+fsub d7, d8, d9
+fmax d10, d11, d12
+fmin d13, d14, d15
+fmaxnm d16, d17, d18
+fminnm d19, d20, d21
+fnmul d22, d23, d24
+
+#------------------------------------------------------------------------------
+# Floating-point data-processing (1 source)
+#------------------------------------------------------------------------------
+
+fmadd s3, s5, s6, s31
+fmadd d3, d13, d0, d23
+fmsub s3, s5, s6, s31
+fmsub d3, d13, d0, d23
+fnmadd s3, s5, s6, s31
+fnmadd d3, d13, d0, d23
+fnmsub s3, s5, s6, s31
+fnmsub d3, d13, d0, d23
+
+#------------------------------------------------------------------------------
+# Floating-point <-> fixed-point conversion
+#------------------------------------------------------------------------------
+
+fcvtzs w3, h5, #1
+fcvtzs wzr, h20, #13
+fcvtzs w19, h0, #32
+fcvtzs x3, h5, #1
+fcvtzs x12, h30, #45
+fcvtzs x19, h0, #64
+fcvtzs w3, s5, #1
+fcvtzs wzr, s20, #13
+fcvtzs w19, s0, #32
+fcvtzs x3, s5, #1
+fcvtzs x12, s30, #45
+fcvtzs x19, s0, #64
+fcvtzs w3, d5, #1
+fcvtzs wzr, d20, #13
+fcvtzs w19, d0, #32
+fcvtzs x3, d5, #1
+fcvtzs x12, d30, #45
+fcvtzs x19, d0, #64
+fcvtzu w3, h5, #1
+fcvtzu wzr, h20, #13
+fcvtzu w19, h0, #32
+fcvtzu x3, h5, #1
+fcvtzu x12, h30, #45
+fcvtzu x19, h0, #64
+fcvtzu w3, s5, #1
+fcvtzu wzr, s20, #13
+fcvtzu w19, s0, #32
+fcvtzu x3, s5, #1
+fcvtzu x12, s30, #45
+fcvtzu x19, s0, #64
+fcvtzu w3, d5, #1
+fcvtzu wzr, d20, #13
+fcvtzu w19, d0, #32
+fcvtzu x3, d5, #1
+fcvtzu x12, d30, #45
+fcvtzu x19, d0, #64
+scvtf h23, w19, #1
+scvtf h31, wzr, #20
+scvtf h14, w0, #32
+scvtf h23, x19, #1
+scvtf h31, xzr, #20
+scvtf h14, x0, #64
+scvtf s23, w19, #1
+scvtf s31, wzr, #20
+scvtf s14, w0, #32
+scvtf s23, x19, #1
+scvtf s31, xzr, #20
+scvtf s14, x0, #64
+scvtf d23, w19, #1
+scvtf d31, wzr, #20
+scvtf d14, w0, #32
+scvtf d23, x19, #1
+scvtf d31, xzr, #20
+scvtf d14, x0, #64
+ucvtf h23, w19, #1
+ucvtf h31, wzr, #20
+ucvtf h14, w0, #32
+ucvtf h23, x19, #1
+ucvtf h31, xzr, #20
+ucvtf h14, x0, #64
+ucvtf s23, w19, #1
+ucvtf s31, wzr, #20
+ucvtf s14, w0, #32
+ucvtf s23, x19, #1
+ucvtf s31, xzr, #20
+ucvtf s14, x0, #64
+ucvtf d23, w19, #1
+ucvtf d31, wzr, #20
+ucvtf d14, w0, #32
+ucvtf d23, x19, #1
+ucvtf d31, xzr, #20
+ucvtf d14, x0, #64
+
+#------------------------------------------------------------------------------
+# Floating-point <-> integer conversion
+#------------------------------------------------------------------------------
+
+fcvtns w3, h31
+fcvtns xzr, h12
+fcvtnu wzr, h12
+fcvtnu x0, h0
+fcvtps wzr, h9
+fcvtps x12, h20
+fcvtpu w30, h23
+fcvtpu x29, h3
+fcvtms w2, h3
+fcvtms x4, h5
+fcvtmu w6, h7
+fcvtmu x8, h9
+fcvtzs w10, h11
+fcvtzs x12, h13
+fcvtzu w14, h15
+fcvtzu x15, h16
+scvtf h17, w18
+scvtf h19, x20
+ucvtf h21, w22
+scvtf h23, x24
+fcvtas w25, h26
+fcvtas x27, h28
+fcvtau w29, h30
+fcvtau xzr, h0
+fcvtns w3, s31
+fcvtns xzr, s12
+fcvtnu wzr, s12
+fcvtnu x0, s0
+fcvtps wzr, s9
+fcvtps x12, s20
+fcvtpu w30, s23
+fcvtpu x29, s3
+fcvtms w2, s3
+fcvtms x4, s5
+fcvtmu w6, s7
+fcvtmu x8, s9
+fcvtzs w10, s11
+fcvtzs x12, s13
+fcvtzu w14, s15
+fcvtzu x15, s16
+scvtf s17, w18
+scvtf s19, x20
+ucvtf s21, w22
+scvtf s23, x24
+fcvtas w25, s26
+fcvtas x27, s28
+fcvtau w29, s30
+fcvtau xzr, s0
+fcvtns w3, d31
+fcvtns xzr, d12
+fcvtnu wzr, d12
+fcvtnu x0, d0
+fcvtps wzr, d9
+fcvtps x12, d20
+fcvtpu w30, d23
+fcvtpu x29, d3
+fcvtms w2, d3
+fcvtms x4, d5
+fcvtmu w6, d7
+fcvtmu x8, d9
+fcvtzs w10, d11
+fcvtzs x12, d13
+fcvtzu w14, d15
+fcvtzu x15, d16
+scvtf d17, w18
+scvtf d19, x20
+ucvtf d21, w22
+ucvtf d23, x24
+fcvtas w25, d26
+fcvtas x27, d28
+fcvtau w29, d30
+fcvtau xzr, d0
+fmov w3, s9
+fmov s9, w3
+fmov x20, d31
+fmov d1, x15
+fmov x3, v12.d[1]
+fmov v1.d[1], x19
+
+#------------------------------------------------------------------------------
+# Floating-point immediate
+#------------------------------------------------------------------------------
+
+fmov s2, #0.12500000
+fmov s3, #1.00000000
+fmov d30, #16.00000000
+fmov s4, #1.06250000
+fmov d10, #1.93750000
+fmov s12, #-1.00000000
+fmov d16, #8.50000000
+
+#------------------------------------------------------------------------------
+# Load-register (literal)
+#------------------------------------------------------------------------------
+
+ldr w3, #0
+ldr x29, #4
+ldrsw xzr, #-4
+ldr s0, #8
+ldr d0, #1048572
+ldr q0, #-1048576
+prfm pldl1strm, #0
+prfm #22, #0
+
+#------------------------------------------------------------------------------
+# Load/store exclusive
+#------------------------------------------------------------------------------
+
+stxrb w18, w8, [sp]
+stxrh w24, w15, [x16]
+stxr w5, w6, [x17]
+stxr w1, x10, [x21]
+ldxrb w30, [x0]
+ldxrh w17, [x4]
+ldxr w22, [sp]
+ldxr x11, [x29]
+ldxr x11, [x29]
+ldxr x11, [x29]
+stxp w12, w11, w10, [sp]
+stxp wzr, x27, x9, [x12]
+ldxp w0, wzr, [sp]
+ldxp x17, x0, [x18]
+ldxp x17, x0, [x18]
+stlxrb w12, w22, [x0]
+stlxrh w10, w1, [x1]
+stlxr w9, w2, [x2]
+stlxr w9, x3, [sp]
+ldaxrb w8, [x4]
+ldaxrh w7, [x5]
+ldaxr w6, [sp]
+ldaxr x5, [x6]
+ldaxr x5, [x6]
+ldaxr x5, [x6]
+stlxp w4, w5, w6, [sp]
+stlxp wzr, x6, x7, [x1]
+ldaxp w5, w18, [sp]
+ldaxp x6, x19, [x22]
+ldaxp x6, x19, [x22]
+stlrb w24, [sp]
+stlrh w25, [x30]
+stlr w26, [x29]
+stlr x27, [x28]
+stlr x27, [x28]
+stlr x27, [x28]
+ldarb w23, [sp]
+ldarh w22, [x30]
+ldar wzr, [x29]
+ldar x21, [x28]
+ldar x21, [x28]
+ldar x21, [x28]
+
+#------------------------------------------------------------------------------
+# Load/store (unscaled immediate)
+#------------------------------------------------------------------------------
+
+sturb w9, [sp]
+sturh wzr, [x12, #255]
+stur w16, [x0, #-256]
+stur x28, [x14, #1]
+ldurb w1, [x20, #255]
+ldurh w20, [x1, #255]
+ldur w12, [sp, #255]
+ldur xzr, [x12, #255]
+ldursb x9, [x7, #-256]
+ldursh x17, [x19, #-256]
+ldursw x20, [x15, #-256]
+prfum pldl2keep, [sp, #-256]
+ldursb w19, [x1, #-256]
+ldursh w15, [x21, #-256]
+stur b0, [sp, #1]
+stur h12, [x12, #-1]
+stur s15, [x0, #255]
+stur d31, [x5, #25]
+stur q9, [x5]
+ldur b3, [sp]
+ldur h5, [x4, #-256]
+ldur s7, [x12, #-1]
+ldur d11, [x19, #4]
+ldur q13, [x1, #2]
+
+#------------------------------------------------------------------------------
+# Load/store (immediate post-indexed)
+#------------------------------------------------------------------------------
+
+strb w9, [x2], #255
+strb w10, [x3], #1
+strb w10, [x3], #-256
+strh w9, [x2], #255
+strh w9, [x2], #1
+strh w10, [x3], #-256
+str w19, [sp], #255
+str w20, [x30], #1
+str w21, [x12], #-256
+str xzr, [x9], #255
+str x2, [x3], #1
+str x19, [x12], #-256
+ldrb w9, [x2], #255
+ldrb w10, [x3], #1
+ldrb w10, [x3], #-256
+ldrh w9, [x2], #255
+ldrh w9, [x2], #1
+ldrh w10, [x3], #-256
+ldr w19, [sp], #255
+ldr w20, [x30], #1
+ldr w21, [x12], #-256
+ldr xzr, [x9], #255
+ldr x2, [x3], #1
+ldr x19, [x12], #-256
+ldrsb xzr, [x9], #255
+ldrsb x2, [x3], #1
+ldrsb x19, [x12], #-256
+ldrsh xzr, [x9], #255
+ldrsh x2, [x3], #1
+ldrsh x19, [x12], #-256
+ldrsw xzr, [x9], #255
+ldrsw x2, [x3], #1
+ldrsw x19, [x12], #-256
+ldrsb wzr, [x9], #255
+ldrsb w2, [x3], #1
+ldrsb w19, [x12], #-256
+ldrsh wzr, [x9], #255
+ldrsh w2, [x3], #1
+ldrsh w19, [x12], #-256
+str b0, [x0], #255
+str b3, [x3], #1
+str b5, [sp], #-256
+str h10, [x10], #255
+str h13, [x23], #1
+str h15, [sp], #-256
+str s20, [x20], #255
+str s23, [x23], #1
+str s25, [x0], #-256
+str d20, [x20], #255
+str d23, [x23], #1
+str d25, [x0], #-256
+ldr b0, [x0], #255
+ldr b3, [x3], #1
+ldr b5, [sp], #-256
+ldr h10, [x10], #255
+ldr h13, [x23], #1
+ldr h15, [sp], #-256
+ldr s20, [x20], #255
+ldr s23, [x23], #1
+ldr s25, [x0], #-256
+ldr d20, [x20], #255
+ldr d23, [x23], #1
+ldr d25, [x0], #-256
+ldr q20, [x1], #255
+ldr q23, [x9], #1
+ldr q25, [x20], #-256
+str q10, [x1], #255
+str q22, [sp], #1
+str q21, [x20], #-256
+
+#-------------------------------------------------------------------------------
+# Load-store register (immediate pre-indexed)
+#-------------------------------------------------------------------------------
+
+ldr x3, [x4, #0]!
+strb w9, [x2, #255]!
+strb w10, [x3, #1]!
+strb w10, [x3, #-256]!
+strh w9, [x2, #255]!
+strh w9, [x2, #1]!
+strh w10, [x3, #-256]!
+str w19, [sp, #255]!
+str w20, [x30, #1]!
+str w21, [x12, #-256]!
+str xzr, [x9, #255]!
+str x2, [x3, #1]!
+str x19, [x12, #-256]!
+ldrb w9, [x2, #255]!
+ldrb w10, [x3, #1]!
+ldrb w10, [x3, #-256]!
+ldrh w9, [x2, #255]!
+ldrh w9, [x2, #1]!
+ldrh w10, [x3, #-256]!
+ldr w19, [sp, #255]!
+ldr w20, [x30, #1]!
+ldr w21, [x12, #-256]!
+ldr xzr, [x9, #255]!
+ldr x2, [x3, #1]!
+ldr x19, [x12, #-256]!
+ldrsb xzr, [x9, #255]!
+ldrsb x2, [x3, #1]!
+ldrsb x19, [x12, #-256]!
+ldrsh xzr, [x9, #255]!
+ldrsh x2, [x3, #1]!
+ldrsh x19, [x12, #-256]!
+ldrsw xzr, [x9, #255]!
+ldrsw x2, [x3, #1]!
+ldrsw x19, [x12, #-256]!
+ldrsb wzr, [x9, #255]!
+ldrsb w2, [x3, #1]!
+ldrsb w19, [x12, #-256]!
+ldrsh wzr, [x9, #255]!
+ldrsh w2, [x3, #1]!
+ldrsh w19, [x12, #-256]!
+str b0, [x0, #255]!
+str b3, [x3, #1]!
+str b5, [sp, #-256]!
+str h10, [x10, #255]!
+str h13, [x23, #1]!
+str h15, [sp, #-256]!
+str s20, [x20, #255]!
+str s23, [x23, #1]!
+str s25, [x0, #-256]!
+str d20, [x20, #255]!
+str d23, [x23, #1]!
+str d25, [x0, #-256]!
+ldr b0, [x0, #255]!
+ldr b3, [x3, #1]!
+ldr b5, [sp, #-256]!
+ldr h10, [x10, #255]!
+ldr h13, [x23, #1]!
+ldr h15, [sp, #-256]!
+ldr s20, [x20, #255]!
+ldr s23, [x23, #1]!
+ldr s25, [x0, #-256]!
+ldr d20, [x20, #255]!
+ldr d23, [x23, #1]!
+ldr d25, [x0, #-256]!
+ldr q20, [x1, #255]!
+ldr q23, [x9, #1]!
+ldr q25, [x20, #-256]!
+str q10, [x1, #255]!
+str q22, [sp, #1]!
+str q21, [x20, #-256]!
+
+#------------------------------------------------------------------------------
+# Load/store (unprivileged)
+#------------------------------------------------------------------------------
+
+sttrb w9, [sp]
+sttrh wzr, [x12, #255]
+sttr w16, [x0, #-256]
+sttr x28, [x14, #1]
+ldtrb w1, [x20, #255]
+ldtrh w20, [x1, #255]
+ldtr w12, [sp, #255]
+ldtr xzr, [x12, #255]
+ldtrsb x9, [x7, #-256]
+ldtrsh x17, [x19, #-256]
+ldtrsw x20, [x15, #-256]
+ldtrsb w19, [x1, #-256]
+ldtrsh w15, [x21, #-256]
+
+#------------------------------------------------------------------------------
+# Load/store (unsigned immediate)
+#------------------------------------------------------------------------------
+
+ldr x4, [x29]
+ldr x30, [x12, #32760]
+ldr x20, [sp, #8]
+ldr xzr, [sp]
+ldr w2, [sp]
+ldr w17, [sp, #16380]
+ldr w13, [x2, #4]
+ldrsw x2, [x5, #4]
+ldrsw x23, [sp, #16380]
+ldrh w2, [x4]
+ldrsh w23, [x6, #8190]
+ldrsh wzr, [sp, #2]
+ldrsh x29, [x2, #2]
+ldrb w26, [x3, #121]
+ldrb w12, [x2]
+ldrsb w27, [sp, #4095]
+ldrsb xzr, [x15]
+str x30, [sp]
+str w20, [x4, #16380]
+strh w17, [sp, #8190]
+strb w23, [x3, #4095]
+strb wzr, [x2]
+ldr b31, [sp, #4095]
+ldr h20, [x2, #8190]
+ldr s10, [x19, #16380]
+ldr d3, [x10, #32760]
+str q12, [sp, #65520]
+
+#------------------------------------------------------------------------------
+# Load/store (register offset)
+#------------------------------------------------------------------------------
+
+ldrb w3, [sp, x5]
+ldrb w9, [x27, x6]
+ldrsb w10, [x30, x7]
+ldrb w11, [x29, x3, sxtx]
+strb w12, [x28, xzr, sxtx]
+ldrb w14, [x26, w6, uxtw]
+ldrsb w15, [x25, w7, uxtw]
+ldrb w17, [x23, w9, sxtw]
+ldrsb x18, [x22, w10, sxtw]
+ldrsh w3, [sp, x5]
+ldrsh w9, [x27, x6]
+ldrh w10, [x30, x7, lsl #1]
+strh w11, [x29, x3, sxtx]
+ldrh w12, [x28, xzr, sxtx]
+ldrsh x13, [x27, x5, sxtx #1]
+ldrh w14, [x26, w6, uxtw]
+ldrh w15, [x25, w7, uxtw]
+ldrsh w16, [x24, w8, uxtw #1]
+ldrh w17, [x23, w9, sxtw]
+ldrh w18, [x22, w10, sxtw]
+strh w19, [x21, wzr, sxtw #1]
+ldr w3, [sp, x5]
+ldr s9, [x27, x6]
+ldr w10, [x30, x7, lsl #2]
+ldr w11, [x29, x3, sxtx]
+str s12, [x28, xzr, sxtx]
+str w13, [x27, x5, sxtx #2]
+str w14, [x26, w6, uxtw]
+ldr w15, [x25, w7, uxtw]
+ldr w16, [x24, w8, uxtw #2]
+ldrsw x17, [x23, w9, sxtw]
+ldr w18, [x22, w10, sxtw]
+ldrsw x19, [x21, wzr, sxtw #2]
+ldr x3, [sp, x5]
+str x9, [x27, x6]
+ldr d10, [x30, x7, lsl #3]
+str x11, [x29, x3, sxtx]
+ldr x12, [x28, xzr, sxtx]
+ldr x13, [x27, x5, sxtx #3]
+prfm pldl1keep, [x26, w6, uxtw]
+ldr x15, [x25, w7, uxtw]
+ldr x16, [x24, w8, uxtw #3]
+ldr x17, [x23, w9, sxtw]
+ldr x18, [x22, w10, sxtw]
+str d19, [x21, wzr, sxtw #3]
+ldr q3, [sp, x5]
+ldr q9, [x27, x6]
+ldr q10, [x30, x7, lsl #4]
+str q11, [x29, x3, sxtx]
+str q12, [x28, xzr, sxtx]
+str q13, [x27, x5, sxtx #4]
+ldr q14, [x26, w6, uxtw]
+ldr q15, [x25, w7, uxtw]
+ldr q16, [x24, w8, uxtw #4]
+ldr q17, [x23, w9, sxtw]
+str q18, [x22, w10, sxtw]
+ldr q19, [x21, wzr, sxtw #4]
+
+#------------------------------------------------------------------------------
+# Load/store register pair (offset)
+#------------------------------------------------------------------------------
+
+ldp w3, w5, [sp]
+stp wzr, w9, [sp, #252]
+ldp w2, wzr, [sp, #-256]
+ldp w9, w10, [sp, #4]
+ldpsw x9, x10, [sp, #4]
+ldpsw x9, x10, [x2, #-256]
+ldpsw x20, x30, [sp, #252]
+ldp x21, x29, [x2, #504]
+ldp x22, x23, [x3, #-512]
+ldp x24, x25, [x4, #8]
+ldp s29, s28, [sp, #252]
+stp s27, s26, [sp, #-256]
+ldp s1, s2, [x3, #44]
+stp d3, d5, [x9, #504]
+stp d7, d11, [x10, #-512]
+ldp d2, d3, [x30, #-8]
+stp q3, q5, [sp]
+stp q17, q19, [sp, #1008]
+ldp q23, q29, [x1, #-1024]
+
+#------------------------------------------------------------------------------
+# Load/store register pair (post-indexed)
+#------------------------------------------------------------------------------
+
+ldp w3, w5, [sp], #0
+stp wzr, w9, [sp], #252
+ldp w2, wzr, [sp], #-256
+ldp w9, w10, [sp], #4
+ldpsw x9, x10, [sp], #4
+ldpsw x9, x10, [x2], #-256
+ldpsw x20, x30, [sp], #252
+ldp x21, x29, [x2], #504
+ldp x22, x23, [x3], #-512
+ldp x24, x25, [x4], #8
+ldp s29, s28, [sp], #252
+stp s27, s26, [sp], #-256
+ldp s1, s2, [x3], #44
+stp d3, d5, [x9], #504
+stp d7, d11, [x10], #-512
+ldp d2, d3, [x30], #-8
+stp q3, q5, [sp], #0
+stp q17, q19, [sp], #1008
+ldp q23, q29, [x1], #-1024
+
+#------------------------------------------------------------------------------
+# Load/store register pair (pre-indexed)
+#------------------------------------------------------------------------------
+
+ldp w3, w5, [sp, #0]!
+stp wzr, w9, [sp, #252]!
+ldp w2, wzr, [sp, #-256]!
+ldp w9, w10, [sp, #4]!
+ldpsw x9, x10, [sp, #4]!
+ldpsw x9, x10, [x2, #-256]!
+ldpsw x20, x30, [sp, #252]!
+ldp x21, x29, [x2, #504]!
+ldp x22, x23, [x3, #-512]!
+ldp x24, x25, [x4, #8]!
+ldp s29, s28, [sp, #252]!
+stp s27, s26, [sp, #-256]!
+ldp s1, s2, [x3, #44]!
+stp d3, d5, [x9, #504]!
+stp d7, d11, [x10, #-512]!
+ldp d2, d3, [x30, #-8]!
+stp q3, q5, [sp, #0]!
+stp q17, q19, [sp, #1008]!
+ldp q23, q29, [x1, #-1024]!
+
+#------------------------------------------------------------------------------
+# Load/store register pair (offset)
+#------------------------------------------------------------------------------
+
+ldnp w3, w5, [sp]
+stnp wzr, w9, [sp, #252]
+ldnp w2, wzr, [sp, #-256]
+ldnp w9, w10, [sp, #4]
+ldnp x21, x29, [x2, #504]
+ldnp x22, x23, [x3, #-512]
+ldnp x24, x25, [x4, #8]
+ldnp s29, s28, [sp, #252]
+stnp s27, s26, [sp, #-256]
+ldnp s1, s2, [x3, #44]
+stnp d3, d5, [x9, #504]
+stnp d7, d11, [x10, #-512]
+ldnp d2, d3, [x30, #-8]
+stnp q3, q5, [sp]
+stnp q17, q19, [sp, #1008]
+ldnp q23, q29, [x1, #-1024]
+
+#------------------------------------------------------------------------------
+# Logical (immediate)
+#------------------------------------------------------------------------------
+
+mov w3, #983055
+mov x10, #-6148914691236517206
+
+#------------------------------------------------------------------------------
+# Logical (shifted register)
+#------------------------------------------------------------------------------
+
+and w12, w23, w21
+and w16, w15, w1, lsl #1
+and w9, w4, w10, lsl #31
+and w3, w30, w11
+and x3, x5, x7, lsl #63
+and x5, x14, x19, asr #4
+and w3, w17, w19, ror #31
+and w0, w2, wzr, lsr #17
+and w3, w30, w11, asr #2
+and xzr, x4, x26
+and w3, wzr, w20, ror #2
+and x7, x20, xzr, asr #63
+bic x13, x20, x14, lsl #47
+bic w2, w7, w9
+orr w2, w7, w0, asr #31
+orr x8, x9, x10, lsl #12
+orn x3, x5, x7, asr #2
+orn w2, w5, w29
+ands w7, wzr, w9, lsl #1
+ands x3, x5, x20, ror #63
+bics w3, w5, w7
+bics x3, xzr, x3, lsl #1
+tst w3, w7, lsl #31
+tst x2, x20, asr #2
+mov x3, x6
+mov x3, xzr
+mov wzr, w2
+mov w3, w5
+
+#------------------------------------------------------------------------------
+# Move wide (immediate)
+#------------------------------------------------------------------------------
+
+movz w2, #0, lsl #16
+mov w2, #-1235
+mov x2, #5299989643264
+mov x2, #0
+movk w3, #0
+movz x4, #0, lsl #16
+movk w5, #0, lsl #16
+movz x6, #0, lsl #32
+movk x7, #0, lsl #32
+movz x8, #0, lsl #48
+movk x9, #0, lsl #48
+
+#------------------------------------------------------------------------------
+# PC-relative addressing
+#------------------------------------------------------------------------------
+
+adr x2, #1600
+adrp x21, #6553600
+adr x0, #262144
+
+#------------------------------------------------------------------------------
+# Test and branch (immediate)
+#------------------------------------------------------------------------------
+
+tbz x12, #62, #0
+tbz x12, #62, #4
+tbz x12, #62, #-32768
+tbnz x12, #60, #32764
+
+#------------------------------------------------------------------------------
+# Unconditional branch (immediate)
+#------------------------------------------------------------------------------
+
+b #4
+b #-4
+b #134217724
+
+#------------------------------------------------------------------------------
+# Unconditional branch (register)
+#------------------------------------------------------------------------------
+
+br x20
+blr xzr
+ret x10
+ret
+eret
+drps
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 add w2, w3, #4095
+# CHECK-NEXT: 1 1 0.25 add w30, w29, #1, lsl #12
+# CHECK-NEXT: 1 1 0.25 add w13, w5, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.25 add x5, x7, #1638
+# CHECK-NEXT: 1 1 0.25 add w20, wsp, #801
+# CHECK-NEXT: 1 1 0.25 add wsp, wsp, #1104
+# CHECK-NEXT: 1 1 0.25 add wsp, w30, #4084
+# CHECK-NEXT: 1 1 0.25 add x0, x24, #291
+# CHECK-NEXT: 1 1 0.25 add x3, x24, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.25 add x8, sp, #1074
+# CHECK-NEXT: 1 1 0.25 add sp, x29, #3816
+# CHECK-NEXT: 1 1 0.25 sub w0, wsp, #4077
+# CHECK-NEXT: 1 1 0.25 sub w4, w20, #546, lsl #12
+# CHECK-NEXT: 1 1 0.25 sub sp, sp, #288
+# CHECK-NEXT: 1 1 0.25 sub wsp, w19, #16
+# CHECK-NEXT: 1 1 0.50 adds w13, w23, #291, lsl #12
+# CHECK-NEXT: 1 1 0.50 cmn w2, #4095
+# CHECK-NEXT: 1 1 0.50 adds w20, wsp, #0
+# CHECK-NEXT: 1 1 0.50 cmn x3, #1, lsl #12
+# CHECK-NEXT: 1 1 0.50 cmp sp, #20, lsl #12
+# CHECK-NEXT: 1 1 0.50 cmp x30, #4095
+# CHECK-NEXT: 1 1 0.50 subs x4, sp, #3822
+# CHECK-NEXT: 1 1 0.50 cmn w3, #291, lsl #12
+# CHECK-NEXT: 1 1 0.50 cmn wsp, #1365
+# CHECK-NEXT: 1 1 0.50 cmn sp, #1092, lsl #12
+# CHECK-NEXT: 1 1 0.25 mov sp, x30
+# CHECK-NEXT: 1 1 0.25 mov wsp, w20
+# CHECK-NEXT: 1 1 0.25 mov x11, sp
+# CHECK-NEXT: 1 1 0.25 mov w24, wsp
+# CHECK-NEXT: 1 1 0.25 add w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 add wzr, w3, w5
+# CHECK-NEXT: 1 1 0.25 add w20, wzr, w4
+# CHECK-NEXT: 1 1 0.25 add w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 add w11, w13, w15
+# CHECK-NEXT: 2 2 0.50 add w9, w3, wzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 add w17, w29, w20, lsl #31
+# CHECK-NEXT: 2 2 0.50 add w21, w22, w23, lsr #0
+# CHECK-NEXT: 2 2 0.50 add w24, w25, w26, lsr #18
+# CHECK-NEXT: 2 2 0.50 add w27, w28, w29, lsr #31
+# CHECK-NEXT: 2 2 0.50 add w2, w3, w4, asr #0
+# CHECK-NEXT: 2 2 0.50 add w5, w6, w7, asr #21
+# CHECK-NEXT: 2 2 0.50 add w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 add x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 add xzr, x3, x5
+# CHECK-NEXT: 1 1 0.25 add x20, xzr, x4
+# CHECK-NEXT: 1 1 0.25 add x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 add x11, x13, x15
+# CHECK-NEXT: 2 2 0.50 add x9, x3, xzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 add x17, x29, x20, lsl #63
+# CHECK-NEXT: 2 2 0.50 add x21, x22, x23, lsr #0
+# CHECK-NEXT: 2 2 0.50 add x24, x25, x26, lsr #18
+# CHECK-NEXT: 2 2 0.50 add x27, x28, x29, lsr #63
+# CHECK-NEXT: 2 2 0.50 add x2, x3, x4, asr #0
+# CHECK-NEXT: 2 2 0.50 add x5, x6, x7, asr #21
+# CHECK-NEXT: 2 2 0.50 add x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 adds w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 cmn w3, w5
+# CHECK-NEXT: 1 1 0.25 adds w20, wzr, w4
+# CHECK-NEXT: 1 1 0.25 adds w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 adds w11, w13, w15
+# CHECK-NEXT: 2 2 0.50 adds w9, w3, wzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 adds w17, w29, w20, lsl #31
+# CHECK-NEXT: 2 2 0.50 adds w21, w22, w23, lsr #0
+# CHECK-NEXT: 2 2 0.50 adds w24, w25, w26, lsr #18
+# CHECK-NEXT: 2 2 0.50 adds w27, w28, w29, lsr #31
+# CHECK-NEXT: 2 2 0.50 adds w2, w3, w4, asr #0
+# CHECK-NEXT: 2 2 0.50 adds w5, w6, w7, asr #21
+# CHECK-NEXT: 2 2 0.50 adds w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 adds x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 cmn x3, x5
+# CHECK-NEXT: 1 1 0.25 adds x20, xzr, x4
+# CHECK-NEXT: 1 1 0.25 adds x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 adds x11, x13, x15
+# CHECK-NEXT: 2 2 0.50 adds x9, x3, xzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 adds x17, x29, x20, lsl #63
+# CHECK-NEXT: 2 2 0.50 adds x21, x22, x23, lsr #0
+# CHECK-NEXT: 2 2 0.50 adds x24, x25, x26, lsr #18
+# CHECK-NEXT: 2 2 0.50 adds x27, x28, x29, lsr #63
+# CHECK-NEXT: 2 2 0.50 adds x2, x3, x4, asr #0
+# CHECK-NEXT: 2 2 0.50 adds x5, x6, x7, asr #21
+# CHECK-NEXT: 2 2 0.50 adds x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 sub w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 sub wzr, w3, w5
+# CHECK-NEXT: 1 1 0.25 sub w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 sub w11, w13, w15
+# CHECK-NEXT: 2 2 0.50 sub w9, w3, wzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 sub w17, w29, w20, lsl #31
+# CHECK-NEXT: 2 2 0.50 sub w21, w22, w23, lsr #0
+# CHECK-NEXT: 2 2 0.50 sub w24, w25, w26, lsr #18
+# CHECK-NEXT: 2 2 0.50 sub w27, w28, w29, lsr #31
+# CHECK-NEXT: 2 2 0.50 sub w2, w3, w4, asr #0
+# CHECK-NEXT: 2 2 0.50 sub w5, w6, w7, asr #21
+# CHECK-NEXT: 2 2 0.50 sub w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 sub x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 sub xzr, x3, x5
+# CHECK-NEXT: 1 1 0.25 sub x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 sub x11, x13, x15
+# CHECK-NEXT: 2 2 0.50 sub x9, x3, xzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 sub x17, x29, x20, lsl #63
+# CHECK-NEXT: 2 2 0.50 sub x21, x22, x23, lsr #0
+# CHECK-NEXT: 2 2 0.50 sub x24, x25, x26, lsr #18
+# CHECK-NEXT: 2 2 0.50 sub x27, x28, x29, lsr #63
+# CHECK-NEXT: 2 2 0.50 sub x2, x3, x4, asr #0
+# CHECK-NEXT: 2 2 0.50 sub x5, x6, x7, asr #21
+# CHECK-NEXT: 2 2 0.50 sub x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 subs w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 cmp w3, w5
+# CHECK-NEXT: 1 1 0.25 subs w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 subs w11, w13, w15
+# CHECK-NEXT: 2 2 0.50 subs w9, w3, wzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 subs w17, w29, w20, lsl #31
+# CHECK-NEXT: 2 2 0.50 subs w21, w22, w23, lsr #0
+# CHECK-NEXT: 2 2 0.50 subs w24, w25, w26, lsr #18
+# CHECK-NEXT: 2 2 0.50 subs w27, w28, w29, lsr #31
+# CHECK-NEXT: 2 2 0.50 subs w2, w3, w4, asr #0
+# CHECK-NEXT: 2 2 0.50 subs w5, w6, w7, asr #21
+# CHECK-NEXT: 2 2 0.50 subs w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 subs x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 cmp x3, x5
+# CHECK-NEXT: 1 1 0.25 subs x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 subs x11, x13, x15
+# CHECK-NEXT: 2 2 0.50 subs x9, x3, xzr, lsl #10
+# CHECK-NEXT: 2 2 0.50 subs x17, x29, x20, lsl #63
+# CHECK-NEXT: 2 2 0.50 subs x21, x22, x23, lsr #0
+# CHECK-NEXT: 2 2 0.50 subs x24, x25, x26, lsr #18
+# CHECK-NEXT: 2 2 0.50 subs x27, x28, x29, lsr #63
+# CHECK-NEXT: 2 2 0.50 subs x2, x3, x4, asr #0
+# CHECK-NEXT: 2 2 0.50 subs x5, x6, x7, asr #21
+# CHECK-NEXT: 2 2 0.50 subs x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 cmn wzr, w4
+# CHECK-NEXT: 1 1 0.25 cmn w5, wzr
+# CHECK-NEXT: 1 1 0.25 cmn w6, w7
+# CHECK-NEXT: 2 2 0.50 cmn w8, w9, lsl #15
+# CHECK-NEXT: 2 2 0.50 cmn w10, w11, lsl #31
+# CHECK-NEXT: 2 2 0.50 cmn w12, w13, lsr #0
+# CHECK-NEXT: 2 2 0.50 cmn w14, w15, lsr #21
+# CHECK-NEXT: 2 2 0.50 cmn w16, w17, lsr #31
+# CHECK-NEXT: 2 2 0.50 cmn w18, w19, asr #0
+# CHECK-NEXT: 2 2 0.50 cmn w20, w21, asr #22
+# CHECK-NEXT: 2 2 0.50 cmn w22, w23, asr #31
+# CHECK-NEXT: 1 1 0.25 cmn x0, x3
+# CHECK-NEXT: 1 1 0.25 cmn xzr, x4
+# CHECK-NEXT: 1 1 0.25 cmn x5, xzr
+# CHECK-NEXT: 1 1 0.25 cmn x6, x7
+# CHECK-NEXT: 2 2 0.50 cmn x8, x9, lsl #15
+# CHECK-NEXT: 2 2 0.50 cmn x10, x11, lsl #63
+# CHECK-NEXT: 2 2 0.50 cmn x12, x13, lsr #0
+# CHECK-NEXT: 2 2 0.50 cmn x14, x15, lsr #41
+# CHECK-NEXT: 2 2 0.50 cmn x16, x17, lsr #63
+# CHECK-NEXT: 2 2 0.50 cmn x18, x19, asr #0
+# CHECK-NEXT: 2 2 0.50 cmn x20, x21, asr #55
+# CHECK-NEXT: 2 2 0.50 cmn x22, x23, asr #63
+# CHECK-NEXT: 1 1 0.25 cmp w0, w3
+# CHECK-NEXT: 1 1 0.25 cmp wzr, w4
+# CHECK-NEXT: 1 1 0.25 cmp w5, wzr
+# CHECK-NEXT: 1 1 0.25 cmp w6, w7
+# CHECK-NEXT: 2 2 0.50 cmp w8, w9, lsl #15
+# CHECK-NEXT: 2 2 0.50 cmp w10, w11, lsl #31
+# CHECK-NEXT: 2 2 0.50 cmp w12, w13, lsr #0
+# CHECK-NEXT: 2 2 0.50 cmp w14, w15, lsr #21
+# CHECK-NEXT: 2 2 0.50 cmp w18, w19, asr #0
+# CHECK-NEXT: 2 2 0.50 cmp w20, w21, asr #22
+# CHECK-NEXT: 2 2 0.50 cmp w22, w23, asr #31
+# CHECK-NEXT: 1 1 0.25 cmp x0, x3
+# CHECK-NEXT: 1 1 0.25 cmp xzr, x4
+# CHECK-NEXT: 1 1 0.25 cmp x5, xzr
+# CHECK-NEXT: 1 1 0.25 cmp x6, x7
+# CHECK-NEXT: 2 2 0.50 cmp x8, x9, lsl #15
+# CHECK-NEXT: 2 2 0.50 cmp x10, x11, lsl #63
+# CHECK-NEXT: 2 2 0.50 cmp x12, x13, lsr #0
+# CHECK-NEXT: 2 2 0.50 cmp x14, x15, lsr #41
+# CHECK-NEXT: 2 2 0.50 cmp x16, x17, lsr #63
+# CHECK-NEXT: 2 2 0.50 cmp x18, x19, asr #0
+# CHECK-NEXT: 2 2 0.50 cmp x20, x21, asr #55
+# CHECK-NEXT: 2 2 0.50 cmp x22, x23, asr #63
+# CHECK-NEXT: 1 1 0.25 cmp wzr, w0
+# CHECK-NEXT: 1 1 0.25 cmp xzr, x0
+# CHECK-NEXT: 1 1 0.50 adc w29, w27, w25
+# CHECK-NEXT: 1 1 0.50 adc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.50 adc w9, wzr, w10
+# CHECK-NEXT: 1 1 0.50 adc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.50 adc x29, x27, x25
+# CHECK-NEXT: 1 1 0.50 adc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.50 adc x9, xzr, x10
+# CHECK-NEXT: 1 1 0.50 adc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.50 adcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.50 adcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.50 adcs w9, wzr, w10
+# CHECK-NEXT: 1 1 0.50 adcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.50 adcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.50 adcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.50 adcs x9, xzr, x10
+# CHECK-NEXT: 1 1 0.50 adcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.50 sbc w29, w27, w25
+# CHECK-NEXT: 1 1 0.50 sbc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.50 ngc w9, w10
+# CHECK-NEXT: 1 1 0.50 sbc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.50 sbc x29, x27, x25
+# CHECK-NEXT: 1 1 0.50 sbc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.50 ngc x9, x10
+# CHECK-NEXT: 1 1 0.50 sbc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.50 sbcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.50 sbcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.50 ngcs w9, w10
+# CHECK-NEXT: 1 1 0.50 sbcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.50 sbcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.50 sbcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.50 ngcs x9, x10
+# CHECK-NEXT: 1 1 0.50 sbcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.50 ngc w3, w12
+# CHECK-NEXT: 1 1 0.50 ngc wzr, w9
+# CHECK-NEXT: 1 1 0.50 ngc w23, wzr
+# CHECK-NEXT: 1 1 0.50 ngc x29, x30
+# CHECK-NEXT: 1 1 0.50 ngc xzr, x0
+# CHECK-NEXT: 1 1 0.50 ngc x0, xzr
+# CHECK-NEXT: 1 1 0.50 ngcs w3, w12
+# CHECK-NEXT: 1 1 0.50 ngcs wzr, w9
+# CHECK-NEXT: 1 1 0.50 ngcs w23, wzr
+# CHECK-NEXT: 1 1 0.50 ngcs x29, x30
+# CHECK-NEXT: 1 1 0.50 ngcs xzr, x0
+# CHECK-NEXT: 1 1 0.50 ngcs x0, xzr
+# CHECK-NEXT: 1 1 0.50 sbfx x1, x2, #3, #2
+# CHECK-NEXT: 1 1 0.50 asr x3, x4, #63
+# CHECK-NEXT: 1 1 0.50 asr wzr, wzr, #31
+# CHECK-NEXT: 1 1 0.50 sbfx w12, w9, #0, #1
+# CHECK-NEXT: 1 1 0.50 ubfiz x4, x5, #52, #11
+# CHECK-NEXT: 1 1 0.50 ubfx xzr, x4, #0, #1
+# CHECK-NEXT: 1 1 0.50 ubfiz x4, xzr, #1, #6
+# CHECK-NEXT: 1 1 0.50 lsr x5, x6, #12
+# CHECK-NEXT: 1 1 0.50 bfi x4, x5, #52, #11
+# CHECK-NEXT: 1 1 0.50 bfxil xzr, x4, #0, #1
+# CHECK-NEXT: 1 1 0.50 bfc x4, #1, #6
+# CHECK-NEXT: 1 1 0.50 bfxil x5, x6, #12, #52
+# CHECK-NEXT: 1 1 0.50 sxtb w1, w2
+# CHECK-NEXT: 1 1 0.50 sxtb xzr, w3
+# CHECK-NEXT: 1 1 0.50 sxth w9, w10
+# CHECK-NEXT: 1 1 0.50 sxth x0, w1
+# CHECK-NEXT: 1 1 0.50 sxtw x3, w30
+# CHECK-NEXT: 1 1 0.50 uxtb w1, w2
+# CHECK-NEXT: 1 1 0.50 uxth w9, w10
+# CHECK-NEXT: 1 1 0.50 ubfx x3, x30, #0, #32
+# CHECK-NEXT: 1 1 0.50 asr w3, w2, #0
+# CHECK-NEXT: 1 1 0.50 asr w9, w10, #31
+# CHECK-NEXT: 1 1 0.50 asr x20, x21, #63
+# CHECK-NEXT: 1 1 0.50 asr w1, wzr, #3
+# CHECK-NEXT: 1 1 0.50 lsr w3, w2, #0
+# CHECK-NEXT: 1 1 0.50 lsr w9, w10, #31
+# CHECK-NEXT: 1 1 0.50 lsr x20, x21, #63
+# CHECK-NEXT: 1 1 0.50 lsr wzr, wzr, #3
+# CHECK-NEXT: 1 1 0.50 lsr w3, w2, #0
+# CHECK-NEXT: 1 1 0.50 lsl w9, w10, #31
+# CHECK-NEXT: 1 1 0.50 lsl x20, x21, #63
+# CHECK-NEXT: 1 1 0.50 lsl w1, wzr, #3
+# CHECK-NEXT: 1 1 0.50 sbfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 sbfiz x2, x3, #63, #1
+# CHECK-NEXT: 1 1 0.50 asr x19, x20, #0
+# CHECK-NEXT: 1 1 0.50 sbfiz x9, x10, #5, #59
+# CHECK-NEXT: 1 1 0.50 asr w9, w10, #0
+# CHECK-NEXT: 1 1 0.50 sbfiz w11, w12, #31, #1
+# CHECK-NEXT: 1 1 0.50 sbfiz w13, w14, #29, #3
+# CHECK-NEXT: 1 1 0.50 sbfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 sbfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 asr x2, x3, #63
+# CHECK-NEXT: 1 1 0.50 asr x19, x20, #0
+# CHECK-NEXT: 1 1 0.50 asr x9, x10, #5
+# CHECK-NEXT: 1 1 0.50 asr w9, w10, #0
+# CHECK-NEXT: 1 1 0.50 asr w11, w12, #31
+# CHECK-NEXT: 1 1 0.50 asr w13, w14, #29
+# CHECK-NEXT: 1 1 0.50 sbfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 bfxil w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 bfi x2, x3, #63, #1
+# CHECK-NEXT: 1 1 0.50 bfxil x19, x20, #0, #64
+# CHECK-NEXT: 1 1 0.50 bfi x9, x10, #5, #59
+# CHECK-NEXT: 1 1 0.50 bfxil w9, w10, #0, #32
+# CHECK-NEXT: 1 1 0.50 bfi w11, w12, #31, #1
+# CHECK-NEXT: 1 1 0.50 bfi w13, w14, #29, #3
+# CHECK-NEXT: 1 1 0.50 bfc xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 bfxil w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 bfxil x2, x3, #63, #1
+# CHECK-NEXT: 1 1 0.50 bfxil x19, x20, #0, #64
+# CHECK-NEXT: 1 1 0.50 bfxil x9, x10, #5, #59
+# CHECK-NEXT: 1 1 0.50 bfxil w9, w10, #0, #32
+# CHECK-NEXT: 1 1 0.50 bfxil w11, w12, #31, #1
+# CHECK-NEXT: 1 1 0.50 bfxil w13, w14, #29, #3
+# CHECK-NEXT: 1 1 0.50 bfxil xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 ubfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 lsl x2, x3, #63
+# CHECK-NEXT: 1 1 0.50 lsr x19, x20, #0
+# CHECK-NEXT: 1 1 0.50 lsl x9, x10, #5
+# CHECK-NEXT: 1 1 0.50 lsr w9, w10, #0
+# CHECK-NEXT: 1 1 0.50 lsl w11, w12, #31
+# CHECK-NEXT: 1 1 0.50 lsl w13, w14, #29
+# CHECK-NEXT: 1 1 0.50 ubfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 ubfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.50 lsr x2, x3, #63
+# CHECK-NEXT: 1 1 0.50 lsr x19, x20, #0
+# CHECK-NEXT: 1 1 0.50 lsr x9, x10, #5
+# CHECK-NEXT: 1 1 0.50 lsr w9, w10, #0
+# CHECK-NEXT: 1 1 0.50 lsr w11, w12, #31
+# CHECK-NEXT: 1 1 0.50 lsr w13, w14, #29
+# CHECK-NEXT: 1 1 0.50 ubfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.50 cbz w5, #4
+# CHECK-NEXT: 1 1 0.50 cbz x5, #0
+# CHECK-NEXT: 1 1 0.50 cbnz x2, #-4
+# CHECK-NEXT: 1 1 0.50 cbnz x26, #1048572
+# CHECK-NEXT: 1 1 0.50 cbz wzr, #0
+# CHECK-NEXT: 1 1 0.50 cbnz xzr, #0
+# CHECK-NEXT: 1 1 0.50 b.ne #4
+# CHECK-NEXT: 1 1 0.50 b.ge #1048572
+# CHECK-NEXT: 1 1 0.50 b.ge #-4
+# CHECK-NEXT: 1 1 0.50 ccmp w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.50 ccmp w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.50 ccmp wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.50 ccmp x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.50 ccmp x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.50 ccmp xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.50 ccmn w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.50 ccmn w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.50 ccmn wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.50 ccmn x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.50 ccmn x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.50 ccmn xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.50 ccmp w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.50 ccmp w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.50 ccmp wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.50 ccmp x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.50 ccmp x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.50 ccmp xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.50 ccmn w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.50 ccmn w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.50 ccmn wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.50 ccmn x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.50 ccmn x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.50 ccmn xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.50 csel w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.50 csel wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.50 csel w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.50 csel w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.50 csel x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.50 csel xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.50 csel x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.50 csel x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.50 csinc w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.50 csinc wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.50 csinc w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.50 csinc w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.50 csinc x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.50 csinc xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.50 csinc x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.50 csinc x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.50 csinv w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.50 csinv wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.50 csinv w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.50 csinv w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.50 csinv x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.50 csinv xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.50 csinv x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.50 csinv x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.50 csneg w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.50 csneg wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.50 csneg w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.50 csneg w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.50 csneg x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.50 csneg xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.50 csneg x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.50 csneg x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.50 cset w3, eq
+# CHECK-NEXT: 1 1 0.50 cset x9, pl
+# CHECK-NEXT: 1 1 0.50 csetm w20, ne
+# CHECK-NEXT: 1 1 0.50 csetm x30, ge
+# CHECK-NEXT: 1 1 0.50 csinc w2, wzr, wzr, al
+# CHECK-NEXT: 1 1 0.50 csinv x3, xzr, xzr, nv
+# CHECK-NEXT: 1 1 0.50 cinc w3, w5, gt
+# CHECK-NEXT: 1 1 0.50 cinc wzr, w4, le
+# CHECK-NEXT: 1 1 0.50 cset w9, lt
+# CHECK-NEXT: 1 1 0.50 cinc x3, x5, gt
+# CHECK-NEXT: 1 1 0.50 cinc xzr, x4, le
+# CHECK-NEXT: 1 1 0.50 cset x9, lt
+# CHECK-NEXT: 1 1 0.50 csinc w5, w6, w6, nv
+# CHECK-NEXT: 1 1 0.50 csinc x1, x2, x2, al
+# CHECK-NEXT: 1 1 0.50 cinv w3, w5, gt
+# CHECK-NEXT: 1 1 0.50 cinv wzr, w4, le
+# CHECK-NEXT: 1 1 0.50 csetm w9, lt
+# CHECK-NEXT: 1 1 0.50 cinv x3, x5, gt
+# CHECK-NEXT: 1 1 0.50 cinv xzr, x4, le
+# CHECK-NEXT: 1 1 0.50 csetm x9, lt
+# CHECK-NEXT: 1 1 0.50 csinv x1, x0, x0, al
+# CHECK-NEXT: 1 1 0.50 csinv w9, w8, w8, nv
+# CHECK-NEXT: 1 1 0.50 cneg w3, w5, gt
+# CHECK-NEXT: 1 1 0.50 cneg wzr, w4, le
+# CHECK-NEXT: 1 1 0.50 cneg w9, wzr, lt
+# CHECK-NEXT: 1 1 0.50 cneg x3, x5, gt
+# CHECK-NEXT: 1 1 0.50 cneg xzr, x4, le
+# CHECK-NEXT: 1 1 0.50 cneg x9, xzr, lt
+# CHECK-NEXT: 1 1 0.50 csneg x4, x8, x8, al
+# CHECK-NEXT: 1 1 0.50 csinv w9, w8, w8, nv
+# CHECK-NEXT: 1 1 0.50 rbit w0, w7
+# CHECK-NEXT: 1 1 0.50 rbit x18, x3
+# CHECK-NEXT: 1 1 0.50 rev16 w17, w1
+# CHECK-NEXT: 1 1 0.50 rev16 x5, x2
+# CHECK-NEXT: 1 1 0.50 rev w18, w0
+# CHECK-NEXT: 1 1 0.50 rev32 x20, x1
+# CHECK-NEXT: 1 1 0.50 rev x22, x2
+# CHECK-NEXT: 1 1 0.25 clz w24, w3
+# CHECK-NEXT: 1 1 0.25 clz x26, x4
+# CHECK-NEXT: 1 1 0.50 cls w3, w5
+# CHECK-NEXT: 1 1 0.50 cls x20, x5
+# CHECK-NEXT: 2 13 1.00 udiv w0, w7, w10
+# CHECK-NEXT: 3 13 2.00 udiv x9, x22, x4
+# CHECK-NEXT: 2 13 1.00 sdiv w12, w21, w0
+# CHECK-NEXT: 3 13 2.00 sdiv x13, x2, x1
+# CHECK-NEXT: 1 1 0.50 lsl w11, w12, w13
+# CHECK-NEXT: 1 1 0.50 lsl x14, x15, x16
+# CHECK-NEXT: 1 1 0.50 lsr w17, w18, w19
+# CHECK-NEXT: 1 1 0.50 lsr x20, x21, x22
+# CHECK-NEXT: 1 1 0.50 asr w23, w24, w25
+# CHECK-NEXT: 1 1 0.50 asr x26, x27, x28
+# CHECK-NEXT: 1 1 0.50 ror w0, w1, w2
+# CHECK-NEXT: 1 1 0.50 ror x3, x4, x5
+# CHECK-NEXT: 1 1 0.50 lsl w6, w7, w8
+# CHECK-NEXT: 1 1 0.50 lsl x9, x10, x11
+# CHECK-NEXT: 1 1 0.50 lsr w12, w13, w14
+# CHECK-NEXT: 1 1 0.50 lsr x15, x16, x17
+# CHECK-NEXT: 1 1 0.50 asr w18, w19, w20
+# CHECK-NEXT: 1 1 0.50 asr x21, x22, x23
+# CHECK-NEXT: 1 1 0.50 ror w24, w25, w26
+# CHECK-NEXT: 1 1 0.50 ror x27, x28, x29
+# CHECK-NEXT: 1 3 1.00 smulh x30, x29, x28
+# CHECK-NEXT: 1 3 1.00 smulh xzr, x27, x26
+# CHECK-NEXT: 1 3 1.00 umulh x30, x29, x28
+# CHECK-NEXT: 1 3 1.00 umulh x23, x30, xzr
+# CHECK-NEXT: 1 3 1.00 madd w1, w3, w7, w4
+# CHECK-NEXT: 1 3 1.00 madd wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 1.00 madd w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 1.00 madd w19, w30, wzr, w29
+# CHECK-NEXT: 1 3 1.00 mul w4, w5, w6
+# CHECK-NEXT: 1 3 1.00 madd x1, x3, x7, x4
+# CHECK-NEXT: 1 3 1.00 madd xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 1.00 madd x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 1.00 madd x19, x30, xzr, x29
+# CHECK-NEXT: 1 3 1.00 mul x4, x5, x6
+# CHECK-NEXT: 1 3 1.00 msub w1, w3, w7, w4
+# CHECK-NEXT: 1 3 1.00 msub wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 1.00 msub w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 1.00 msub w19, w30, wzr, w29
+# CHECK-NEXT: 1 3 1.00 mneg w4, w5, w6
+# CHECK-NEXT: 1 3 1.00 msub x1, x3, x7, x4
+# CHECK-NEXT: 1 3 1.00 msub xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 1.00 msub x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 1.00 msub x19, x30, xzr, x29
+# CHECK-NEXT: 1 3 1.00 mneg x4, x5, x6
+# CHECK-NEXT: 2 4 1.00 smaddl x3, w5, w2, x9
+# CHECK-NEXT: 2 4 1.00 smaddl xzr, w10, w11, x12
+# CHECK-NEXT: 2 4 1.00 smaddl x13, wzr, w14, x15
+# CHECK-NEXT: 2 4 1.00 smaddl x16, w17, wzr, x18
+# CHECK-NEXT: 2 4 1.00 smull x19, w20, w21
+# CHECK-NEXT: 2 4 1.00 smsubl x3, w5, w2, x9
+# CHECK-NEXT: 2 4 1.00 smsubl xzr, w10, w11, x12
+# CHECK-NEXT: 2 4 1.00 smsubl x13, wzr, w14, x15
+# CHECK-NEXT: 2 4 1.00 smsubl x16, w17, wzr, x18
+# CHECK-NEXT: 2 4 1.00 smnegl x19, w20, w21
+# CHECK-NEXT: 2 4 1.00 umaddl x3, w5, w2, x9
+# CHECK-NEXT: 2 4 1.00 umaddl xzr, w10, w11, x12
+# CHECK-NEXT: 2 4 1.00 umaddl x13, wzr, w14, x15
+# CHECK-NEXT: 2 4 1.00 umaddl x16, w17, wzr, x18
+# CHECK-NEXT: 2 4 1.00 umull x19, w20, w21
+# CHECK-NEXT: 2 4 1.00 umsubl x3, w5, w2, x9
+# CHECK-NEXT: 2 4 1.00 umsubl x16, w17, wzr, x18
+# CHECK-NEXT: 2 4 1.00 umnegl x19, w20, w21
+# CHECK-NEXT: 1 3 1.00 smulh x30, x29, x28
+# CHECK-NEXT: 1 3 1.00 smulh x23, x22, xzr
+# CHECK-NEXT: 1 3 1.00 umulh x23, x22, xzr
+# CHECK-NEXT: 1 3 1.00 mul x19, x20, xzr
+# CHECK-NEXT: 1 3 1.00 mneg w21, w22, w23
+# CHECK-NEXT: 2 4 1.00 smull x11, w13, w17
+# CHECK-NEXT: 2 4 1.00 umull x11, w13, w17
+# CHECK-NEXT: 2 4 1.00 smnegl x11, w13, w17
+# CHECK-NEXT: 2 4 1.00 umnegl x11, w13, w17
+# CHECK-NEXT: 1 1 0.50 extr w3, w5, w7, #0
+# CHECK-NEXT: 1 1 0.50 extr w11, w13, w17, #31
+# CHECK-NEXT: 1 1 0.50 extr x3, x5, x7, #15
+# CHECK-NEXT: 1 1 0.50 extr x11, x13, x17, #63
+# CHECK-NEXT: 1 1 0.50 ror x19, x23, #24
+# CHECK-NEXT: 1 1 0.50 ror x29, xzr, #63
+# CHECK-NEXT: 1 1 0.50 ror w9, w13, #31
+# CHECK-NEXT: 1 3 1.00 fcmp s3, s5
+# CHECK-NEXT: 1 3 1.00 fcmp s31, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmp s31, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmpe s29, s30
+# CHECK-NEXT: 1 3 1.00 fcmpe s15, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmpe s15, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmp d4, d12
+# CHECK-NEXT: 1 3 1.00 fcmp d23, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmp d23, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmpe d26, d22
+# CHECK-NEXT: 1 3 1.00 fcmpe d29, #0.0
+# CHECK-NEXT: 1 3 1.00 fcmpe d29, #0.0
+# CHECK-NEXT: 3 9 1.00 fccmp s1, s31, #0, eq
+# CHECK-NEXT: 3 9 1.00 fccmp s3, s0, #15, hs
+# CHECK-NEXT: 3 9 1.00 fccmp s31, s15, #13, hs
+# CHECK-NEXT: 3 9 1.00 fccmp d9, d31, #0, le
+# CHECK-NEXT: 3 9 1.00 fccmp d3, d0, #15, gt
+# CHECK-NEXT: 3 9 1.00 fccmp d31, d5, #7, ne
+# CHECK-NEXT: 3 9 1.00 fccmpe s1, s31, #0, eq
+# CHECK-NEXT: 3 9 1.00 fccmpe s3, s0, #15, hs
+# CHECK-NEXT: 3 9 1.00 fccmpe s31, s15, #13, hs
+# CHECK-NEXT: 3 9 1.00 fccmpe d9, d31, #0, le
+# CHECK-NEXT: 3 9 1.00 fccmpe d3, d0, #15, gt
+# CHECK-NEXT: 3 9 1.00 fccmpe d31, d5, #7, ne
+# CHECK-NEXT: 3 9 1.00 fcsel s3, s20, s9, pl
+# CHECK-NEXT: 3 9 1.00 fcsel d9, d10, d11, mi
+# CHECK-NEXT: 1 2 0.50 fmov s0, s1
+# CHECK-NEXT: 1 2 0.50 fabs s2, s3
+# CHECK-NEXT: 1 2 0.50 fneg s4, s5
+# CHECK-NEXT: 1 33 1.00 fsqrt s6, s7
+# CHECK-NEXT: 1 3 0.50 fcvt d8, s9
+# CHECK-NEXT: 1 3 0.50 fcvt h10, s11
+# CHECK-NEXT: 1 2 0.50 frintn s12, s13
+# CHECK-NEXT: 1 2 0.50 frintp s14, s15
+# CHECK-NEXT: 1 2 0.50 frintm s16, s17
+# CHECK-NEXT: 1 2 0.50 frintz s18, s19
+# CHECK-NEXT: 1 2 0.50 frinta s20, s21
+# CHECK-NEXT: 1 2 0.50 frintx s22, s23
+# CHECK-NEXT: 1 2 0.50 frinti s24, s25
+# CHECK-NEXT: 1 2 0.50 fmov d0, d1
+# CHECK-NEXT: 1 2 0.50 fabs d2, d3
+# CHECK-NEXT: 1 2 0.50 fneg d4, d5
+# CHECK-NEXT: 1 63 1.00 fsqrt d6, d7
+# CHECK-NEXT: 1 3 0.50 fcvt s8, d9
+# CHECK-NEXT: 1 3 0.50 fcvt h10, d11
+# CHECK-NEXT: 1 2 0.50 frintn d12, d13
+# CHECK-NEXT: 1 2 0.50 frintp d14, d15
+# CHECK-NEXT: 1 2 0.50 frintm d16, d17
+# CHECK-NEXT: 1 2 0.50 frintz d18, d19
+# CHECK-NEXT: 1 2 0.50 frinta d20, d21
+# CHECK-NEXT: 1 2 0.50 frintx d22, d23
+# CHECK-NEXT: 1 2 0.50 frinti d24, d25
+# CHECK-NEXT: 1 3 0.50 fcvt s26, h27
+# CHECK-NEXT: 1 3 0.50 fcvt d28, h29
+# CHECK-NEXT: 1 4 0.50 fmul s20, s19, s17
+# CHECK-NEXT: 1 12 1.00 fdiv s1, s2, s3
+# CHECK-NEXT: 1 2 0.50 fadd s4, s5, s6
+# CHECK-NEXT: 1 2 0.50 fsub s7, s8, s9
+# CHECK-NEXT: 1 2 0.50 fmax s10, s11, s12
+# CHECK-NEXT: 1 2 0.50 fmin s13, s14, s15
+# CHECK-NEXT: 1 2 0.50 fmaxnm s16, s17, s18
+# CHECK-NEXT: 1 2 0.50 fminnm s19, s20, s21
+# CHECK-NEXT: 1 4 0.50 fnmul s22, s23, s2
+# CHECK-NEXT: 1 4 0.50 fmul d20, d19, d17
+# CHECK-NEXT: 1 19 1.00 fdiv d1, d2, d3
+# CHECK-NEXT: 1 2 0.50 fadd d4, d5, d6
+# CHECK-NEXT: 1 2 0.50 fsub d7, d8, d9
+# CHECK-NEXT: 1 2 0.50 fmax d10, d11, d12
+# CHECK-NEXT: 1 2 0.50 fmin d13, d14, d15
+# CHECK-NEXT: 1 2 0.50 fmaxnm d16, d17, d18
+# CHECK-NEXT: 1 2 0.50 fminnm d19, d20, d21
+# CHECK-NEXT: 1 4 0.50 fnmul d22, d23, d24
+# CHECK-NEXT: 1 4 0.50 fmadd s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.50 fmadd d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.50 fmsub s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.50 fmsub d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.50 fnmadd s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.50 fnmadd d3, d13, d0, d23
+# CHECK-NEXT: 1 4 0.50 fnmsub s3, s5, s6, s31
+# CHECK-NEXT: 1 4 0.50 fnmsub d3, d13, d0, d23
+# CHECK-NEXT: 2 7 1.00 fcvtzs w3, h5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs wzr, h20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzs w19, h0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzs x3, h5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, h30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzs x19, h0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtzs w3, s5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs wzr, s20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzs w19, s0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzs x3, s5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, s30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzs x19, s0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtzs w3, d5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs wzr, d20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzs w19, d0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzs x3, d5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, d30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzs x19, d0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtzu w3, h5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu wzr, h20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w19, h0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzu x3, h5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu x12, h30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzu x19, h0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtzu w3, s5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu wzr, s20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w19, s0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzu x3, s5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu x12, s30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzu x19, s0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtzu w3, d5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu wzr, d20, #13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w19, d0, #32
+# CHECK-NEXT: 2 7 1.00 fcvtzu x3, d5, #1
+# CHECK-NEXT: 2 7 1.00 fcvtzu x12, d30, #45
+# CHECK-NEXT: 2 7 1.00 fcvtzu x19, d0, #64
+# CHECK-NEXT: 3 11 1.00 scvtf h23, w19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf h31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf h14, w0, #32
+# CHECK-NEXT: 3 11 1.00 scvtf h23, x19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf h31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf h14, x0, #64
+# CHECK-NEXT: 3 11 1.00 scvtf s23, w19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf s31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf s14, w0, #32
+# CHECK-NEXT: 3 11 1.00 scvtf s23, x19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf s31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf s14, x0, #64
+# CHECK-NEXT: 3 11 1.00 scvtf d23, w19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf d31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf d14, w0, #32
+# CHECK-NEXT: 3 11 1.00 scvtf d23, x19, #1
+# CHECK-NEXT: 3 11 1.00 scvtf d31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 scvtf d14, x0, #64
+# CHECK-NEXT: 3 11 1.00 ucvtf h23, w19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf h31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf h14, w0, #32
+# CHECK-NEXT: 3 11 1.00 ucvtf h23, x19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf h31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf h14, x0, #64
+# CHECK-NEXT: 3 11 1.00 ucvtf s23, w19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf s31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf s14, w0, #32
+# CHECK-NEXT: 3 11 1.00 ucvtf s23, x19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf s31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf s14, x0, #64
+# CHECK-NEXT: 3 11 1.00 ucvtf d23, w19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf d31, wzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf d14, w0, #32
+# CHECK-NEXT: 3 11 1.00 ucvtf d23, x19, #1
+# CHECK-NEXT: 3 11 1.00 ucvtf d31, xzr, #20
+# CHECK-NEXT: 3 11 1.00 ucvtf d14, x0, #64
+# CHECK-NEXT: 2 7 1.00 fcvtns w3, h31
+# CHECK-NEXT: 2 7 1.00 fcvtns xzr, h12
+# CHECK-NEXT: 2 7 1.00 fcvtnu wzr, h12
+# CHECK-NEXT: 2 7 1.00 fcvtnu x0, h0
+# CHECK-NEXT: 2 7 1.00 fcvtps wzr, h9
+# CHECK-NEXT: 2 7 1.00 fcvtps x12, h20
+# CHECK-NEXT: 2 7 1.00 fcvtpu w30, h23
+# CHECK-NEXT: 2 7 1.00 fcvtpu x29, h3
+# CHECK-NEXT: 2 7 1.00 fcvtms w2, h3
+# CHECK-NEXT: 2 7 1.00 fcvtms x4, h5
+# CHECK-NEXT: 2 7 1.00 fcvtmu w6, h7
+# CHECK-NEXT: 2 7 1.00 fcvtmu x8, h9
+# CHECK-NEXT: 2 7 1.00 fcvtzs w10, h11
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, h13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w14, h15
+# CHECK-NEXT: 2 7 1.00 fcvtzu x15, h16
+# CHECK-NEXT: 3 11 1.00 scvtf h17, w18
+# CHECK-NEXT: 3 11 1.00 scvtf h19, x20
+# CHECK-NEXT: 3 11 1.00 ucvtf h21, w22
+# CHECK-NEXT: 3 11 1.00 scvtf h23, x24
+# CHECK-NEXT: 2 7 1.00 fcvtas w25, h26
+# CHECK-NEXT: 2 7 1.00 fcvtas x27, h28
+# CHECK-NEXT: 2 7 1.00 fcvtau w29, h30
+# CHECK-NEXT: 2 7 1.00 fcvtau xzr, h0
+# CHECK-NEXT: 2 7 1.00 fcvtns w3, s31
+# CHECK-NEXT: 2 7 1.00 fcvtns xzr, s12
+# CHECK-NEXT: 2 7 1.00 fcvtnu wzr, s12
+# CHECK-NEXT: 2 7 1.00 fcvtnu x0, s0
+# CHECK-NEXT: 2 7 1.00 fcvtps wzr, s9
+# CHECK-NEXT: 2 7 1.00 fcvtps x12, s20
+# CHECK-NEXT: 2 7 1.00 fcvtpu w30, s23
+# CHECK-NEXT: 2 7 1.00 fcvtpu x29, s3
+# CHECK-NEXT: 2 7 1.00 fcvtms w2, s3
+# CHECK-NEXT: 2 7 1.00 fcvtms x4, s5
+# CHECK-NEXT: 2 7 1.00 fcvtmu w6, s7
+# CHECK-NEXT: 2 7 1.00 fcvtmu x8, s9
+# CHECK-NEXT: 2 7 1.00 fcvtzs w10, s11
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, s13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w14, s15
+# CHECK-NEXT: 2 7 1.00 fcvtzu x15, s16
+# CHECK-NEXT: 3 11 1.00 scvtf s17, w18
+# CHECK-NEXT: 3 11 1.00 scvtf s19, x20
+# CHECK-NEXT: 3 11 1.00 ucvtf s21, w22
+# CHECK-NEXT: 3 11 1.00 scvtf s23, x24
+# CHECK-NEXT: 2 7 1.00 fcvtas w25, s26
+# CHECK-NEXT: 2 7 1.00 fcvtas x27, s28
+# CHECK-NEXT: 2 7 1.00 fcvtau w29, s30
+# CHECK-NEXT: 2 7 1.00 fcvtau xzr, s0
+# CHECK-NEXT: 2 7 1.00 fcvtns w3, d31
+# CHECK-NEXT: 2 7 1.00 fcvtns xzr, d12
+# CHECK-NEXT: 2 7 1.00 fcvtnu wzr, d12
+# CHECK-NEXT: 2 7 1.00 fcvtnu x0, d0
+# CHECK-NEXT: 2 7 1.00 fcvtps wzr, d9
+# CHECK-NEXT: 2 7 1.00 fcvtps x12, d20
+# CHECK-NEXT: 2 7 1.00 fcvtpu w30, d23
+# CHECK-NEXT: 2 7 1.00 fcvtpu x29, d3
+# CHECK-NEXT: 2 7 1.00 fcvtms w2, d3
+# CHECK-NEXT: 2 7 1.00 fcvtms x4, d5
+# CHECK-NEXT: 2 7 1.00 fcvtmu w6, d7
+# CHECK-NEXT: 2 7 1.00 fcvtmu x8, d9
+# CHECK-NEXT: 2 7 1.00 fcvtzs w10, d11
+# CHECK-NEXT: 2 7 1.00 fcvtzs x12, d13
+# CHECK-NEXT: 2 7 1.00 fcvtzu w14, d15
+# CHECK-NEXT: 2 7 1.00 fcvtzu x15, d16
+# CHECK-NEXT: 3 11 1.00 scvtf d17, w18
+# CHECK-NEXT: 3 11 1.00 scvtf d19, x20
+# CHECK-NEXT: 3 11 1.00 ucvtf d21, w22
+# CHECK-NEXT: 3 11 1.00 ucvtf d23, x24
+# CHECK-NEXT: 2 7 1.00 fcvtas w25, d26
+# CHECK-NEXT: 2 7 1.00 fcvtas x27, d28
+# CHECK-NEXT: 2 7 1.00 fcvtau w29, d30
+# CHECK-NEXT: 2 7 1.00 fcvtau xzr, d0
+# CHECK-NEXT: 1 5 1.00 fmov w3, s9
+# CHECK-NEXT: 1 3 1.00 fmov s9, w3
+# CHECK-NEXT: 1 5 1.00 fmov x20, d31
+# CHECK-NEXT: 1 3 1.00 fmov d1, x15
+# CHECK-NEXT: 2 7 1.00 fmov x3, v12.d[1]
+# CHECK-NEXT: 1 5 1.00 fmov v1.d[1], x19
+# CHECK-NEXT: 1 2 0.50 fmov s2, #0.12500000
+# CHECK-NEXT: 1 2 0.50 fmov s3, #1.00000000
+# CHECK-NEXT: 1 2 0.50 fmov d30, #16.00000000
+# CHECK-NEXT: 1 2 0.50 fmov s4, #1.06250000
+# CHECK-NEXT: 1 2 0.50 fmov d10, #1.93750000
+# CHECK-NEXT: 1 2 0.50 fmov s12, #-1.00000000
+# CHECK-NEXT: 1 2 0.50 fmov d16, #8.50000000
+# CHECK-NEXT: 1 3 0.50 * ldr w3, #0
+# CHECK-NEXT: 1 3 0.50 * ldr x29, #4
+# CHECK-NEXT: 1 3 0.50 * ldrsw xzr, #-4
+# CHECK-NEXT: 1 3 0.50 * ldr s0, #8
+# CHECK-NEXT: 1 3 0.50 * ldr d0, #1048572
+# CHECK-NEXT: 1 3 0.50 * ldr q0, #-1048576
+# CHECK-NEXT: 1 1 0.50 U prfm pldl1strm, #0
+# CHECK-NEXT: 1 1 0.50 U prfm #22, #0
+# CHECK-NEXT: 2 4 0.50 * * U stxrb w18, w8, [sp]
+# CHECK-NEXT: 2 4 0.50 * * U stxrh w24, w15, [x16]
+# CHECK-NEXT: 2 4 0.50 * * U stxr w5, w6, [x17]
+# CHECK-NEXT: 2 4 0.50 * * U stxr w1, x10, [x21]
+# CHECK-NEXT: 1 3 0.50 * * U ldxrb w30, [x0]
+# CHECK-NEXT: 1 3 0.50 * * U ldxrh w17, [x4]
+# CHECK-NEXT: 1 3 0.50 * * U ldxr w22, [sp]
+# CHECK-NEXT: 1 3 0.50 * * U ldxr x11, [x29]
+# CHECK-NEXT: 1 3 0.50 * * U ldxr x11, [x29]
+# CHECK-NEXT: 1 3 0.50 * * U ldxr x11, [x29]
+# CHECK-NEXT: 2 4 0.50 * * U stxp w12, w11, w10, [sp]
+# CHECK-NEXT: 2 4 0.50 * * U stxp wzr, x27, x9, [x12]
+# CHECK-NEXT: 2 3 0.50 * * U ldxp w0, wzr, [sp]
+# CHECK-NEXT: 2 3 0.50 * * U ldxp x17, x0, [x18]
+# CHECK-NEXT: 2 3 0.50 * * U ldxp x17, x0, [x18]
+# CHECK-NEXT: 2 4 0.50 * * U stlxrb w12, w22, [x0]
+# CHECK-NEXT: 2 4 0.50 * * U stlxrh w10, w1, [x1]
+# CHECK-NEXT: 2 4 0.50 * * U stlxr w9, w2, [x2]
+# CHECK-NEXT: 2 4 0.50 * * U stlxr w9, x3, [sp]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxrb w8, [x4]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxrh w7, [x5]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxr w6, [sp]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxr x5, [x6]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxr x5, [x6]
+# CHECK-NEXT: 1 3 0.50 * * U ldaxr x5, [x6]
+# CHECK-NEXT: 2 4 0.50 * * U stlxp w4, w5, w6, [sp]
+# CHECK-NEXT: 2 4 0.50 * * U stlxp wzr, x6, x7, [x1]
+# CHECK-NEXT: 2 3 0.50 * * U ldaxp w5, w18, [sp]
+# CHECK-NEXT: 2 3 0.50 * * U ldaxp x6, x19, [x22]
+# CHECK-NEXT: 2 3 0.50 * * U ldaxp x6, x19, [x22]
+# CHECK-NEXT: 1 1 0.50 * U stlrb w24, [sp]
+# CHECK-NEXT: 1 1 0.50 * U stlrh w25, [x30]
+# CHECK-NEXT: 1 1 0.50 * U stlr w26, [x29]
+# CHECK-NEXT: 1 1 0.50 * U stlr x27, [x28]
+# CHECK-NEXT: 1 1 0.50 * U stlr x27, [x28]
+# CHECK-NEXT: 1 1 0.50 * U stlr x27, [x28]
+# CHECK-NEXT: 1 3 0.50 * U ldarb w23, [sp]
+# CHECK-NEXT: 1 3 0.50 * U ldarh w22, [x30]
+# CHECK-NEXT: 1 3 0.50 * U ldar wzr, [x29]
+# CHECK-NEXT: 1 3 0.50 * U ldar x21, [x28]
+# CHECK-NEXT: 1 3 0.50 * U ldar x21, [x28]
+# CHECK-NEXT: 1 3 0.50 * U ldar x21, [x28]
+# CHECK-NEXT: 1 1 0.50 * sturb w9, [sp]
+# CHECK-NEXT: 1 1 0.50 * sturh wzr, [x12, #255]
+# CHECK-NEXT: 1 1 0.50 * stur w16, [x0, #-256]
+# CHECK-NEXT: 1 1 0.50 * stur x28, [x14, #1]
+# CHECK-NEXT: 1 3 0.50 * ldurb w1, [x20, #255]
+# CHECK-NEXT: 1 3 0.50 * ldurh w20, [x1, #255]
+# CHECK-NEXT: 1 3 0.50 * ldur w12, [sp, #255]
+# CHECK-NEXT: 1 3 0.50 * ldur xzr, [x12, #255]
+# CHECK-NEXT: 1 3 0.50 * ldursb x9, [x7, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldursh x17, [x19, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldursw x20, [x15, #-256]
+# CHECK-NEXT: 1 1 0.50 U prfum pldl2keep, [sp, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldursb w19, [x1, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldursh w15, [x21, #-256]
+# CHECK-NEXT: 2 2 1.00 * stur b0, [sp, #1]
+# CHECK-NEXT: 2 2 1.00 * stur h12, [x12, #-1]
+# CHECK-NEXT: 2 2 1.00 * stur s15, [x0, #255]
+# CHECK-NEXT: 2 2 1.00 * stur d31, [x5, #25]
+# CHECK-NEXT: 2 2 1.00 * stur q9, [x5]
+# CHECK-NEXT: 1 4 0.50 * ldur b3, [sp]
+# CHECK-NEXT: 1 4 0.50 * ldur h5, [x4, #-256]
+# CHECK-NEXT: 1 4 0.50 * ldur s7, [x12, #-1]
+# CHECK-NEXT: 1 4 0.50 * ldur d11, [x19, #4]
+# CHECK-NEXT: 1 4 0.50 * ldur q13, [x1, #2]
+# CHECK-NEXT: 2 1 0.50 * strb w9, [x2], #255
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3], #1
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3], #-256
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2], #255
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2], #1
+# CHECK-NEXT: 2 1 0.50 * strh w10, [x3], #-256
+# CHECK-NEXT: 2 1 0.50 * str w19, [sp], #255
+# CHECK-NEXT: 2 1 0.50 * str w20, [x30], #1
+# CHECK-NEXT: 2 1 0.50 * str w21, [x12], #-256
+# CHECK-NEXT: 2 1 0.50 * str xzr, [x9], #255
+# CHECK-NEXT: 2 1 0.50 * str x2, [x3], #1
+# CHECK-NEXT: 2 1 0.50 * str x19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrb w9, [x2], #255
+# CHECK-NEXT: 2 3 0.50 * ldrb w10, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrb w10, [x3], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrh w9, [x2], #255
+# CHECK-NEXT: 2 3 0.50 * ldrh w9, [x2], #1
+# CHECK-NEXT: 2 3 0.50 * ldrh w10, [x3], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr w19, [sp], #255
+# CHECK-NEXT: 2 3 0.50 * ldr w20, [x30], #1
+# CHECK-NEXT: 2 3 0.50 * ldr w21, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr xzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldr x2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldr x19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrsb xzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldrsb x2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrsb x19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrsh xzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldrsh x2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrsh x19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrsw xzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldrsw x2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrsw x19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrsb wzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldrsb w2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrsb w19, [x12], #-256
+# CHECK-NEXT: 2 3 0.50 * ldrsh wzr, [x9], #255
+# CHECK-NEXT: 2 3 0.50 * ldrsh w2, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldrsh w19, [x12], #-256
+# CHECK-NEXT: 2 1 0.50 * str b0, [x0], #255
+# CHECK-NEXT: 2 1 0.50 * str b3, [x3], #1
+# CHECK-NEXT: 2 1 0.50 * str b5, [sp], #-256
+# CHECK-NEXT: 2 1 0.50 * str h10, [x10], #255
+# CHECK-NEXT: 2 1 0.50 * str h13, [x23], #1
+# CHECK-NEXT: 2 1 0.50 * str h15, [sp], #-256
+# CHECK-NEXT: 2 1 0.50 * str s20, [x20], #255
+# CHECK-NEXT: 2 1 0.50 * str s23, [x23], #1
+# CHECK-NEXT: 2 1 0.50 * str s25, [x0], #-256
+# CHECK-NEXT: 2 1 0.50 * str d20, [x20], #255
+# CHECK-NEXT: 2 1 0.50 * str d23, [x23], #1
+# CHECK-NEXT: 2 1 0.50 * str d25, [x0], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr b0, [x0], #255
+# CHECK-NEXT: 2 3 0.50 * ldr b3, [x3], #1
+# CHECK-NEXT: 2 3 0.50 * ldr b5, [sp], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr h10, [x10], #255
+# CHECK-NEXT: 2 3 0.50 * ldr h13, [x23], #1
+# CHECK-NEXT: 2 3 0.50 * ldr h15, [sp], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr s20, [x20], #255
+# CHECK-NEXT: 2 3 0.50 * ldr s23, [x23], #1
+# CHECK-NEXT: 2 3 0.50 * ldr s25, [x0], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr d20, [x20], #255
+# CHECK-NEXT: 2 3 0.50 * ldr d23, [x23], #1
+# CHECK-NEXT: 2 3 0.50 * ldr d25, [x0], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr q20, [x1], #255
+# CHECK-NEXT: 2 3 0.50 * ldr q23, [x9], #1
+# CHECK-NEXT: 2 3 0.50 * ldr q25, [x20], #-256
+# CHECK-NEXT: 2 1 0.50 * str q10, [x1], #255
+# CHECK-NEXT: 2 1 0.50 * str q22, [sp], #1
+# CHECK-NEXT: 2 1 0.50 * str q21, [x20], #-256
+# CHECK-NEXT: 2 3 0.50 * ldr x3, [x4, #0]!
+# CHECK-NEXT: 2 1 0.50 * strb w9, [x2, #255]!
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3, #1]!
+# CHECK-NEXT: 2 1 0.50 * strb w10, [x3, #-256]!
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2, #255]!
+# CHECK-NEXT: 2 1 0.50 * strh w9, [x2, #1]!
+# CHECK-NEXT: 2 1 0.50 * strh w10, [x3, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str w19, [sp, #255]!
+# CHECK-NEXT: 2 1 0.50 * str w20, [x30, #1]!
+# CHECK-NEXT: 2 1 0.50 * str w21, [x12, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str xzr, [x9, #255]!
+# CHECK-NEXT: 2 1 0.50 * str x2, [x3, #1]!
+# CHECK-NEXT: 2 1 0.50 * str x19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrb w9, [x2, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrb w10, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrb w10, [x3, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrh w9, [x2, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrh w9, [x2, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrh w10, [x3, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr w19, [sp, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr w20, [x30, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr w21, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr xzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr x2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr x19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb xzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb x2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb x19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh xzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh x2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh x19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrsw xzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrsw x2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrsw x19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb wzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb w2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrsb w19, [x12, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh wzr, [x9, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh w2, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldrsh w19, [x12, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str b0, [x0, #255]!
+# CHECK-NEXT: 2 1 0.50 * str b3, [x3, #1]!
+# CHECK-NEXT: 2 1 0.50 * str b5, [sp, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str h10, [x10, #255]!
+# CHECK-NEXT: 2 1 0.50 * str h13, [x23, #1]!
+# CHECK-NEXT: 2 1 0.50 * str h15, [sp, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str s20, [x20, #255]!
+# CHECK-NEXT: 2 1 0.50 * str s23, [x23, #1]!
+# CHECK-NEXT: 2 1 0.50 * str s25, [x0, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str d20, [x20, #255]!
+# CHECK-NEXT: 2 1 0.50 * str d23, [x23, #1]!
+# CHECK-NEXT: 2 1 0.50 * str d25, [x0, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr b0, [x0, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr b3, [x3, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr b5, [sp, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr h10, [x10, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr h13, [x23, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr h15, [sp, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr s20, [x20, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr s23, [x23, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr s25, [x0, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr d20, [x20, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr d23, [x23, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr d25, [x0, #-256]!
+# CHECK-NEXT: 2 3 0.50 * ldr q20, [x1, #255]!
+# CHECK-NEXT: 2 3 0.50 * ldr q23, [x9, #1]!
+# CHECK-NEXT: 2 3 0.50 * ldr q25, [x20, #-256]!
+# CHECK-NEXT: 2 1 0.50 * str q10, [x1, #255]!
+# CHECK-NEXT: 2 1 0.50 * str q22, [sp, #1]!
+# CHECK-NEXT: 2 1 0.50 * str q21, [x20, #-256]!
+# CHECK-NEXT: 1 1 0.50 * sttrb w9, [sp]
+# CHECK-NEXT: 1 1 0.50 * sttrh wzr, [x12, #255]
+# CHECK-NEXT: 1 1 0.50 * sttr w16, [x0, #-256]
+# CHECK-NEXT: 1 1 0.50 * sttr x28, [x14, #1]
+# CHECK-NEXT: 1 3 0.50 * ldtrb w1, [x20, #255]
+# CHECK-NEXT: 1 3 0.50 * ldtrh w20, [x1, #255]
+# CHECK-NEXT: 1 3 0.50 * ldtr w12, [sp, #255]
+# CHECK-NEXT: 1 3 0.50 * ldtr xzr, [x12, #255]
+# CHECK-NEXT: 1 3 0.50 * ldtrsb x9, [x7, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldtrsh x17, [x19, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldtrsw x20, [x15, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldtrsb w19, [x1, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldtrsh w15, [x21, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldr x4, [x29]
+# CHECK-NEXT: 1 3 0.50 * ldr x30, [x12, #32760]
+# CHECK-NEXT: 1 3 0.50 * ldr x20, [sp, #8]
+# CHECK-NEXT: 1 3 0.50 * ldr xzr, [sp]
+# CHECK-NEXT: 1 3 0.50 * ldr w2, [sp]
+# CHECK-NEXT: 1 3 0.50 * ldr w17, [sp, #16380]
+# CHECK-NEXT: 1 3 0.50 * ldr w13, [x2, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrsw x2, [x5, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrsw x23, [sp, #16380]
+# CHECK-NEXT: 1 3 0.50 * ldrh w2, [x4]
+# CHECK-NEXT: 1 3 0.50 * ldrsh w23, [x6, #8190]
+# CHECK-NEXT: 1 3 0.50 * ldrsh wzr, [sp, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh x29, [x2, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrb w26, [x3, #121]
+# CHECK-NEXT: 1 3 0.50 * ldrb w12, [x2]
+# CHECK-NEXT: 1 3 0.50 * ldrsb w27, [sp, #4095]
+# CHECK-NEXT: 1 3 0.50 * ldrsb xzr, [x15]
+# CHECK-NEXT: 1 1 0.50 * str x30, [sp]
+# CHECK-NEXT: 1 1 0.50 * str w20, [x4, #16380]
+# CHECK-NEXT: 1 1 0.50 * strh w17, [sp, #8190]
+# CHECK-NEXT: 1 1 0.50 * strb w23, [x3, #4095]
+# CHECK-NEXT: 1 1 0.50 * strb wzr, [x2]
+# CHECK-NEXT: 1 3 0.50 * ldr b31, [sp, #4095]
+# CHECK-NEXT: 1 3 0.50 * ldr h20, [x2, #8190]
+# CHECK-NEXT: 1 3 0.50 * ldr s10, [x19, #16380]
+# CHECK-NEXT: 1 3 0.50 * ldr d3, [x10, #32760]
+# CHECK-NEXT: 2 2 1.00 * str q12, [sp, #65520]
+# CHECK-NEXT: 1 3 0.50 * ldrb w3, [sp, x5]
+# CHECK-NEXT: 1 3 0.50 * ldrb w9, [x27, x6]
+# CHECK-NEXT: 1 3 0.50 * ldrsb w10, [x30, x7]
+# CHECK-NEXT: 1 3 0.50 * ldrb w11, [x29, x3, sxtx]
+# CHECK-NEXT: 2 1 1.00 * strb w12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 3 0.50 * ldrb w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrsb w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrb w17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrsb x18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrsh w3, [sp, x5]
+# CHECK-NEXT: 1 3 0.50 * ldrsh w9, [x27, x6]
+# CHECK-NEXT: 1 3 0.50 * ldrh w10, [x30, x7, lsl #1]
+# CHECK-NEXT: 2 1 1.00 * strh w11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 3 0.50 * ldrh w12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 3 0.50 * ldrsh x13, [x27, x5, sxtx #1]
+# CHECK-NEXT: 1 3 0.50 * ldrh w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrh w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrsh w16, [x24, w8, uxtw #1]
+# CHECK-NEXT: 1 3 0.50 * ldrh w17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrh w18, [x22, w10, sxtw]
+# CHECK-NEXT: 2 1 1.00 * strh w19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: 1 3 0.50 * ldr w3, [sp, x5]
+# CHECK-NEXT: 1 4 0.50 * ldr s9, [x27, x6]
+# CHECK-NEXT: 1 3 0.50 * ldr w10, [x30, x7, lsl #2]
+# CHECK-NEXT: 1 3 0.50 * ldr w11, [x29, x3, sxtx]
+# CHECK-NEXT: 2 2 1.00 * str s12, [x28, xzr, sxtx]
+# CHECK-NEXT: 2 1 1.00 * str w13, [x27, x5, sxtx #2]
+# CHECK-NEXT: 2 1 1.00 * str w14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr w15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr w16, [x24, w8, uxtw #2]
+# CHECK-NEXT: 1 3 0.50 * ldrsw x17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr w18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldrsw x19, [x21, wzr, sxtw #2]
+# CHECK-NEXT: 1 3 0.50 * ldr x3, [sp, x5]
+# CHECK-NEXT: 2 1 1.00 * str x9, [x27, x6]
+# CHECK-NEXT: 1 4 0.50 * ldr d10, [x30, x7, lsl #3]
+# CHECK-NEXT: 2 1 1.00 * str x11, [x29, x3, sxtx]
+# CHECK-NEXT: 1 3 0.50 * ldr x12, [x28, xzr, sxtx]
+# CHECK-NEXT: 1 3 0.50 * ldr x13, [x27, x5, sxtx #3]
+# CHECK-NEXT: 1 1 0.50 U prfm pldl1keep, [x26, w6, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr x15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr x16, [x24, w8, uxtw #3]
+# CHECK-NEXT: 1 3 0.50 * ldr x17, [x23, w9, sxtw]
+# CHECK-NEXT: 1 3 0.50 * ldr x18, [x22, w10, sxtw]
+# CHECK-NEXT: 2 2 1.00 * str d19, [x21, wzr, sxtw #3]
+# CHECK-NEXT: 1 4 0.50 * ldr q3, [sp, x5]
+# CHECK-NEXT: 1 4 0.50 * ldr q9, [x27, x6]
+# CHECK-NEXT: 1 4 0.50 * ldr q10, [x30, x7, lsl #4]
+# CHECK-NEXT: 2 2 1.00 * str q11, [x29, x3, sxtx]
+# CHECK-NEXT: 2 2 1.00 * str q12, [x28, xzr, sxtx]
+# CHECK-NEXT: 2 2 1.00 * str q13, [x27, x5, sxtx #4]
+# CHECK-NEXT: 1 4 0.50 * ldr q14, [x26, w6, uxtw]
+# CHECK-NEXT: 1 4 0.50 * ldr q15, [x25, w7, uxtw]
+# CHECK-NEXT: 1 4 0.50 * ldr q16, [x24, w8, uxtw #4]
+# CHECK-NEXT: 1 4 0.50 * ldr q17, [x23, w9, sxtw]
+# CHECK-NEXT: 2 2 1.00 * str q18, [x22, w10, sxtw]
+# CHECK-NEXT: 1 4 0.50 * ldr q19, [x21, wzr, sxtw #4]
+# CHECK-NEXT: 1 3 0.50 * ldp w3, w5, [sp]
+# CHECK-NEXT: 2 2 0.50 * stp wzr, w9, [sp, #252]
+# CHECK-NEXT: 1 3 0.50 * ldp w2, wzr, [sp, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldp w9, w10, [sp, #4]
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [sp, #4]
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [x2, #-256]
+# CHECK-NEXT: 2 5 1.00 * ldpsw x20, x30, [sp, #252]
+# CHECK-NEXT: 1 3 0.50 * ldp x21, x29, [x2, #504]
+# CHECK-NEXT: 1 3 0.50 * ldp x22, x23, [x3, #-512]
+# CHECK-NEXT: 1 3 0.50 * ldp x24, x25, [x4, #8]
+# CHECK-NEXT: 2 5 1.00 * ldp s29, s28, [sp, #252]
+# CHECK-NEXT: 4 3 2.00 * stp s27, s26, [sp, #-256]
+# CHECK-NEXT: 2 5 1.00 * ldp s1, s2, [x3, #44]
+# CHECK-NEXT: 4 3 2.00 * stp d3, d5, [x9, #504]
+# CHECK-NEXT: 4 3 2.00 * stp d7, d11, [x10, #-512]
+# CHECK-NEXT: 2 5 1.00 * ldp d2, d3, [x30, #-8]
+# CHECK-NEXT: 4 3 2.00 * stp q3, q5, [sp]
+# CHECK-NEXT: 4 3 2.00 * stp q17, q19, [sp, #1008]
+# CHECK-NEXT: 2 4 1.00 * ldp q23, q29, [x1, #-1024]
+# CHECK-NEXT: 1 3 0.50 * ldp w3, w5, [sp], #0
+# CHECK-NEXT: 3 2 0.50 * stp wzr, w9, [sp], #252
+# CHECK-NEXT: 1 3 0.50 * ldp w2, wzr, [sp], #-256
+# CHECK-NEXT: 1 3 0.50 * ldp w9, w10, [sp], #4
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [sp], #4
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [x2], #-256
+# CHECK-NEXT: 2 5 1.00 * ldpsw x20, x30, [sp], #252
+# CHECK-NEXT: 1 3 0.50 * ldp x21, x29, [x2], #504
+# CHECK-NEXT: 1 3 0.50 * ldp x22, x23, [x3], #-512
+# CHECK-NEXT: 1 3 0.50 * ldp x24, x25, [x4], #8
+# CHECK-NEXT: 2 5 1.00 * ldp s29, s28, [sp], #252
+# CHECK-NEXT: 4 3 2.00 * stp s27, s26, [sp], #-256
+# CHECK-NEXT: 2 5 1.00 * ldp s1, s2, [x3], #44
+# CHECK-NEXT: 4 3 2.00 * stp d3, d5, [x9], #504
+# CHECK-NEXT: 4 3 2.00 * stp d7, d11, [x10], #-512
+# CHECK-NEXT: 2 5 1.00 * ldp d2, d3, [x30], #-8
+# CHECK-NEXT: 4 3 2.00 * stp q3, q5, [sp], #0
+# CHECK-NEXT: 4 3 2.00 * stp q17, q19, [sp], #1008
+# CHECK-NEXT: 2 4 1.00 * ldp q23, q29, [x1], #-1024
+# CHECK-NEXT: 1 3 0.50 * ldp w3, w5, [sp, #0]!
+# CHECK-NEXT: 3 2 0.50 * stp wzr, w9, [sp, #252]!
+# CHECK-NEXT: 1 3 0.50 * ldp w2, wzr, [sp, #-256]!
+# CHECK-NEXT: 1 3 0.50 * ldp w9, w10, [sp, #4]!
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [sp, #4]!
+# CHECK-NEXT: 2 5 1.00 * ldpsw x9, x10, [x2, #-256]!
+# CHECK-NEXT: 2 5 1.00 * ldpsw x20, x30, [sp, #252]!
+# CHECK-NEXT: 1 3 0.50 * ldp x21, x29, [x2, #504]!
+# CHECK-NEXT: 1 3 0.50 * ldp x22, x23, [x3, #-512]!
+# CHECK-NEXT: 1 3 0.50 * ldp x24, x25, [x4, #8]!
+# CHECK-NEXT: 2 5 1.00 * ldp s29, s28, [sp, #252]!
+# CHECK-NEXT: 4 3 2.00 * stp s27, s26, [sp, #-256]!
+# CHECK-NEXT: 2 5 1.00 * ldp s1, s2, [x3, #44]!
+# CHECK-NEXT: 4 3 2.00 * stp d3, d5, [x9, #504]!
+# CHECK-NEXT: 4 3 2.00 * stp d7, d11, [x10, #-512]!
+# CHECK-NEXT: 2 5 1.00 * ldp d2, d3, [x30, #-8]!
+# CHECK-NEXT: 4 3 2.00 * stp q3, q5, [sp, #0]!
+# CHECK-NEXT: 4 3 2.00 * stp q17, q19, [sp, #1008]!
+# CHECK-NEXT: 2 4 1.00 * ldp q23, q29, [x1, #-1024]!
+# CHECK-NEXT: 1 3 0.50 * ldnp w3, w5, [sp]
+# CHECK-NEXT: 2 1 1.00 * stnp wzr, w9, [sp, #252]
+# CHECK-NEXT: 1 3 0.50 * ldnp w2, wzr, [sp, #-256]
+# CHECK-NEXT: 1 3 0.50 * ldnp w9, w10, [sp, #4]
+# CHECK-NEXT: 1 3 0.50 * ldnp x21, x29, [x2, #504]
+# CHECK-NEXT: 1 3 0.50 * ldnp x22, x23, [x3, #-512]
+# CHECK-NEXT: 1 3 0.50 * ldnp x24, x25, [x4, #8]
+# CHECK-NEXT: 2 5 1.00 * ldnp s29, s28, [sp, #252]
+# CHECK-NEXT: 4 3 2.00 * stnp s27, s26, [sp, #-256]
+# CHECK-NEXT: 2 5 1.00 * ldnp s1, s2, [x3, #44]
+# CHECK-NEXT: 4 3 2.00 * stnp d3, d5, [x9, #504]
+# CHECK-NEXT: 4 3 2.00 * stnp d7, d11, [x10, #-512]
+# CHECK-NEXT: 2 5 1.00 * ldnp d2, d3, [x30, #-8]
+# CHECK-NEXT: 4 3 2.00 * stnp q3, q5, [sp]
+# CHECK-NEXT: 4 3 2.00 * stnp q17, q19, [sp, #1008]
+# CHECK-NEXT: 2 4 1.00 * ldnp q23, q29, [x1, #-1024]
+# CHECK-NEXT: 1 1 0.25 mov w3, #983055
+# CHECK-NEXT: 1 1 0.25 mov x10, #-6148914691236517206
+# CHECK-NEXT: 1 1 0.25 and w12, w23, w21
+# CHECK-NEXT: 1 1 0.25 and w16, w15, w1, lsl #1
+# CHECK-NEXT: 2 2 0.50 and w9, w4, w10, lsl #31
+# CHECK-NEXT: 1 1 0.25 and w3, w30, w11
+# CHECK-NEXT: 2 2 0.50 and x3, x5, x7, lsl #63
+# CHECK-NEXT: 2 2 0.50 and x5, x14, x19, asr #4
+# CHECK-NEXT: 2 2 0.50 and w3, w17, w19, ror #31
+# CHECK-NEXT: 2 2 0.50 and w0, w2, wzr, lsr #17
+# CHECK-NEXT: 2 2 0.50 and w3, w30, w11, asr #2
+# CHECK-NEXT: 1 1 0.25 and xzr, x4, x26
+# CHECK-NEXT: 2 2 0.50 and w3, wzr, w20, ror #2
+# CHECK-NEXT: 2 2 0.50 and x7, x20, xzr, asr #63
+# CHECK-NEXT: 2 2 0.50 bic x13, x20, x14, lsl #47
+# CHECK-NEXT: 1 1 0.25 bic w2, w7, w9
+# CHECK-NEXT: 2 2 0.50 orr w2, w7, w0, asr #31
+# CHECK-NEXT: 2 2 0.50 orr x8, x9, x10, lsl #12
+# CHECK-NEXT: 2 2 0.50 orn x3, x5, x7, asr #2
+# CHECK-NEXT: 1 1 0.25 orn w2, w5, w29
+# CHECK-NEXT: 1 1 0.25 ands w7, wzr, w9, lsl #1
+# CHECK-NEXT: 2 2 0.50 ands x3, x5, x20, ror #63
+# CHECK-NEXT: 1 1 0.25 bics w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 bics x3, xzr, x3, lsl #1
+# CHECK-NEXT: 2 2 0.50 tst w3, w7, lsl #31
+# CHECK-NEXT: 2 2 0.50 tst x2, x20, asr #2
+# CHECK-NEXT: 1 1 0.25 mov x3, x6
+# CHECK-NEXT: 1 1 0.25 mov x3, xzr
+# CHECK-NEXT: 1 1 0.25 mov wzr, w2
+# CHECK-NEXT: 1 1 0.25 mov w3, w5
+# CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16
+# CHECK-NEXT: 1 1 0.25 mov w2, #-1235
+# CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264
+# CHECK-NEXT: 1 1 0.25 mov x2, #0
+# CHECK-NEXT: 1 1 0.25 movk w3, #0
+# CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16
+# CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16
+# CHECK-NEXT: 1 1 0.25 movz x6, #0, lsl #32
+# CHECK-NEXT: 1 1 0.25 movk x7, #0, lsl #32
+# CHECK-NEXT: 1 1 0.25 movz x8, #0, lsl #48
+# CHECK-NEXT: 1 1 0.25 movk x9, #0, lsl #48
+# CHECK-NEXT: 1 1 0.50 adr x2, #1600
+# CHECK-NEXT: 1 1 0.50 adrp x21, #6553600
+# CHECK-NEXT: 1 1 0.50 adr x0, #262144
+# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #0
+# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #4
+# CHECK-NEXT: 1 1 0.50 tbz x12, #62, #-32768
+# CHECK-NEXT: 1 1 0.50 tbnz x12, #60, #32764
+# CHECK-NEXT: 1 1 0.50 b #4
+# CHECK-NEXT: 1 1 0.50 b #-4
+# CHECK-NEXT: 1 1 0.50 b #134217724
+# CHECK-NEXT: 1 1 1.00 br x20
+# CHECK-NEXT: 2 1 1.00 blr xzr
+# CHECK-NEXT: 1 1 0.50 U ret x10
+# CHECK-NEXT: 1 1 0.50 U ret
+# CHECK-NEXT: 1 1 1.00 U eret
+# CHECK-NEXT: 1 1 1.00 U drps
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Ampere1BUnitA
+# CHECK-NEXT: [0.1] - Ampere1BUnitA
+# CHECK-NEXT: [1.0] - Ampere1BUnitB
+# CHECK-NEXT: [1.1] - Ampere1BUnitB
+# CHECK-NEXT: [2] - Ampere1BUnitBS
+# CHECK-NEXT: [3.0] - Ampere1BUnitL
+# CHECK-NEXT: [3.1] - Ampere1BUnitL
+# CHECK-NEXT: [4.0] - Ampere1BUnitS
+# CHECK-NEXT: [4.1] - Ampere1BUnitS
+# CHECK-NEXT: [5] - Ampere1BUnitX
+# CHECK-NEXT: [6] - Ampere1BUnitY
+# CHECK-NEXT: [7] - Ampere1BUnitZ
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
+# CHECK-NEXT: 190.00 190.00 211.00 211.00 143.00 130.50 130.50 83.00 83.00 159.00 126.00 150.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w2, w3, #4095
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w30, w29, #1, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w13, w5, #4095, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x5, x7, #1638
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w20, wsp, #801
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add wsp, wsp, #1104
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add wsp, w30, #4084
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x0, x24, #291
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x3, x24, #4095, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x8, sp, #1074
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add sp, x29, #3816
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub w0, wsp, #4077
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub w4, w20, #546, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub sp, sp, #288
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub wsp, w19, #16
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adds w13, w23, #291, lsl #12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmn w2, #4095
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adds w20, wsp, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmn x3, #1, lsl #12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmp sp, #20, lsl #12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmp x30, #4095
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - subs x4, sp, #3822
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmn w3, #291, lsl #12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmn wsp, #1365
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cmn sp, #1092, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov sp, x30
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov wsp, w20
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x11, sp
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov w24, wsp
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w3, w5, w7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add wzr, w3, w5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w20, wzr, w4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w4, w6, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add w11, w13, w15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w9, w3, wzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w17, w29, w20, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w21, w22, w23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w24, w25, w26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w27, w28, w29, lsr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w2, w3, w4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w5, w6, w7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add w8, w9, w10, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x3, x5, x7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add xzr, x3, x5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x20, xzr, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x4, x6, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - add x11, x13, x15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x9, x3, xzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x17, x29, x20, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x21, x22, x23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x24, x25, x26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x27, x28, x29, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x2, x3, x4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x5, x6, x7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - add x8, x9, x10, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds w3, w5, w7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn w3, w5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds w20, wzr, w4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds w4, w6, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds w11, w13, w15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w9, w3, wzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w17, w29, w20, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w21, w22, w23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w24, w25, w26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w27, w28, w29, lsr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w2, w3, w4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w5, w6, w7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds w8, w9, w10, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds x3, x5, x7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn x3, x5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds x20, xzr, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds x4, x6, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - adds x11, x13, x15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x9, x3, xzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x17, x29, x20, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x21, x22, x23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x24, x25, x26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x27, x28, x29, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x2, x3, x4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x5, x6, x7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - adds x8, x9, x10, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub w3, w5, w7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub wzr, w3, w5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub w4, w6, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub w11, w13, w15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w9, w3, wzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w17, w29, w20, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w21, w22, w23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w24, w25, w26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w27, w28, w29, lsr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w2, w3, w4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w5, w6, w7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub w8, w9, w10, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub x3, x5, x7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub xzr, x3, x5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub x4, x6, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - sub x11, x13, x15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x9, x3, xzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x17, x29, x20, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x21, x22, x23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x24, x25, x26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x27, x28, x29, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x2, x3, x4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x5, x6, x7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - sub x8, x9, x10, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs w3, w5, w7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp w3, w5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs w4, w6, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs w11, w13, w15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w9, w3, wzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w17, w29, w20, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w21, w22, w23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w24, w25, w26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w27, w28, w29, lsr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w2, w3, w4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w5, w6, w7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs w8, w9, w10, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs x3, x5, x7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp x3, x5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs x4, x6, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subs x11, x13, x15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x9, x3, xzr, lsl #10
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x17, x29, x20, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x21, x22, x23, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x24, x25, x26, lsr #18
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x27, x28, x29, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x2, x3, x4, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x5, x6, x7, asr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - subs x8, x9, x10, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn wzr, w4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn w5, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn w6, w7
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w8, w9, lsl #15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w10, w11, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w12, w13, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w14, w15, lsr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w16, w17, lsr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w18, w19, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w20, w21, asr #22
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn w22, w23, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn x0, x3
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn xzr, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn x5, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmn x6, x7
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x8, x9, lsl #15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x10, x11, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x12, x13, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x14, x15, lsr #41
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x16, x17, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x18, x19, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x20, x21, asr #55
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmn x22, x23, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp w0, w3
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp wzr, w4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp w5, wzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp w6, w7
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w8, w9, lsl #15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w10, w11, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w12, w13, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w14, w15, lsr #21
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w18, w19, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w20, w21, asr #22
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp w22, w23, asr #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp x0, x3
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp xzr, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp x5, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp x6, x7
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x8, x9, lsl #15
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x10, x11, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x12, x13, lsr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x14, x15, lsr #41
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x16, x17, lsr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x18, x19, asr #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x20, x21, asr #55
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - cmp x22, x23, asr #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp wzr, w0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - cmp xzr, x0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc w29, w27, w25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc wzr, w3, w4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc w9, wzr, w10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc w20, w0, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc x29, x27, x25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc xzr, x3, x4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc x9, xzr, x10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adc x20, x0, xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs w29, w27, w25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs wzr, w3, w4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs w9, wzr, w10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs w20, w0, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs x29, x27, x25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs xzr, x3, x4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs x9, xzr, x10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adcs x20, x0, xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc w29, w27, w25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc wzr, w3, w4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc w9, w10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc w20, w0, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc x29, x27, x25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc xzr, x3, x4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc x9, x10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbc x20, x0, xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs w29, w27, w25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs wzr, w3, w4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs w9, w10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs w20, w0, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs x29, x27, x25
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs xzr, x3, x4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs x9, x10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - sbcs x20, x0, xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc w3, w12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc wzr, w9
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc w23, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc x29, x30
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc xzr, x0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngc x0, xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs w3, w12
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs wzr, w9
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs w23, wzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs x29, x30
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs xzr, x0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ngcs x0, xzr
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfx x1, x2, #3, #2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x3, x4, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr wzr, wzr, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfx w12, w9, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfiz x4, x5, #52, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfx xzr, x4, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfiz x4, xzr, #1, #6
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x5, x6, #12
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfi x4, x5, #52, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil xzr, x4, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfc x4, #1, #6
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil x5, x6, #12, #52
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sxtb w1, w2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sxtb xzr, w3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sxth w9, w10
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sxth x0, w1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sxtw x3, w30
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - uxtb w1, w2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - uxth w9, w10
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfx x3, x30, #0, #32
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w3, w2, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w9, w10, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x20, x21, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w1, wzr, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w3, w2, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w9, w10, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x20, x21, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr wzr, wzr, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w3, w2, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w9, w10, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl x20, x21, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w1, wzr, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfx w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfiz x2, x3, #63, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x19, x20, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfiz x9, x10, #5, #59
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w9, w10, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfiz w11, w12, #31, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfiz w13, w14, #29, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfiz xzr, xzr, #10, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfx w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x2, x3, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x19, x20, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x9, x10, #5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w9, w10, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w11, w12, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w13, w14, #29
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - sbfx xzr, xzr, #10, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfi x2, x3, #63, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil x19, x20, #0, #64
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfi x9, x10, #5, #59
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #32
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfi w11, w12, #31, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfi w13, w14, #29, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfc xzr, #10, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil x2, x3, #63, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil x19, x20, #0, #64
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil x9, x10, #5, #59
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w9, w10, #0, #32
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w11, w12, #31, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil w13, w14, #29, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - bfxil xzr, xzr, #10, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfx w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl x2, x3, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x19, x20, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl x9, x10, #5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w9, w10, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w11, w12, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w13, w14, #29
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfiz xzr, xzr, #10, #11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfx w9, w10, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x2, x3, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x19, x20, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x9, x10, #5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w9, w10, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w11, w12, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w13, w14, #29
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ubfx xzr, xzr, #10, #11
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbz w5, #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbz x5, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbnz x2, #-4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbnz x26, #1048572
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbz wzr, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cbnz xzr, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b.ne #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b.ge #1048572
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b.ge #-4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp w1, #31, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp w3, #0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp wzr, #15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp x9, #31, #0, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp x3, #0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp xzr, #5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn w1, #31, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn w3, #0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn wzr, #15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn x9, #31, #0, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn x3, #0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn xzr, #5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp w1, wzr, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp w3, w0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp wzr, w15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp x9, xzr, #0, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp x3, x0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmp xzr, x5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn w1, wzr, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn w3, w0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn wzr, w15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn x9, xzr, #0, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn x3, x0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ccmn xzr, x5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel w1, w0, w19, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel wzr, w5, w9, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel w9, wzr, w30, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel w1, w28, wzr, mi
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel x19, x23, x29, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel xzr, x3, x4, ge
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel x5, xzr, x6, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csel x7, x8, xzr, lo
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc w1, w0, w19, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc wzr, w5, w9, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc w9, wzr, w30, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc w1, w28, wzr, mi
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc x19, x23, x29, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc xzr, x3, x4, ge
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc x5, xzr, x6, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc x7, x8, xzr, lo
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv w1, w0, w19, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv wzr, w5, w9, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv w9, wzr, w30, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv w1, w28, wzr, mi
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv x19, x23, x29, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv xzr, x3, x4, ge
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv x5, xzr, x6, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv x7, x8, xzr, lo
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg w1, w0, w19, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg wzr, w5, w9, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg w9, wzr, w30, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg w1, w28, wzr, mi
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg x19, x23, x29, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg xzr, x3, x4, ge
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg x5, xzr, x6, hs
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg x7, x8, xzr, lo
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cset w3, eq
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cset x9, pl
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csetm w20, ne
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csetm x30, ge
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc w2, wzr, wzr, al
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv x3, xzr, xzr, nv
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinc w3, w5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinc wzr, w4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cset w9, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinc x3, x5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinc xzr, x4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cset x9, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc w5, w6, w6, nv
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinc x1, x2, x2, al
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinv w3, w5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinv wzr, w4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csetm w9, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinv x3, x5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cinv xzr, x4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csetm x9, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv x1, x0, x0, al
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv w9, w8, w8, nv
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg w3, w5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg wzr, w4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg w9, wzr, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg x3, x5, gt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg xzr, x4, le
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - cneg x9, xzr, lt
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csneg x4, x8, x8, al
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - csinv w9, w8, w8, nv
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rbit w0, w7
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rbit x18, x3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rev16 w17, w1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rev16 x5, x2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rev w18, w0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rev32 x20, x1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - rev x22, x2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - clz w24, w3
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - clz x26, x4
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - cls w3, w5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - cls x20, x5
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 - - udiv w0, w7, w10
+# CHECK-NEXT: - - - - 2.00 - - - - 1.00 - - udiv x9, x22, x4
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 - - sdiv w12, w21, w0
+# CHECK-NEXT: - - - - 2.00 - - - - 1.00 - - sdiv x13, x2, x1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w11, w12, w13
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl x14, x15, x16
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w17, w18, w19
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x20, x21, x22
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w23, w24, w25
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x26, x27, x28
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror w0, w1, w2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror x3, x4, x5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl w6, w7, w8
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsl x9, x10, x11
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr w12, w13, w14
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - lsr x15, x16, x17
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr w18, w19, w20
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - asr x21, x22, x23
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror w24, w25, w26
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror x27, x28, x29
+# CHECK-NEXT: - - - - 1.00 - - - - - - - smulh x30, x29, x28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - smulh xzr, x27, x26
+# CHECK-NEXT: - - - - 1.00 - - - - - - - umulh x30, x29, x28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - umulh x23, x30, xzr
+# CHECK-NEXT: - - - - 1.00 - - - - - - - madd w1, w3, w7, w4
+# CHECK-NEXT: - - - - 1.00 - - - - - - - madd wzr, w0, w9, w11
+# CHECK-NEXT: - - - - 1.00 - - - - - - - madd w13, wzr, w4, w4
+# CHECK-NEXT: - - - - 1.00 - - - - - - - madd w19, w30, wzr, w29
+# CHECK-NEXT: - - - - 1.00 - - - - - - - mul w4, w5, w6
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - madd x1, x3, x7, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - madd xzr, x0, x9, x11
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - madd x13, xzr, x4, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - madd x19, x30, xzr, x29
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - mul x4, x5, x6
+# CHECK-NEXT: - - - - 1.00 - - - - - - - msub w1, w3, w7, w4
+# CHECK-NEXT: - - - - 1.00 - - - - - - - msub wzr, w0, w9, w11
+# CHECK-NEXT: - - - - 1.00 - - - - - - - msub w13, wzr, w4, w4
+# CHECK-NEXT: - - - - 1.00 - - - - - - - msub w19, w30, wzr, w29
+# CHECK-NEXT: - - - - 1.00 - - - - - - - mneg w4, w5, w6
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - msub x1, x3, x7, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - msub xzr, x0, x9, x11
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - msub x13, xzr, x4, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - msub x19, x30, xzr, x29
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - mneg x4, x5, x6
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smaddl x3, w5, w2, x9
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smaddl xzr, w10, w11, x12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smaddl x13, wzr, w14, x15
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smaddl x16, w17, wzr, x18
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smull x19, w20, w21
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smsubl x3, w5, w2, x9
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smsubl xzr, w10, w11, x12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smsubl x13, wzr, w14, x15
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smsubl x16, w17, wzr, x18
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smnegl x19, w20, w21
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umaddl x3, w5, w2, x9
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umaddl xzr, w10, w11, x12
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umaddl x13, wzr, w14, x15
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umaddl x16, w17, wzr, x18
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umull x19, w20, w21
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umsubl x3, w5, w2, x9
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umsubl x16, w17, wzr, x18
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umnegl x19, w20, w21
+# CHECK-NEXT: - - - - 1.00 - - - - - - - smulh x30, x29, x28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - smulh x23, x22, xzr
+# CHECK-NEXT: - - - - 1.00 - - - - - - - umulh x23, x22, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - mul x19, x20, xzr
+# CHECK-NEXT: - - - - 1.00 - - - - - - - mneg w21, w22, w23
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smull x11, w13, w17
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umull x11, w13, w17
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - smnegl x11, w13, w17
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 1.00 - - - - - - - umnegl x11, w13, w17
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - extr w3, w5, w7, #0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - extr w11, w13, w17, #31
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - extr x3, x5, x7, #15
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - extr x11, x13, x17, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror x19, x23, #24
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror x29, xzr, #63
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ror w9, w13, #31
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp s3, s5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp s31, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp s31, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe s29, s30
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe s15, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe s15, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp d4, d12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp d23, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmp d23, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe d26, d22
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe d29, #0.0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fcmpe d29, #0.0
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp s1, s31, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp s3, s0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp s31, s15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp d9, d31, #0, le
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp d3, d0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmp d31, d5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe s1, s31, #0, eq
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe s3, s0, #15, hs
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe s31, s15, #13, hs
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe d9, d31, #0, le
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe d3, d0, #15, gt
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 1.00 - - fccmpe d31, d5, #7, ne
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 0.50 0.50 - fcsel s3, s20, s9, pl
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - 0.50 0.50 - fcsel d9, d10, d11, mi
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov s0, s1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs s2, s3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg s4, s5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt s6, s7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt d8, s9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt h10, s11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp s14, s15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm s16, s17
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz s18, s19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta s20, s21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx s22, s23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti s24, s25
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov d0, d1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs d2, d3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg d4, d5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt d6, d7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt s8, d9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt h10, d11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn d12, d13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp d14, d15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm d16, d17
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz d18, d19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta d20, d21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx d22, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti d24, d25
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt s26, h27
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvt d28, h29
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmul s20, s19, s17
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fdiv s1, s2, s3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fadd s4, s5, s6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fsub s7, s8, s9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmax s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmin s13, s14, s15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnm s16, s17, s18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnm s19, s20, s21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmul s22, s23, s2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmul d20, d19, d17
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fdiv d1, d2, d3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fadd d4, d5, d6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fsub d7, d8, d9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmax d10, d11, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmin d13, d14, d15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnm d16, d17, d18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnm d19, d20, d21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmul d22, d23, d24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmadd s3, s5, s6, s31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmadd d3, d13, d0, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmsub s3, s5, s6, s31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmsub d3, d13, d0, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmadd s3, s5, s6, s31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmadd d3, d13, d0, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmsub s3, s5, s6, s31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fnmsub d3, d13, d0, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w3, h5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs wzr, h20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w19, h0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x3, h5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, h30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x19, h0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w3, s5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs wzr, s20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w19, s0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x3, s5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, s30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x19, s0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w3, d5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs wzr, d20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w19, d0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x3, d5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, d30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x19, d0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w3, h5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu wzr, h20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w19, h0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x3, h5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x12, h30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x19, h0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w3, s5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu wzr, s20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w19, s0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x3, s5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x12, s30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x19, s0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w3, d5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu wzr, d20, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w19, d0, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x3, d5, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x12, d30, #45
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x19, d0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h14, x0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s14, x0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d14, x0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h14, x0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s14, x0, #64
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d23, w19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d31, wzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d14, w0, #32
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d23, x19, #1
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d31, xzr, #20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d14, x0, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns w3, h31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns xzr, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu wzr, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu x0, h0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps wzr, h9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps x12, h20
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu w30, h23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu x29, h3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms w2, h3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms x4, h5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu w6, h7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu x8, h9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w10, h11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, h13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w14, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x15, h16
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h17, w18
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h19, x20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf h21, w22
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf h23, x24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas w25, h26
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas x27, h28
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau w29, h30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau xzr, h0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns w3, s31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns xzr, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu wzr, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu x0, s0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps wzr, s9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps x12, s20
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu w30, s23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu x29, s3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms w2, s3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms x4, s5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu w6, s7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu x8, s9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w10, s11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w14, s15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x15, s16
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s17, w18
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s19, x20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf s21, w22
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf s23, x24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas w25, s26
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas x27, s28
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau w29, s30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau xzr, s0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns w3, d31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtns xzr, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu wzr, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtnu x0, d0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps wzr, d9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtps x12, d20
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu w30, d23
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtpu x29, d3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms w2, d3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtms x4, d5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu w6, d7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtmu x8, d9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs w10, d11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzs x12, d13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu w14, d15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtzu x15, d16
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d17, w18
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - scvtf d19, x20
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d21, w22
+# CHECK-NEXT: - - - - 1.00 - - - - 1.00 1.00 - ucvtf d23, x24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas w25, d26
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtas x27, d28
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau w29, d30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 1.00 fcvtau xzr, d0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - fmov w3, s9
+# CHECK-NEXT: - - - - - - - - - - - 1.00 fmov s9, w3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - fmov x20, d31
+# CHECK-NEXT: - - - - - - - - - - - 1.00 fmov d1, x15
+# CHECK-NEXT: - - - - 1.00 - - - - 0.50 0.50 - fmov x3, v12.d[1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fmov v1.d[1], x19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov s2, #0.12500000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov s3, #1.00000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov d30, #16.00000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov s4, #1.06250000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov d10, #1.93750000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov s12, #-1.00000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov d16, #8.50000000
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w3, #0
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x29, #4
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsw xzr, #-4
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr s0, #8
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr d0, #1048572
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q0, #-1048576
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm pldl1strm, #0
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm #22, #0
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxrb w18, w8, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxrh w24, w15, [x16]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxr w5, w6, [x17]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxr w1, x10, [x21]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxrb w30, [x0]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxrh w17, [x4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxr w22, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxr x11, [x29]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxr x11, [x29]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxr x11, [x29]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxp w12, w11, w10, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stxp wzr, x27, x9, [x12]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxp w0, wzr, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxp x17, x0, [x18]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldxp x17, x0, [x18]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxrb w12, w22, [x0]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxrh w10, w1, [x1]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxr w9, w2, [x2]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxr w9, x3, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxrb w8, [x4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxrh w7, [x5]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxr w6, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxr x5, [x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxr x5, [x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxr x5, [x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxp w4, w5, w6, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 0.50 0.50 - - - stlxp wzr, x6, x7, [x1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxp w5, w18, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxp x6, x19, [x22]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldaxp x6, x19, [x22]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlrb w24, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlrh w25, [x30]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlr w26, [x29]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlr x27, [x28]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlr x27, [x28]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stlr x27, [x28]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldarb w23, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldarh w22, [x30]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldar wzr, [x29]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldar x21, [x28]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldar x21, [x28]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldar x21, [x28]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sturb w9, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sturh wzr, [x12, #255]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stur w16, [x0, #-256]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stur x28, [x14, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldurb w1, [x20, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldurh w20, [x1, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur w12, [sp, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur xzr, [x12, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldursb x9, [x7, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldursh x17, [x19, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldursw x20, [x15, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfum pldl2keep, [sp, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldursb w19, [x1, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldursh w15, [x21, #-256]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 stur b0, [sp, #1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 stur h12, [x12, #-1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 stur s15, [x0, #255]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 stur d31, [x5, #25]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 stur q9, [x5]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur b3, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur h5, [x4, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur s7, [x12, #-1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur d11, [x19, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldur q13, [x1, #2]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w9, [x2], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w10, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w10, [x3], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w9, [x2], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w9, [x2], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w10, [x3], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w19, [sp], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w20, [x30], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w21, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str xzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str x2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str x19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w9, [x2], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w10, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w10, [x3], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w9, [x2], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w9, [x2], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w10, [x3], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w19, [sp], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w20, [x30], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w21, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr xzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr x2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr x19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb xzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb x2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb x19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh xzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh x2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh x19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw xzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw x2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw x19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb wzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb w2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb w19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh wzr, [x9], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh w2, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh w19, [x12], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b0, [x0], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b3, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b5, [sp], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h10, [x10], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h13, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h15, [sp], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s20, [x20], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s23, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s25, [x0], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d20, [x20], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d23, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d25, [x0], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b0, [x0], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b3, [x3], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b5, [sp], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h10, [x10], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h13, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h15, [sp], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s20, [x20], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s23, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s25, [x0], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d20, [x20], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d23, [x23], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d25, [x0], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q20, [x1], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q23, [x9], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q25, [x20], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q10, [x1], #255
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q22, [sp], #1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q21, [x20], #-256
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr x3, [x4, #0]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w9, [x2, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w10, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strb w10, [x3, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w9, [x2, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w9, [x2, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - strh w10, [x3, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w19, [sp, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w20, [x30, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str w21, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str xzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str x2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str x19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w9, [x2, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w10, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrb w10, [x3, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w9, [x2, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w9, [x2, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrh w10, [x3, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w19, [sp, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w20, [x30, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr w21, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr xzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr x2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr x19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb xzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb x2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb x19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh xzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh x2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh x19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw xzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw x2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsw x19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb wzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb w2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsb w19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh wzr, [x9, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh w2, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldrsh w19, [x12, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b0, [x0, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b3, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str b5, [sp, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h10, [x10, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h13, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str h15, [sp, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s20, [x20, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s23, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str s25, [x0, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d20, [x20, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d23, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str d25, [x0, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b0, [x0, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b3, [x3, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr b5, [sp, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h10, [x10, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h13, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr h15, [sp, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s20, [x20, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s23, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr s25, [x0, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d20, [x20, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d23, [x23, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr d25, [x0, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q20, [x1, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q23, [x9, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - 0.50 0.50 - - - - - ldr q25, [x20, #-256]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q10, [x1, #255]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q22, [sp, #1]!
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - str q21, [x20, #-256]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sttrb w9, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sttrh wzr, [x12, #255]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sttr w16, [x0, #-256]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - sttr x28, [x14, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrb w1, [x20, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrh w20, [x1, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtr w12, [sp, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtr xzr, [x12, #255]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrsb x9, [x7, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrsh x17, [x19, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrsw x20, [x15, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrsb w19, [x1, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldtrsh w15, [x21, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x4, [x29]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x30, [x12, #32760]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x20, [sp, #8]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr xzr, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w2, [sp]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w17, [sp, #16380]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w13, [x2, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsw x2, [x5, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsw x23, [sp, #16380]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w2, [x4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh w23, [x6, #8190]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh wzr, [sp, #2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh x29, [x2, #2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrb w26, [x3, #121]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrb w12, [x2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsb w27, [sp, #4095]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsb xzr, [x15]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - str x30, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - str w20, [x4, #16380]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - strh w17, [sp, #8190]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - strb w23, [x3, #4095]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - strb wzr, [x2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr b31, [sp, #4095]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr h20, [x2, #8190]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr s10, [x19, #16380]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr d3, [x10, #32760]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str q12, [sp, #65520]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrb w3, [sp, x5]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrb w9, [x27, x6]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrsb w10, [x30, x7]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrb w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - strb w12, [x28, xzr, sxtx]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrb w14, [x26, w6, uxtw]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrsb w15, [x25, w7, uxtw]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrb w17, [x23, w9, sxtw]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrsb x18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh w3, [sp, x5]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh w9, [x27, x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w10, [x30, x7, lsl #1]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - strh w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh x13, [x27, x5, sxtx #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrsh w16, [x24, w8, uxtw #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldrh w18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - strh w19, [x21, wzr, sxtw #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w3, [sp, x5]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr s9, [x27, x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w10, [x30, x7, lsl #2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str s12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - str w13, [x27, x5, sxtx #2]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - str w14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w16, [x24, w8, uxtw #2]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrsw x17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr w18, [x22, w10, sxtw]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - 0.50 0.50 - - - ldrsw x19, [x21, wzr, sxtw #2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x3, [sp, x5]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - str x9, [x27, x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr d10, [x30, x7, lsl #3]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - str x11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x13, [x27, x5, sxtx #3]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - prfm pldl1keep, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x16, [x24, w8, uxtw #3]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr x18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str d19, [x21, wzr, sxtw #3]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q3, [sp, x5]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q9, [x27, x6]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q10, [x30, x7, lsl #4]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str q11, [x29, x3, sxtx]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str q12, [x28, xzr, sxtx]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str q13, [x27, x5, sxtx #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q14, [x26, w6, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q15, [x25, w7, uxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q16, [x24, w8, uxtw #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q17, [x23, w9, sxtw]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 str q18, [x22, w10, sxtw]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldr q19, [x21, wzr, sxtw #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w3, w5, [sp]
+# CHECK-NEXT: - - 0.50 0.50 - - - 0.50 0.50 - - - stp wzr, w9, [sp, #252]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w2, wzr, [sp, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w9, w10, [sp, #4]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [sp, #4]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [x2, #-256]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x20, x30, [sp, #252]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x21, x29, [x2, #504]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x22, x23, [x3, #-512]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x24, x25, [x4, #8]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s29, s28, [sp, #252]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp s27, s26, [sp, #-256]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s1, s2, [x3, #44]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d3, d5, [x9, #504]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d7, d11, [x10, #-512]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp d2, d3, [x30, #-8]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q3, q5, [sp]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q17, q19, [sp, #1008]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ldp q23, q29, [x1, #-1024]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w3, w5, [sp], #0
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - 0.50 0.50 - - - stp wzr, w9, [sp], #252
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w2, wzr, [sp], #-256
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w9, w10, [sp], #4
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [sp], #4
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [x2], #-256
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x20, x30, [sp], #252
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x21, x29, [x2], #504
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x22, x23, [x3], #-512
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x24, x25, [x4], #8
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s29, s28, [sp], #252
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp s27, s26, [sp], #-256
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s1, s2, [x3], #44
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d3, d5, [x9], #504
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d7, d11, [x10], #-512
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp d2, d3, [x30], #-8
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q3, q5, [sp], #0
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q17, q19, [sp], #1008
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ldp q23, q29, [x1], #-1024
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w3, w5, [sp, #0]!
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - 0.50 0.50 - - - stp wzr, w9, [sp, #252]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w2, wzr, [sp, #-256]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp w9, w10, [sp, #4]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [sp, #4]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x9, x10, [x2, #-256]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldpsw x20, x30, [sp, #252]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x21, x29, [x2, #504]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x22, x23, [x3, #-512]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldp x24, x25, [x4, #8]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s29, s28, [sp, #252]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp s27, s26, [sp, #-256]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp s1, s2, [x3, #44]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d3, d5, [x9, #504]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp d7, d11, [x10, #-512]!
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldp d2, d3, [x30, #-8]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q3, q5, [sp, #0]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stp q17, q19, [sp, #1008]!
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ldp q23, q29, [x1, #-1024]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp w3, w5, [sp]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stnp wzr, w9, [sp, #252]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp w2, wzr, [sp, #-256]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp w9, w10, [sp, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp x21, x29, [x2, #504]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp x22, x23, [x3, #-512]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ldnp x24, x25, [x4, #8]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldnp s29, s28, [sp, #252]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stnp s27, s26, [sp, #-256]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldnp s1, s2, [x3, #44]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stnp d3, d5, [x9, #504]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stnp d7, d11, [x10, #-512]
+# CHECK-NEXT: - - - - 1.00 0.50 0.50 - - - - - ldnp d2, d3, [x30, #-8]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stnp q3, q5, [sp]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 stnp q17, q19, [sp, #1008]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ldnp q23, q29, [x1, #-1024]
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov w3, #983055
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x10, #-6148914691236517206
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - and w12, w23, w21
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - and w16, w15, w1, lsl #1
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and w9, w4, w10, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - and w3, w30, w11
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and x3, x5, x7, lsl #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and x5, x14, x19, asr #4
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and w3, w17, w19, ror #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and w0, w2, wzr, lsr #17
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and w3, w30, w11, asr #2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - and xzr, x4, x26
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and w3, wzr, w20, ror #2
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - and x7, x20, xzr, asr #63
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - bic x13, x20, x14, lsl #47
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - bic w2, w7, w9
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - orr w2, w7, w0, asr #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - orr x8, x9, x10, lsl #12
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - orn x3, x5, x7, asr #2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - orn w2, w5, w29
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - ands w7, wzr, w9, lsl #1
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - ands x3, x5, x20, ror #63
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - bics w3, w5, w7
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - bics x3, xzr, x3, lsl #1
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - tst w3, w7, lsl #31
+# CHECK-NEXT: 0.25 0.25 0.75 0.75 - - - - - - - - tst x2, x20, asr #2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x3, x6
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x3, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov wzr, w2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov w3, w5
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movz w2, #0, lsl #16
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov w2, #-1235
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x2, #5299989643264
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - mov x2, #0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movk w3, #0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movz x4, #0, lsl #16
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movk w5, #0, lsl #16
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movz x6, #0, lsl #32
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movk x7, #0, lsl #32
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movz x8, #0, lsl #48
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - movk x9, #0, lsl #48
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adr x2, #1600
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adrp x21, #6553600
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - adr x0, #262144
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - tbz x12, #62, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - tbz x12, #62, #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - tbz x12, #62, #-32768
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - tbnz x12, #60, #32764
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b #-4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - b #134217724
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - br x20
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - blr xzr
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ret x10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - ret
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - eret
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - drps
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s
new file mode 100644
index 00000000000000..a19a106f4b47ec
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
+
+abs w1, w2
+abs x2, x3
+cnt w3, w4
+cnt x4, x5
+ctz w5, w6
+ctz x6, x7
+smax w7, w8, w9
+smax x8, x9, x10
+umax w9, w10, w11
+umax x10, x11, x12
+smin w11, w12, w13
+smin w12, w13, w14
+umin w13, w14, w15
+umin x14, x15, x16
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 abs w1, w2
+# CHECK-NEXT: 1 1 0.25 abs x2, x3
+# CHECK-NEXT: 1 3 1.00 cnt w3, w4
+# CHECK-NEXT: 1 3 1.00 cnt x4, x5
+# CHECK-NEXT: 1 1 0.50 ctz w5, w6
+# CHECK-NEXT: 1 1 0.50 ctz x6, x7
+# CHECK-NEXT: 2 1 0.50 smax w7, w8, w9
+# CHECK-NEXT: 2 1 0.50 smax x8, x9, x10
+# CHECK-NEXT: 2 1 0.50 umax w9, w10, w11
+# CHECK-NEXT: 2 1 0.50 umax x10, x11, x12
+# CHECK-NEXT: 2 1 0.50 smin w11, w12, w13
+# CHECK-NEXT: 2 1 0.50 smin w12, w13, w14
+# CHECK-NEXT: 2 1 0.50 umin w13, w14, w15
+# CHECK-NEXT: 2 1 0.50 umin x14, x15, x16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Ampere1BUnitA
+# CHECK-NEXT: [0.1] - Ampere1BUnitA
+# CHECK-NEXT: [1.0] - Ampere1BUnitB
+# CHECK-NEXT: [1.1] - Ampere1BUnitB
+# CHECK-NEXT: [2] - Ampere1BUnitBS
+# CHECK-NEXT: [3.0] - Ampere1BUnitL
+# CHECK-NEXT: [3.1] - Ampere1BUnitL
+# CHECK-NEXT: [4.0] - Ampere1BUnitS
+# CHECK-NEXT: [4.1] - Ampere1BUnitS
+# CHECK-NEXT: [5] - Ampere1BUnitX
+# CHECK-NEXT: [6] - Ampere1BUnitY
+# CHECK-NEXT: [7] - Ampere1BUnitZ
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
+# CHECK-NEXT: 6.50 6.50 3.50 3.50 2.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - abs w1, w2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - abs x2, x3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - cnt w3, w4
+# CHECK-NEXT: - - - - 1.00 - - - - - - - cnt x4, x5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ctz w5, w6
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - ctz x6, x7
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smax w7, w8, w9
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smax x8, x9, x10
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umax w9, w10, w11
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umax x10, x11, x12
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smin w11, w12, w13
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - smin w12, w13, w14
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umin w13, w14, w15
+# CHECK-NEXT: 0.75 0.75 0.25 0.25 - - - - - - - - umin x14, x15, x16
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
new file mode 100644
index 00000000000000..5148522431edbf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
@@ -0,0 +1,349 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
+
+irg x0, x1
+irg sp, x1
+irg x0, sp
+irg x0, x1, x2
+irg sp, x1, x2
+addg x0, x1, #0, #1
+addg sp, x2, #32, #3
+addg x0, sp, #64, #5
+addg x3, x4, #1008, #6
+addg x5, x6, #112, #15
+subg x0, x1, #0, #1
+subg sp, x2, #32, #3
+subg x0, sp, #64, #5
+subg x3, x4, #1008, #6
+subg x5, x6, #112, #15
+gmi x0, x1, x2
+gmi x3, sp, x4
+gmi xzr, x0, x30
+gmi x30, x0, xzr
+subp x0, x1, x2
+subps x0, x1, x2
+subp x0, sp, sp
+subps x0, sp, sp
+subps xzr, x0, x1
+subps xzr, sp, sp
+stg x0, [x1, #-4096]
+stg x1, [x2, #4080]
+stg x2, [sp, #16]
+stg x3, [x1]
+stg sp, [x1]
+stzg x0, [x1, #-4096]
+stzg x1, [x2, #4080]
+stzg x2, [sp, #16]
+stzg x3, [x1]
+stzg sp, [x1]
+stg x0, [x1, #-4096]!
+stg x1, [x2, #4080]!
+stg x2, [sp, #16]!
+stg sp, [sp, #16]!
+stzg x0, [x1, #-4096]!
+stzg x1, [x2, #4080]!
+stzg x2, [sp, #16]!
+stzg sp, [sp, #16]!
+stg x0, [x1], #-4096
+stg x1, [x2], #4080
+stg x2, [sp], #16
+stg sp, [sp], #16
+stzg x0, [x1], #-4096
+stzg x1, [x2], #4080
+stzg x2, [sp], #16
+stzg sp, [sp], #16
+st2g x0, [x1, #-4096]
+st2g x1, [x2, #4080]
+st2g x2, [sp, #16]
+st2g x3, [x1]
+st2g sp, [x1]
+stz2g x0, [x1, #-4096]
+stz2g x1, [x2, #4080]
+stz2g x2, [sp, #16]
+stz2g x3, [x1]
+stz2g sp, [x1]
+st2g x0, [x1, #-4096]!
+st2g x1, [x2, #4080]!
+st2g x2, [sp, #16]!
+st2g sp, [sp, #16]!
+stz2g x0, [x1, #-4096]!
+stz2g x1, [x2, #4080]!
+stz2g x2, [sp, #16]!
+stz2g sp, [sp, #16]!
+st2g x0, [x1], #-4096
+st2g x1, [x2], #4080
+st2g x2, [sp], #16
+st2g sp, [sp], #16
+stz2g x0, [x1], #-4096
+stz2g x1, [x2], #4080
+stz2g x2, [sp], #16
+stz2g sp, [sp], #16
+stgp x0, x1, [x2, #-1024]
+stgp x0, x1, [x2, #1008]
+stgp x0, x1, [sp, #16]
+stgp xzr, x1, [x2, #16]
+stgp x0, xzr, [x2, #16]
+stgp x0, xzr, [x2]
+stgp x0, x1, [x2, #-1024]!
+stgp x0, x1, [x2, #1008]!
+stgp x0, x1, [sp, #16]!
+stgp xzr, x1, [x2, #16]!
+stgp x0, xzr, [x2, #16]!
+stgp x0, x1, [x2], #-1024
+stgp x0, x1, [x2], #1008
+stgp x0, x1, [sp], #16
+stgp xzr, x1, [x2], #16
+stgp x0, xzr, [x2], #16
+ldg x0, [x1]
+ldg x2, [sp, #-4096]
+ldg x3, [x4, #4080]
+ldgm x0, [x1]
+ldgm x1, [sp]
+ldgm xzr, [x2]
+stgm x0, [x1]
+stgm x1, [sp]
+stgm xzr, [x2]
+stzgm x0, [x1]
+stzgm x1, [sp]
+stzgm xzr, [x2]
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 1 1.00 U irg x0, x1
+# CHECK-NEXT: 2 1 1.00 U irg sp, x1
+# CHECK-NEXT: 2 1 1.00 U irg x0, sp
+# CHECK-NEXT: 2 1 1.00 U irg x0, x1, x2
+# CHECK-NEXT: 2 1 1.00 U irg sp, x1, x2
+# CHECK-NEXT: 1 1 0.50 addg x0, x1, #0, #1
+# CHECK-NEXT: 1 1 0.50 addg sp, x2, #32, #3
+# CHECK-NEXT: 1 1 0.50 addg x0, sp, #64, #5
+# CHECK-NEXT: 1 1 0.50 addg x3, x4, #1008, #6
+# CHECK-NEXT: 1 1 0.50 addg x5, x6, #112, #15
+# CHECK-NEXT: 1 1 0.50 U subg x0, x1, #0, #1
+# CHECK-NEXT: 1 1 0.50 U subg sp, x2, #32, #3
+# CHECK-NEXT: 1 1 0.50 U subg x0, sp, #64, #5
+# CHECK-NEXT: 1 1 0.50 U subg x3, x4, #1008, #6
+# CHECK-NEXT: 1 1 0.50 U subg x5, x6, #112, #15
+# CHECK-NEXT: 1 1 0.25 gmi x0, x1, x2
+# CHECK-NEXT: 1 1 0.25 gmi x3, sp, x4
+# CHECK-NEXT: 1 1 0.25 gmi xzr, x0, x30
+# CHECK-NEXT: 1 1 0.25 gmi x30, x0, xzr
+# CHECK-NEXT: 1 1 0.25 subp x0, x1, x2
+# CHECK-NEXT: 1 1 0.25 U subps x0, x1, x2
+# CHECK-NEXT: 1 1 0.25 subp x0, sp, sp
+# CHECK-NEXT: 1 1 0.25 U subps x0, sp, sp
+# CHECK-NEXT: 1 1 0.25 U subps xzr, x0, x1
+# CHECK-NEXT: 1 1 0.25 U subps xzr, sp, sp
+# CHECK-NEXT: 1 1 0.50 * stg x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * stg x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * stg x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stg x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * stg sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * stzg x0, [x1, #-4096]
+# CHECK-NEXT: 1 1 0.50 * stzg x1, [x2, #4080]
+# CHECK-NEXT: 1 1 0.50 * stzg x2, [sp, #16]
+# CHECK-NEXT: 1 1 0.50 * stzg x3, [x1]
+# CHECK-NEXT: 1 1 0.50 * stzg sp, [x1]
+# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1, #-4096]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2, #4080]!
+# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp, #16]!
+# CHECK-NEXT: 1 1 0.50 * U stg x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U stg x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U stg x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stg sp, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stzg x0, [x1], #-4096
+# CHECK-NEXT: 1 1 0.50 * U stzg x1, [x2], #4080
+# CHECK-NEXT: 1 1 0.50 * U stzg x2, [sp], #16
+# CHECK-NEXT: 1 1 0.50 * U stzg sp, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * st2g x0, [x1, #-4096]
+# CHECK-NEXT: 2 1 1.00 * st2g x1, [x2, #4080]
+# CHECK-NEXT: 2 1 1.00 * st2g x2, [sp, #16]
+# CHECK-NEXT: 2 1 1.00 * st2g x3, [x1]
+# CHECK-NEXT: 2 1 1.00 * st2g sp, [x1]
+# CHECK-NEXT: 2 1 1.00 * stz2g x0, [x1, #-4096]
+# CHECK-NEXT: 2 1 1.00 * stz2g x1, [x2, #4080]
+# CHECK-NEXT: 2 1 1.00 * stz2g x2, [sp, #16]
+# CHECK-NEXT: 2 1 1.00 * stz2g x3, [x1]
+# CHECK-NEXT: 2 1 1.00 * stz2g sp, [x1]
+# CHECK-NEXT: 2 1 1.00 * U st2g x0, [x1, #-4096]!
+# CHECK-NEXT: 2 1 1.00 * U st2g x1, [x2, #4080]!
+# CHECK-NEXT: 2 1 1.00 * U st2g x2, [sp, #16]!
+# CHECK-NEXT: 2 1 1.00 * U st2g sp, [sp, #16]!
+# CHECK-NEXT: 2 1 1.00 * U stz2g x0, [x1, #-4096]!
+# CHECK-NEXT: 2 1 1.00 * U stz2g x1, [x2, #4080]!
+# CHECK-NEXT: 2 1 1.00 * U stz2g x2, [sp, #16]!
+# CHECK-NEXT: 2 1 1.00 * U stz2g sp, [sp, #16]!
+# CHECK-NEXT: 2 1 1.00 * U st2g x0, [x1], #-4096
+# CHECK-NEXT: 2 1 1.00 * U st2g x1, [x2], #4080
+# CHECK-NEXT: 2 1 1.00 * U st2g x2, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * U st2g sp, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * U stz2g x0, [x1], #-4096
+# CHECK-NEXT: 2 1 1.00 * U stz2g x1, [x2], #4080
+# CHECK-NEXT: 2 1 1.00 * U stz2g x2, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * U stz2g sp, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #-1024]
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #1008]
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp, #16]
+# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2, #16]
+# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2, #16]
+# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2]
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #-1024]!
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2, #1008]!
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp, #16]!
+# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2, #16]!
+# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2, #16]!
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2], #-1024
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [x2], #1008
+# CHECK-NEXT: 2 1 1.00 * stgp x0, x1, [sp], #16
+# CHECK-NEXT: 2 1 1.00 * stgp xzr, x1, [x2], #16
+# CHECK-NEXT: 2 1 1.00 * stgp x0, xzr, [x2], #16
+# CHECK-NEXT: 2 4 0.50 * ldg x0, [x1]
+# CHECK-NEXT: 2 4 0.50 * ldg x2, [sp, #-4096]
+# CHECK-NEXT: 2 4 0.50 * ldg x3, [x4, #4080]
+# CHECK-NEXT: 2 4 0.50 * U ldgm x0, [x1]
+# CHECK-NEXT: 2 4 0.50 * U ldgm x1, [sp]
+# CHECK-NEXT: 2 4 0.50 * U ldgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 U stgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 U stgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 U stgm xzr, [x2]
+# CHECK-NEXT: 1 1 0.50 U stzgm x0, [x1]
+# CHECK-NEXT: 1 1 0.50 U stzgm x1, [sp]
+# CHECK-NEXT: 1 1 0.50 U stzgm xzr, [x2]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Ampere1BUnitA
+# CHECK-NEXT: [0.1] - Ampere1BUnitA
+# CHECK-NEXT: [1.0] - Ampere1BUnitB
+# CHECK-NEXT: [1.1] - Ampere1BUnitB
+# CHECK-NEXT: [2] - Ampere1BUnitBS
+# CHECK-NEXT: [3.0] - Ampere1BUnitL
+# CHECK-NEXT: [3.1] - Ampere1BUnitL
+# CHECK-NEXT: [4.0] - Ampere1BUnitS
+# CHECK-NEXT: [4.1] - Ampere1BUnitS
+# CHECK-NEXT: [5] - Ampere1BUnitX
+# CHECK-NEXT: [6] - Ampere1BUnitY
+# CHECK-NEXT: [7] - Ampere1BUnitZ
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
+# CHECK-NEXT: 2.50 2.50 13.00 13.00 5.00 3.00 3.00 58.00 58.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, x1
+# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg sp, x1
+# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, sp
+# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg x0, x1, x2
+# CHECK-NEXT: - - 0.50 0.50 1.00 - - - - - - - irg sp, x1, x2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x0, x1, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg sp, x2, #32, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x0, sp, #64, #5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x3, x4, #1008, #6
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - addg x5, x6, #112, #15
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x0, x1, #0, #1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg sp, x2, #32, #3
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x0, sp, #64, #5
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x3, x4, #1008, #6
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - subg x5, x6, #112, #15
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x0, x1, x2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x3, sp, x4
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi xzr, x0, x30
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - gmi x30, x0, xzr
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subp x0, x1, x2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps x0, x1, x2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subp x0, sp, sp
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps x0, sp, sp
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps xzr, x0, x1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - subps xzr, sp, sp
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1, #-4096]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2, #4080]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp, #16]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x3, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1, #-4096]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2, #4080]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp, #16]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x3, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2, #4080]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2, #4080]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x0, [x1], #-4096
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x1, [x2], #4080
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg x2, [sp], #16
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stg sp, [sp], #16
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x0, [x1], #-4096
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x1, [x2], #4080
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg x2, [sp], #16
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzg sp, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1, #-4096]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2, #4080]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp, #16]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x3, [x1]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [x1]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1, #-4096]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2, #4080]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp, #16]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x3, [x1]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [x1]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2, #4080]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1, #-4096]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2, #4080]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x0, [x1], #-4096
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x1, [x2], #4080
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g x2, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - st2g sp, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x0, [x1], #-4096
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x1, [x2], #4080
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g x2, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stz2g sp, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #-1024]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #1008]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp, #16]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2, #16]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2, #16]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #-1024]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2, #1008]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2, #16]!
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2], #-1024
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [x2], #1008
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, x1, [sp], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp xzr, x1, [x2], #16
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - - stgp x0, xzr, [x2], #16
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x0, [x1]
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x2, [sp, #-4096]
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldg x3, [x4, #4080]
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm x0, [x1]
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm x1, [sp]
+# CHECK-NEXT: - - 0.50 0.50 - 0.50 0.50 - - - - - ldgm xzr, [x2]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm x0, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm x1, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stgm xzr, [x2]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm x0, [x1]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm x1, [sp]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - stzgm xzr, [x2]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
new file mode 100644
index 00000000000000..827c13a24763de
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
@@ -0,0 +1,3235 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=ampere1b -instruction-tables < %s | FileCheck %s
+
+abs d29, d24
+abs v0.16b, v0.16b
+abs v0.2d, v0.2d
+abs v0.2s, v0.2s
+abs v0.4h, v0.4h
+abs v0.4s, v0.4s
+abs v0.8b, v0.8b
+abs v0.8h, v0.8h
+add d17, d31, d29
+add v0.8b, v0.8b, v0.8b
+addhn v0.2s, v0.2d, v0.2d
+addhn v0.4h, v0.4s, v0.4s
+addhn v0.8b, v0.8h, v0.8h
+addhn2 v0.16b, v0.8h, v0.8h
+addhn2 v0.4s, v0.2d, v0.2d
+addhn2 v0.8h, v0.4s, v0.4s
+addp v0.2d, v0.2d, v0.2d
+addp v0.8b, v0.8b, v0.8b
+and v0.8b, v0.8b, v0.8b
+bic v0.4h, #15, lsl #8
+bic v0.8b, v0.8b, v0.8b
+bif v0.16b, v0.16b, v0.16b
+bit v0.16b, v0.16b, v0.16b
+bsl v0.8b, v0.8b, v0.8b
+cls v0.16b, v0.16b
+cls v0.2s, v0.2s
+cls v0.4h, v0.4h
+cls v0.4s, v0.4s
+cls v0.8b, v0.8b
+cls v0.8h, v0.8h
+clz v0.16b, v0.16b
+clz v0.2s, v0.2s
+clz v0.4h, v0.4h
+clz v0.4s, v0.4s
+clz v0.8b, v0.8b
+clz v0.8h, v0.8h
+cmeq d20, d21, 0
+cmeq d20, d21, d22
+cmeq v0.16b, v0.16b, 0
+cmeq v0.16b, v0.16b, v0.16b
+cmge d20, d21, 0
+cmge d20, d21, d22
+cmge v0.4h, v0.4h, v0.4h
+cmge v0.8b, v0.8b, 0
+cmgt d20, d21, 0
+cmgt d20, d21, d22
+cmgt v0.2s, v0.2s, 0
+cmgt v0.4s, v0.4s, v0.4s
+cmhi d20, d21, d22
+cmhi v0.8h, v0.8h, v0.8h
+cmhs d20, d21, d22
+cmhs v0.8b, v0.8b, v0.8b
+cmle d20, d21, 0
+cmle v0.2d, v0.2d, 0
+cmlt d20, d21, 0
+cmlt v0.8h, v0.8h, 0
+cmtst d20, d21, d22
+cmtst v0.2s, v0.2s, v0.2s
+cnt v0.16b, v0.16b
+cnt v0.8b, v0.8b
+dup v0.16b,w28
+dup v0.2d,x28
+dup v0.2s,w28
+dup v0.4h,w28
+dup v0.4s,w28
+dup v0.8b,w28
+dup v0.8h,w28
+eor v0.16b, v0.16b, v0.16b
+ext v0.16b, v0.16b, v0.16b, #3
+ext v0.8b, v0.8b, v0.8b, #3
+fabd d29, d24, d20
+fabd s29, s24, s20
+fabd v0.4s, v0.4s, v0.4s
+fabs v0.2d, v0.2d
+fabs v0.2s, v0.2s
+fabs v0.4h, v0.4h
+fabs v0.4s, v0.4s
+fabs v0.8h, v0.8h
+facge d20, d21, d22
+facge s10, s11, s12
+facge v0.4s, v0.4s, v0.4s
+facgt d20, d21, d22
+facgt s10, s11, s12
+facgt v0.2d, v0.2d, v0.2d
+fadd v0.4s, v0.4s, v0.4s
+faddp v0.2s, v0.2s, v0.2s
+faddp v0.4s, v0.4s, v0.4s
+fcmeq d20, d21, #0.0
+fcmeq d20, d21, d22
+fcmeq s10, s11, #0.0
+fcmeq s10, s11, s12
+fcmeq v0.2s, v0.2s, #0.0
+fcmeq v0.2s, v0.2s, v0.2s
+fcmge d20, d21, #0.0
+fcmge d20, d21, d22
+fcmge s10, s11, #0.0
+fcmge s10, s11, s12
+fcmge v0.2d, v0.2d, #0.0
+fcmge v0.4s, v0.4s, v0.4s
+fcmgt d20, d21, #0.0
+fcmgt d20, d21, d22
+fcmgt s10, s11, #0.0
+fcmgt s10, s11, s12
+fcmgt v0.4s, v0.4s, #0.0
+fcmgt v0.4s, v0.4s, v0.4s
+fcmle d20, d21, #0.0
+fcmle s10, s11, #0.0
+fcmle v0.2d, v0.2d, #0.0
+fcmlt d20, d21, #0.0
+fcmlt s10, s11, #0.0
+fcmlt v0.4s, v0.4s, #0.0
+fcvtas d21, d14
+fcvtas s12, s13
+fcvtas v0.2d, v0.2d
+fcvtas v0.2s, v0.2s
+fcvtas v0.4h, v0.4h
+fcvtas v0.4s, v0.4s
+fcvtas v0.8h, v0.8h
+fcvtau d21, d14
+fcvtau s12, s13
+fcvtau v0.2d, v0.2d
+fcvtau v0.2s, v0.2s
+fcvtau v0.4h, v0.4h
+fcvtau v0.4s, v0.4s
+fcvtau v0.8h, v0.8h
+fcvtl v0.2d, v0.2s
+fcvtl v0.4s, v0.4h
+fcvtl2 v0.2d, v0.4s
+fcvtl2 v0.4s, v0.8h
+fcvtms d21, d14
+fcvtms s22, s13
+fcvtms v0.2d, v0.2d
+fcvtms v0.2s, v0.2s
+fcvtms v0.4h, v0.4h
+fcvtms v0.4s, v0.4s
+fcvtms v0.8h, v0.8h
+fcvtmu d21, d14
+fcvtmu s12, s13
+fcvtmu v0.2d, v0.2d
+fcvtmu v0.2s, v0.2s
+fcvtmu v0.4h, v0.4h
+fcvtmu v0.4s, v0.4s
+fcvtmu v0.8h, v0.8h
+fcvtn v0.2s, v0.2d
+fcvtn v0.4h, v0.4s
+fcvtn2 v0.4s, v0.2d
+fcvtn2 v0.8h, v0.4s
+fcvtns d21, d14
+fcvtns s22, s13
+fcvtns v0.2d, v0.2d
+fcvtns v0.2s, v0.2s
+fcvtns v0.4h, v0.4h
+fcvtns v0.4s, v0.4s
+fcvtns v0.8h, v0.8h
+fcvtnu d21, d14
+fcvtnu s12, s13
+fcvtnu v0.2d, v0.2d
+fcvtnu v0.2s, v0.2s
+fcvtnu v0.4h, v0.4h
+fcvtnu v0.4s, v0.4s
+fcvtnu v0.8h, v0.8h
+fcvtps d21, d14
+fcvtps s22, s13
+fcvtps v0.2d, v0.2d
+fcvtps v0.2s, v0.2s
+fcvtps v0.4h, v0.4h
+fcvtps v0.4s, v0.4s
+fcvtps v0.8h, v0.8h
+fcvtpu d21, d14
+fcvtpu s12, s13
+fcvtpu v0.2d, v0.2d
+fcvtpu v0.2s, v0.2s
+fcvtpu v0.4h, v0.4h
+fcvtpu v0.4s, v0.4s
+fcvtpu v0.8h, v0.8h
+fcvtxn s22, d13
+fcvtxn v0.2s, v0.2d
+fcvtxn2 v0.4s, v0.2d
+fcvtzs d21, d12, #1
+fcvtzs d21, d14
+fcvtzs s12, s13
+fcvtzs s21, s12, #1
+fcvtzs v0.2d, v0.2d
+fcvtzs v0.2d, v0.2d, #3
+fcvtzs v0.2s, v0.2s
+fcvtzs v0.2s, v0.2s, #3
+fcvtzs v0.4h, v0.4h
+fcvtzs v0.4s, v0.4s
+fcvtzs v0.4s, v0.4s, #3
+fcvtzs v0.8h, v0.8h
+fcvtzu d21, d12, #1
+fcvtzu d21, d14
+fcvtzu s12, s13
+fcvtzu s21, s12, #1
+fcvtzu v0.2d, v0.2d
+fcvtzu v0.2d, v0.2d, #3
+fcvtzu v0.2s, v0.2s
+fcvtzu v0.2s, v0.2s, #3
+fcvtzu v0.4h, v0.4h
+fcvtzu v0.4s, v0.4s
+fcvtzu v0.4s, v0.4s, #3
+fcvtzu v0.8h, v0.8h
+fdiv v0.2s, v0.2s, v0.2s
+fmax v0.2d, v0.2d, v0.2d
+fmax v0.2s, v0.2s, v0.2s
+fmax v0.4s, v0.4s, v0.4s
+fmaxnm v0.2d, v0.2d, v0.2d
+fmaxnm v0.2s, v0.2s, v0.2s
+fmaxnm v0.4s, v0.4s, v0.4s
+fmaxnmp v0.2d, v0.2d, v0.2d
+fmaxnmp v0.2s, v0.2s, v0.2s
+fmaxnmp v0.4s, v0.4s, v0.4s
+fmaxp v0.2d, v0.2d, v0.2d
+fmaxp v0.2s, v0.2s, v0.2s
+fmaxp v0.4s, v0.4s, v0.4s
+fmin v0.2d, v0.2d, v0.2d
+fmin v0.2s, v0.2s, v0.2s
+fmin v0.4s, v0.4s, v0.4s
+fminnm v0.2d, v0.2d, v0.2d
+fminnm v0.2s, v0.2s, v0.2s
+fminnm v0.4s, v0.4s, v0.4s
+fminnmp v0.2d, v0.2d, v0.2d
+fminnmp v0.2s, v0.2s, v0.2s
+fminnmp v0.4s, v0.4s, v0.4s
+fminp v0.2d, v0.2d, v0.2d
+fminp v0.2s, v0.2s, v0.2s
+fminp v0.4s, v0.4s, v0.4s
+fmla d0, d1, v0.d[1]
+fmla s0, s1, v0.s[3]
+fmla v0.2s, v0.2s, v0.2s
+fmls d0, d4, v0.d[1]
+fmls s3, s5, v0.s[3]
+fmls v0.2s, v0.2s, v0.2s
+fmov v0.2d, #-1.25
+fmov v0.2s, #13.0
+fmov v0.4s, #1.0
+fmul d0, d1, v0.d[1]
+fmul s0, s1, v0.s[3]
+fmul v0.2s, v0.2s, v0.2s
+fmulx d0, d4, v0.d[1]
+fmulx d23, d11, d1
+fmulx s20, s22, s15
+fmulx s3, s5, v0.s[3]
+fmulx v0.2d, v0.2d, v0.2d
+fmulx v0.2s, v0.2s, v0.2s
+fmulx v0.4s, v0.4s, v0.4s
+fneg v0.2d, v0.2d
+fneg v0.2s, v0.2s
+fneg v0.4h, v0.4h
+fneg v0.4s, v0.4s
+fneg v0.8h, v0.8h
+frecpe d13, d13
+frecpe s19, s14
+frecpe v0.2d, v0.2d
+frecpe v0.2s, v0.2s
+frecpe v0.4h, v0.4h
+frecpe v0.4s, v0.4s
+frecpe v0.8h, v0.8h
+frecps v0.4s, v0.4s, v0.4s
+frecps d22, d30, d21
+frecps s21, s16, s13
+frecpx d16, d19
+frecpx s18, s10
+frinta v0.2d, v0.2d
+frinta v0.2s, v0.2s
+frinta v0.4h, v0.4h
+frinta v0.4s, v0.4s
+frinta v0.8h, v0.8h
+frinti v0.2d, v0.2d
+frinti v0.2s, v0.2s
+frinti v0.4h, v0.4h
+frinti v0.4s, v0.4s
+frinti v0.8h, v0.8h
+frintm v0.2d, v0.2d
+frintm v0.2s, v0.2s
+frintm v0.4h, v0.4h
+frintm v0.4s, v0.4s
+frintm v0.8h, v0.8h
+frintn v0.2d, v0.2d
+frintn v0.2s, v0.2s
+frintn v0.4h, v0.4h
+frintn v0.4s, v0.4s
+frintn v0.8h, v0.8h
+frintp v0.2d, v0.2d
+frintp v0.2s, v0.2s
+frintp v0.4h, v0.4h
+frintp v0.4s, v0.4s
+frintp v0.8h, v0.8h
+frintx v0.2d, v0.2d
+frintx v0.2s, v0.2s
+frintx v0.4h, v0.4h
+frintx v0.4s, v0.4s
+frintx v0.8h, v0.8h
+frintz v0.2d, v0.2d
+frintz v0.2s, v0.2s
+frintz v0.4h, v0.4h
+frintz v0.4s, v0.4s
+frintz v0.8h, v0.8h
+frsqrte d21, d12
+frsqrte s22, s13
+frsqrte v0.2d, v0.2d
+frsqrte v0.2s, v0.2s
+frsqrte v0.4h, v0.4h
+frsqrte v0.4s, v0.4s
+frsqrte v0.8h, v0.8h
+frsqrts d8, d22, d18
+frsqrts s21, s5, s12
+frsqrts v0.2d, v0.2d, v0.2d
+fsqrt v0.2d, v0.2d
+fsqrt v0.2s, v0.2s
+fsqrt v0.4h, v0.4h
+fsqrt v0.4s, v0.4s
+fsqrt v0.8h, v0.8h
+fsub v0.2s, v0.2s, v0.2s
+ld1 { v0.16b }, [x0]
+ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+ld1 { v0.4s, v1.4s }, [sp], #32
+ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+ld1 { v0.8h }, [x15], x2
+ld1 { v0.8h, v1.8h }, [x15]
+ld1 { v0.b }[9], [x0]
+ld1 { v0.b }[9], [x0], #1
+ld1r { v0.16b }, [x0]
+ld1r { v0.16b }, [x0], #1
+ld1r { v0.8h }, [x15]
+ld1r { v0.8h }, [x15], #2
+ld2 { v0.16b, v1.16b }, [x0], x1
+ld2 { v0.8b, v1.8b }, [x0]
+ld2 { v0.h, v1.h }[7], [x15]
+ld2 { v0.h, v1.h }[7], [x15], #4
+ld2r { v0.2d, v1.2d }, [x0]
+ld2r { v0.2d, v1.2d }, [x0], #16
+ld2r { v0.4s, v1.4s }, [sp]
+ld2r { v0.4s, v1.4s }, [sp], #8
+ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+ld3 { v0.s, v1.s, v2.s }[3], [sp]
+ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+mla v0.8b, v0.8b, v0.8b
+mls v0.4h, v0.4h, v0.4h
+mov b0, v0.b[15]
+mov d6, v0.d[1]
+mov h2, v0.h[5]
+mov s17, v0.s[2]
+mov v2.b[0], v0.b[0]
+mov v2.h[1], v0.h[1]
+mov v2.s[2], v0.s[2]
+mov v2.d[1], v0.d[1]
+mov v0.b[0], w8
+mov v0.h[1], w8
+mov v0.s[2], w8
+mov v0.d[1], x8
+mov v0.16b, v0.16b
+mov v0.8b, v0.8b
+movi d15, #0xff00ff00ff00ff
+movi v0.16b, #31
+movi v0.2d, #0xff0000ff0000ffff
+movi v0.2s, #8, msl #8
+movi v0.4s, #255, lsl #24
+movi v0.8b, #255
+mul v0.8b, v0.8b, v0.8b
+mvni v0.2s, 0
+mvni v0.4s, #16, msl #16
+neg d29, d24
+neg v0.16b, v0.16b
+neg v0.2d, v0.2d
+neg v0.2s, v0.2s
+neg v0.4h, v0.4h
+neg v0.4s, v0.4s
+neg v0.8b, v0.8b
+neg v0.8h, v0.8h
+not v0.16b, v0.16b
+not v0.8b, v0.8b
+orn v0.16b, v0.16b, v0.16b
+orr v0.16b, v0.16b, v0.16b
+orr v0.8h, #31
+pmul v0.16b, v0.16b, v0.16b
+pmul v0.8b, v0.8b, v0.8b
+pmull v0.8h, v0.8b, v0.8b
+pmull2 v0.8h, v0.16b, v0.16b
+raddhn v0.2s, v0.2d, v0.2d
+raddhn v0.4h, v0.4s, v0.4s
+raddhn v0.8b, v0.8h, v0.8h
+raddhn2 v0.16b, v0.8h, v0.8h
+raddhn2 v0.4s, v0.2d, v0.2d
+raddhn2 v0.8h, v0.4s, v0.4s
+rbit v0.16b, v0.16b
+rbit v0.8b, v0.8b
+rev16 v21.8b, v1.8b
+rev16 v30.16b, v31.16b
+rev32 v0.4h, v9.4h
+rev32 v21.8b, v1.8b
+rev32 v30.16b, v31.16b
+rev32 v4.8h, v7.8h
+rev64 v0.16b, v31.16b
+rev64 v1.8b, v9.8b
+rev64 v13.4h, v21.4h
+rev64 v2.8h, v4.8h
+rev64 v4.2s, v0.2s
+rev64 v6.4s, v8.4s
+rshrn v0.2s, v0.2d, #3
+rshrn v0.4h, v0.4s, #3
+rshrn v0.8b, v0.8h, #3
+rshrn2 v0.16b, v0.8h, #3
+rshrn2 v0.4s, v0.2d, #3
+rshrn2 v0.8h, v0.4s, #3
+rsubhn v0.2s, v0.2d, v0.2d
+rsubhn v0.4h, v0.4s, v0.4s
+rsubhn v0.8b, v0.8h, v0.8h
+rsubhn2 v0.16b, v0.8h, v0.8h
+rsubhn2 v0.4s, v0.2d, v0.2d
+rsubhn2 v0.8h, v0.4s, v0.4s
+saba v0.16b, v0.16b, v0.16b
+sabal v0.2d, v0.2s, v0.2s
+sabal v0.4s, v0.4h, v0.4h
+sabal v0.8h, v0.8b, v0.8b
+sabal2 v0.2d, v0.4s, v0.4s
+sabal2 v0.4s, v0.8h, v0.8h
+sabal2 v0.8h, v0.16b, v0.16b
+sabd v0.4h, v0.4h, v0.4h
+sabdl v0.2d, v0.2s, v0.2s
+sabdl v0.4s, v0.4h, v0.4h
+sabdl v0.8h, v0.8b, v0.8b
+sabdl2 v0.2d, v0.4s, v0.4s
+sabdl2 v0.4s, v0.8h, v0.8h
+sabdl2 v0.8h, v0.16b, v0.16b
+sadalp v0.1d, v0.2s
+sadalp v0.2d, v0.4s
+sadalp v0.2s, v0.4h
+sadalp v0.4h, v0.8b
+sadalp v0.4s, v0.8h
+sadalp v0.8h, v0.16b
+saddl v0.2d, v0.2s, v0.2s
+saddl v0.4s, v0.4h, v0.4h
+saddl v0.8h, v0.8b, v0.8b
+saddl2 v0.2d, v0.4s, v0.4s
+saddl2 v0.4s, v0.8h, v0.8h
+saddl2 v0.8h, v0.16b, v0.16b
+saddlp v0.1d, v0.2s
+saddlp v0.2d, v0.4s
+saddlp v0.2s, v0.4h
+saddlp v0.4h, v0.8b
+saddlp v0.4s, v0.8h
+saddlp v0.8h, v0.16b
+saddw v0.2d, v0.2d, v0.2s
+saddw v0.4s, v0.4s, v0.4h
+saddw v0.8h, v0.8h, v0.8b
+saddw2 v0.2d, v0.2d, v0.4s
+saddw2 v0.4s, v0.4s, v0.8h
+saddw2 v0.8h, v0.8h, v0.16b
+scvtf d21, d12
+scvtf d21, d12, #64
+scvtf s22, s13
+scvtf s22, s13, #32
+scvtf v0.2d, v0.2d
+scvtf v0.2d, v0.2d, #3
+scvtf v0.2s, v0.2s
+scvtf v0.2s, v0.2s, #3
+scvtf v0.4h, v0.4h
+scvtf v0.4s, v0.4s
+scvtf v0.4s, v0.4s, #3
+scvtf v0.8h, v0.8h
+shadd v0.8b, v0.8b, v0.8b
+shl d7, d10, #12
+shl v0.16b, v0.16b, #3
+shl v0.2d, v0.2d, #3
+shl v0.4h, v0.4h, #3
+shl v0.4s, v0.4s, #3
+shll v0.2d, v0.2s, #32
+shll v0.4s, v0.4h, #16
+shll v0.8h, v0.8b, #8
+shll v0.2d, v0.2s, #32
+shll v0.4s, v0.4h, #16
+shll v0.8h, v0.8b, #8
+shll2 v0.2d, v0.4s, #32
+shll2 v0.4s, v0.8h, #16
+shll2 v0.8h, v0.16b, #8
+shll2 v0.2d, v0.4s, #32
+shll2 v0.4s, v0.8h, #16
+shll2 v0.8h, v0.16b, #8
+shrn v0.2s, v0.2d, #3
+shrn v0.4h, v0.4s, #3
+shrn v0.8b, v0.8h, #3
+shrn2 v0.16b, v0.8h, #3
+shrn2 v0.4s, v0.2d, #3
+shrn2 v0.8h, v0.4s, #3
+shsub v0.2s, v0.2s, v0.2s
+shsub v0.4h, v0.4h, v0.4h
+sli d10, d14, #12
+sli v0.16b, v0.16b, #3
+sli v0.2d, v0.2d, #3
+sli v0.2s, v0.2s, #3
+sli v0.4h, v0.4h, #3
+sli v0.4s, v0.4s, #3
+sli v0.8b, v0.8b, #3
+sli v0.8h, v0.8h, #3
+smax v0.2s, v0.2s, v0.2s
+smax v0.4h, v0.4h, v0.4h
+smax v0.8b, v0.8b, v0.8b
+smaxp v0.2s, v0.2s, v0.2s
+smaxp v0.4h, v0.4h, v0.4h
+smaxp v0.8b, v0.8b, v0.8b
+smin v0.16b, v0.16b, v0.16b
+smin v0.4s, v0.4s, v0.4s
+smin v0.8h, v0.8h, v0.8h
+sminp v0.16b, v0.16b, v0.16b
+sminp v0.4s, v0.4s, v0.4s
+sminp v0.8h, v0.8h, v0.8h
+smlal v0.2d, v0.2s, v0.2s
+smlal v0.4s, v0.4h, v0.4h
+smlal v0.8h, v0.8b, v0.8b
+smlal2 v0.2d, v0.4s, v0.4s
+smlal2 v0.4s, v0.8h, v0.8h
+smlal2 v0.8h, v0.16b, v0.16b
+smlsl v0.2d, v0.2s, v0.2s
+smlsl v0.4s, v0.4h, v0.4h
+smlsl v0.8h, v0.8b, v0.8b
+smlsl2 v0.2d, v0.4s, v0.4s
+smlsl2 v0.4s, v0.8h, v0.8h
+smlsl2 v0.8h, v0.16b, v0.16b
+smull v0.2d, v0.2s, v0.2s
+smull v0.4s, v0.4h, v0.4h
+smull v0.8h, v0.8b, v0.8b
+smull2 v0.2d, v0.4s, v0.4s
+smull2 v0.4s, v0.8h, v0.8h
+smull2 v0.8h, v0.16b, v0.16b
+sqabs b19, b14
+sqabs d18, d12
+sqabs h21, h15
+sqabs s20, s12
+sqabs v0.16b, v0.16b
+sqabs v0.2d, v0.2d
+sqabs v0.2s, v0.2s
+sqabs v0.4h, v0.4h
+sqabs v0.4s, v0.4s
+sqabs v0.8b, v0.8b
+sqabs v0.8h, v0.8h
+sqadd b20, b11, b15
+sqadd v0.16b, v0.16b, v0.16b
+sqadd v0.2s, v0.2s, v0.2s
+sqdmlal d19, s24, s12
+sqdmlal d8, s9, v0.s[1]
+sqdmlal s0, h0, v0.h[3]
+sqdmlal s17, h27, h12
+sqdmlal v0.2d, v0.2s, v0.2s
+sqdmlal v0.4s, v0.4h, v0.4h
+sqdmlal2 v0.2d, v0.4s, v0.4s
+sqdmlal2 v0.4s, v0.8h, v0.8h
+sqdmlsl d12, s23, s13
+sqdmlsl d8, s9, v0.s[1]
+sqdmlsl s0, h0, v0.h[3]
+sqdmlsl s14, h12, h25
+sqdmlsl v0.2d, v0.2s, v0.2s
+sqdmlsl v0.4s, v0.4h, v0.4h
+sqdmlsl2 v0.2d, v0.4s, v0.4s
+sqdmlsl2 v0.4s, v0.8h, v0.8h
+sqdmulh h10, h11, h12
+sqdmulh h7, h15, v0.h[3]
+sqdmulh s15, s14, v0.s[1]
+sqdmulh s20, s21, s2
+sqdmulh v0.2s, v0.2s, v0.2s
+sqdmulh v0.4s, v0.4s, v0.4s
+sqdmull d1, s1, v0.s[1]
+sqdmull d15, s22, s12
+sqdmull s1, h1, v0.h[3]
+sqdmull s12, h22, h12
+sqdmull v0.2d, v0.2s, v0.2s
+sqdmull v0.4s, v0.4h, v0.4h
+sqdmull2 v0.2d, v0.4s, v0.4s
+sqdmull2 v0.4s, v0.8h, v0.8h
+sqneg b19, b14
+sqneg d18, d12
+sqneg h21, h15
+sqneg s20, s12
+sqneg v0.16b, v0.16b
+sqneg v0.2d, v0.2d
+sqneg v0.2s, v0.2s
+sqneg v0.4h, v0.4h
+sqneg v0.4s, v0.4s
+sqneg v0.8b, v0.8b
+sqneg v0.8h, v0.8h
+sqrdmulh h10, h11, h12
+sqrdmulh h7, h15, v0.h[3]
+sqrdmulh s15, s14, v0.s[1]
+sqrdmulh s20, s21, s2
+sqrdmulh v0.4h, v0.4h, v0.4h
+sqrdmulh v0.8h, v0.8h, v0.8h
+sqrshl d31, d31, d31
+sqrshl h3, h4, h15
+sqrshl v0.2s, v0.2s, v0.2s
+sqrshl v0.4h, v0.4h, v0.4h
+sqrshl v0.8b, v0.8b, v0.8b
+sqrshrn b10, h13, #2
+sqrshrn h15, s10, #6
+sqrshrn s15, d12, #9
+sqrshrn v0.2s, v0.2d, #3
+sqrshrn v0.4h, v0.4s, #3
+sqrshrn v0.8b, v0.8h, #3
+sqrshrn2 v0.16b, v0.8h, #3
+sqrshrn2 v0.4s, v0.2d, #3
+sqrshrn2 v0.8h, v0.4s, #3
+sqrshrun b17, h10, #6
+sqrshrun h10, s13, #15
+sqrshrun s22, d16, #31
+sqrshrun v0.2s, v0.2d, #3
+sqrshrun v0.4h, v0.4s, #3
+sqrshrun v0.8b, v0.8h, #3
+sqrshrun2 v0.16b, v0.8h, #3
+sqrshrun2 v0.4s, v0.2d, #3
+sqrshrun2 v0.8h, v0.4s, #3
+sqshl b11, b19, #7
+sqshl d15, d16, #51
+sqshl d31, d31, d31
+sqshl h13, h18, #11
+sqshl h3, h4, h15
+sqshl s14, s17, #22
+sqshl v0.16b, v0.16b, #3
+sqshl v0.2d, v0.2d, #3
+sqshl v0.2s, v0.2s, #3
+sqshl v0.2s, v0.2s, v0.2s
+sqshl v0.4h, v0.4h, #3
+sqshl v0.4h, v0.4h, v0.4h
+sqshl v0.4s, v0.4s, #3
+sqshl v0.8b, v0.8b, #3
+sqshl v0.8b, v0.8b, v0.8b
+sqshl v0.8h, v0.8h, #3
+sqshlu b15, b18, #6
+sqshlu d11, d13, #32
+sqshlu h19, h17, #6
+sqshlu s16, s14, #25
+sqshlu v0.16b, v0.16b, #3
+sqshlu v0.2d, v0.2d, #3
+sqshlu v0.2s, v0.2s, #3
+sqshlu v0.4h, v0.4h, #3
+sqshlu v0.4s, v0.4s, #3
+sqshlu v0.8b, v0.8b, #3
+sqshlu v0.8h, v0.8h, #3
+sqshrn b10, h15, #5
+sqshrn h17, s10, #4
+sqshrn s18, d10, #31
+sqshrn v0.2s, v0.2d, #3
+sqshrn v0.4h, v0.4s, #3
+sqshrn v0.8b, v0.8h, #3
+sqshrn2 v0.16b, v0.8h, #3
+sqshrn2 v0.4s, v0.2d, #3
+sqshrn2 v0.8h, v0.4s, #3
+sqshrun b15, h10, #7
+sqshrun h20, s14, #3
+sqshrun s10, d15, #15
+sqshrun v0.2s, v0.2d, #3
+sqshrun v0.4h, v0.4s, #3
+sqshrun v0.8b, v0.8h, #3
+sqshrun2 v0.16b, v0.8h, #3
+sqshrun2 v0.4s, v0.2d, #3
+sqshrun2 v0.8h, v0.4s, #3
+sqsub s20, s10, s7
+sqsub v0.2d, v0.2d, v0.2d
+sqsub v0.4s, v0.4s, v0.4s
+sqsub v0.8b, v0.8b, v0.8b
+sqxtn b18, h18
+sqxtn h20, s17
+sqxtn s19, d14
+sqxtn v0.2s, v0.2d
+sqxtn v0.4h, v0.4s
+sqxtn v0.8b, v0.8h
+sqxtn2 v0.16b, v0.8h
+sqxtn2 v0.4s, v0.2d
+sqxtn2 v0.8h, v0.4s
+sqxtun b19, h14
+sqxtun h21, s15
+sqxtun s20, d12
+sqxtun v0.2s, v0.2d
+sqxtun v0.4h, v0.4s
+sqxtun v0.8b, v0.8h
+sqxtun2 v0.16b, v0.8h
+sqxtun2 v0.4s, v0.2d
+sqxtun2 v0.8h, v0.4s
+srhadd v0.2s, v0.2s, v0.2s
+srhadd v0.4h, v0.4h, v0.4h
+srhadd v0.8b, v0.8b, v0.8b
+sri d10, d12, #14
+sri v0.16b, v0.16b, #3
+sri v0.2d, v0.2d, #3
+sri v0.2s, v0.2s, #3
+sri v0.4h, v0.4h, #3
+sri v0.4s, v0.4s, #3
+sri v0.8b, v0.8b, #3
+sri v0.8h, v0.8h, #3
+srshl d16, d16, d16
+srshl v0.2s, v0.2s, v0.2s
+srshl v0.4h, v0.4h, v0.4h
+srshl v0.8b, v0.8b, v0.8b
+srshr d19, d18, #7
+srshr v0.16b, v0.16b, #3
+srshr v0.2d, v0.2d, #3
+srshr v0.2s, v0.2s, #3
+srshr v0.4h, v0.4h, #3
+srshr v0.4s, v0.4s, #3
+srshr v0.8b, v0.8b, #3
+srshr v0.8h, v0.8h, #3
+srsra d15, d11, #19
+srsra v0.16b, v0.16b, #3
+srsra v0.2d, v0.2d, #3
+srsra v0.2s, v0.2s, #3
+srsra v0.4h, v0.4h, #3
+srsra v0.4s, v0.4s, #3
+srsra v0.8b, v0.8b, #3
+srsra v0.8h, v0.8h, #3
+sshl d31, d31, d31
+sshl v0.2d, v0.2d, v0.2d
+sshl v0.2s, v0.2s, v0.2s
+sshl v0.4h, v0.4h, v0.4h
+sshl v0.8b, v0.8b, v0.8b
+sshll v0.2d, v0.2s, #3
+sshll2 v0.4s, v0.8h, #3
+sshr d15, d16, #12
+sshr v0.16b, v0.16b, #3
+sshr v0.2d, v0.2d, #3
+sshr v0.2s, v0.2s, #3
+sshr v0.4h, v0.4h, #3
+sshr v0.4s, v0.4s, #3
+sshr v0.8b, v0.8b, #3
+sshr v0.8h, v0.8h, #3
+ssra d18, d12, #21
+ssra v0.16b, v0.16b, #3
+ssra v0.2d, v0.2d, #3
+ssra v0.2s, v0.2s, #3
+ssra v0.4h, v0.4h, #3
+ssra v0.4s, v0.4s, #3
+ssra v0.8b, v0.8b, #3
+ssra v0.8h, v0.8h, #3
+ssubl v0.2d, v0.2s, v0.2s
+ssubl v0.4s, v0.4h, v0.4h
+ssubl v0.8h, v0.8b, v0.8b
+ssubl2 v0.2d, v0.4s, v0.4s
+ssubl2 v0.4s, v0.8h, v0.8h
+ssubl2 v0.8h, v0.16b, v0.16b
+ssubw v0.2d, v0.2d, v0.2s
+ssubw v0.4s, v0.4s, v0.4h
+ssubw v0.8h, v0.8h, v0.8b
+ssubw2 v0.2d, v0.2d, v0.4s
+ssubw2 v0.4s, v0.4s, v0.8h
+ssubw2 v0.8h, v0.8h, v0.16b
+st1 { v0.16b }, [x0]
+st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+st1 { v0.4s, v1.4s }, [sp], #32
+st1 { v0.4s, v1.4s, v2.4s }, [sp]
+st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+st1 { v0.8h }, [x15], x2
+st1 { v0.8h, v1.8h }, [x15]
+st1 { v0.d }[1], [x0]
+st1 { v0.d }[1], [x0], #8
+st2 { v0.16b, v1.16b }, [x0], x1
+st2 { v0.8b, v1.8b }, [x0]
+st2 { v0.s, v1.s }[3], [sp]
+st2 { v0.s, v1.s }[3], [sp], #8
+st3 { v0.4h, v1.4h, v2.4h }, [x15]
+st3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+st3 { v0.h, v1.h, v2.h }[7], [x15]
+st3 { v0.h, v1.h, v2.h }[7], [x15], #6
+st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
+st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
+sub d15, d5, d16
+sub v0.2d, v0.2d, v0.2d
+suqadd b19, b14
+suqadd d18, d22
+suqadd h20, h15
+suqadd s21, s12
+suqadd v0.16b, v0.16b
+suqadd v0.2d, v0.2d
+suqadd v0.2s, v0.2s
+suqadd v0.4h, v0.4h
+suqadd v0.4s, v0.4s
+suqadd v0.8b, v0.8b
+suqadd v0.8h, v0.8h
+tbl v0.16b, { v0.16b }, v0.16b
+tbl v0.16b, { v0.16b, v1.16b }, v0.16b
+tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+tbl v0.8b, { v0.16b }, v0.8b
+tbl v0.8b, { v0.16b, v1.16b }, v0.8b
+tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+tbx v0.16b, { v0.16b }, v0.16b
+tbx v0.16b, { v0.16b, v1.16b }, v0.16b
+tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+tbx v0.8b, { v0.16b }, v0.8b
+tbx v0.8b, { v0.16b, v1.16b }, v0.8b
+tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+trn1 v0.16b, v0.16b, v0.16b
+trn1 v0.2d, v0.2d, v0.2d
+trn1 v0.2s, v0.2s, v0.2s
+trn1 v0.4h, v0.4h, v0.4h
+trn1 v0.4s, v0.4s, v0.4s
+trn1 v0.8b, v0.8b, v0.8b
+trn1 v0.8h, v0.8h, v0.8h
+trn2 v0.16b, v0.16b, v0.16b
+trn2 v0.2d, v0.2d, v0.2d
+trn2 v0.2s, v0.2s, v0.2s
+trn2 v0.4h, v0.4h, v0.4h
+trn2 v0.4s, v0.4s, v0.4s
+trn2 v0.8b, v0.8b, v0.8b
+trn2 v0.8h, v0.8h, v0.8h
+uaba v0.8b, v0.8b, v0.8b
+uabal v0.2d, v0.2s, v0.2s
+uabal v0.4s, v0.4h, v0.4h
+uabal v0.8h, v0.8b, v0.8b
+uabal2 v0.2d, v0.4s, v0.4s
+uabal2 v0.4s, v0.8h, v0.8h
+uabal2 v0.8h, v0.16b, v0.16b
+uabd v0.4h, v0.4h, v0.4h
+uabdl v0.2d, v0.2s, v0.2s
+uabdl v0.4s, v0.4h, v0.4h
+uabdl v0.8h, v0.8b, v0.8b
+uabdl2 v0.2d, v0.4s, v0.4s
+uabdl2 v0.4s, v0.8h, v0.8h
+uabdl2 v0.8h, v0.16b, v0.16b
+uadalp v0.1d, v0.2s
+uadalp v0.2d, v0.4s
+uadalp v0.2s, v0.4h
+uadalp v0.4h, v0.8b
+uadalp v0.4s, v0.8h
+uadalp v0.8h, v0.16b
+uaddl v0.2d, v0.2s, v0.2s
+uaddl v0.4s, v0.4h, v0.4h
+uaddl v0.8h, v0.8b, v0.8b
+uaddl2 v0.2d, v0.4s, v0.4s
+uaddl2 v0.4s, v0.8h, v0.8h
+uaddl2 v0.8h, v0.16b, v0.16b
+uaddlp v0.1d, v0.2s
+uaddlp v0.2d, v0.4s
+uaddlp v0.2s, v0.4h
+uaddlp v0.4h, v0.8b
+uaddlp v0.4s, v0.8h
+uaddlp v0.8h, v0.16b
+uaddw v0.2d, v0.2d, v0.2s
+uaddw v0.4s, v0.4s, v0.4h
+uaddw v0.8h, v0.8h, v0.8b
+uaddw2 v0.2d, v0.2d, v0.4s
+uaddw2 v0.4s, v0.4s, v0.8h
+uaddw2 v0.8h, v0.8h, v0.16b
+ucvtf d21, d14
+ucvtf d21, d14, #64
+ucvtf s22, s13
+ucvtf s22, s13, #32
+ucvtf v0.2d, v0.2d
+ucvtf v0.2d, v0.2d, #3
+ucvtf v0.2s, v0.2s
+ucvtf v0.2s, v0.2s, #3
+ucvtf v0.4h, v0.4h
+ucvtf v0.4s, v0.4s
+ucvtf v0.4s, v0.4s, #3
+ucvtf v0.8h, v0.8h
+uhadd v0.16b, v0.16b, v0.16b
+uhadd v0.8h, v0.8h, v0.8h
+uhsub v0.4s, v0.4s, v0.4s
+umax v0.16b, v0.16b, v0.16b
+umax v0.4s, v0.4s, v0.4s
+umax v0.8h, v0.8h, v0.8h
+umaxp v0.16b, v0.16b, v0.16b
+umaxp v0.4s, v0.4s, v0.4s
+umaxp v0.8h, v0.8h, v0.8h
+umin v0.2s, v0.2s, v0.2s
+umin v0.4h, v0.4h, v0.4h
+umin v0.8b, v0.8b, v0.8b
+uminp v0.2s, v0.2s, v0.2s
+uminp v0.4h, v0.4h, v0.4h
+uminp v0.8b, v0.8b, v0.8b
+umlal v0.2d, v0.2s, v0.2s
+umlal v0.4s, v0.4h, v0.4h
+umlal v0.8h, v0.8b, v0.8b
+umlal2 v0.2d, v0.4s, v0.4s
+umlal2 v0.4s, v0.8h, v0.8h
+umlal2 v0.8h, v0.16b, v0.16b
+umlsl v0.2d, v0.2s, v0.2s
+umlsl v0.4s, v0.4h, v0.4h
+umlsl v0.8h, v0.8b, v0.8b
+umlsl2 v0.2d, v0.4s, v0.4s
+umlsl2 v0.4s, v0.8h, v0.8h
+umlsl2 v0.8h, v0.16b, v0.16b
+umull v0.2d, v0.2s, v0.2s
+umull v0.4s, v0.4h, v0.4h
+umull v0.8h, v0.8b, v0.8b
+umull2 v0.2d, v0.4s, v0.4s
+umull2 v0.4s, v0.8h, v0.8h
+umull2 v0.8h, v0.16b, v0.16b
+uqadd h0, h1, h5
+uqadd v0.8h, v0.8h, v0.8h
+uqrshl b11, b20, b30
+uqrshl s23, s20, s16
+uqrshl v0.16b, v0.16b, v0.16b
+uqrshl v0.4s, v0.4s, v0.4s
+uqrshl v0.4s, v0.4s, v0.4s
+uqrshl v0.8h, v0.8h, v0.8h
+uqrshrn b10, h12, #5
+uqrshrn h12, s10, #14
+uqrshrn s10, d10, #25
+uqrshrn v0.2s, v0.2d, #3
+uqrshrn v0.4h, v0.4s, #3
+uqrshrn v0.8b, v0.8h, #3
+uqrshrn2 v0.16b, v0.8h, #3
+uqrshrn2 v0.4s, v0.2d, #3
+uqrshrn2 v0.8h, v0.4s, #3
+uqshl b11, b20, b30
+uqshl b18, b15, #6
+uqshl d15, d12, #19
+uqshl h11, h18, #7
+uqshl s14, s19, #18
+uqshl s23, s20, s16
+uqshl v0.16b, v0.16b, #3
+uqshl v0.16b, v0.16b, v0.16b
+uqshl v0.2d, v0.2d, #3
+uqshl v0.2d, v0.2d, v0.2d
+uqshl v0.2s, v0.2s, #3
+uqshl v0.4h, v0.4h, #3
+uqshl v0.4s, v0.4s, #3
+uqshl v0.4s, v0.4s, v0.4s
+uqshl v0.8b, v0.8b, #3
+uqshl v0.8h, v0.8h, #3
+uqshl v0.8h, v0.8h, v0.8h
+uqshrn b12, h10, #7
+uqshrn h10, s14, #5
+uqshrn s10, d12, #13
+uqshrn v0.2s, v0.2d, #3
+uqshrn v0.4h, v0.4s, #3
+uqshrn v0.8b, v0.8h, #3
+uqshrn2 v0.16b, v0.8h, #3
+uqshrn2 v0.4s, v0.2d, #3
+uqshrn2 v0.8h, v0.4s, #3
+uqsub d16, d16, d16
+uqsub v0.4h, v0.4h, v0.4h
+uqxtn b18, h18
+uqxtn h20, s17
+uqxtn s19, d14
+uqxtn v0.2s, v0.2d
+uqxtn v0.4h, v0.4s
+uqxtn v0.8b, v0.8h
+uqxtn2 v0.16b, v0.8h
+uqxtn2 v0.4s, v0.2d
+uqxtn2 v0.8h, v0.4s
+urecpe v0.2s, v0.2s
+urecpe v0.4s, v0.4s
+urhadd v0.16b, v0.16b, v0.16b
+urhadd v0.4s, v0.4s, v0.4s
+urhadd v0.8h, v0.8h, v0.8h
+urshl d8, d7, d4
+urshl v0.16b, v0.16b, v0.16b
+urshl v0.2d, v0.2d, v0.2d
+urshl v0.4s, v0.4s, v0.4s
+urshl v0.8h, v0.8h, v0.8h
+urshr d20, d23, #31
+urshr v0.16b, v0.16b, #3
+urshr v0.2d, v0.2d, #3
+urshr v0.2s, v0.2s, #3
+urshr v0.4h, v0.4h, #3
+urshr v0.4s, v0.4s, #3
+urshr v0.8b, v0.8b, #3
+urshr v0.8h, v0.8h, #3
+ursqrte v0.2s, v0.2s
+ursqrte v0.4s, v0.4s
+ursra d18, d10, #13
+ursra v0.16b, v0.16b, #3
+ursra v0.2d, v0.2d, #3
+ursra v0.2s, v0.2s, #3
+ursra v0.4h, v0.4h, #3
+ursra v0.4s, v0.4s, #3
+ursra v0.8b, v0.8b, #3
+ursra v0.8h, v0.8h, #3
+ushl d0, d0, d0
+ushl v0.16b, v0.16b, v0.16b
+ushl v0.4s, v0.4s, v0.4s
+ushl v0.8h, v0.8h, v0.8h
+ushll v0.4s, v0.4h, #3
+ushll2 v0.8h, v0.16b, #3
+ushr d10, d17, #18
+ushr v0.16b, v0.16b, #3
+ushr v0.2d, v0.2d, #3
+ushr v0.2s, v0.2s, #3
+ushr v0.4h, v0.4h, #3
+ushr v0.4s, v0.4s, #3
+ushr v0.8b, v0.8b, #3
+ushr v0.8h, v0.8h, #3
+usqadd b19, b14
+usqadd d18, d22
+usqadd h20, h15
+usqadd s21, s12
+usqadd v0.16b, v0.16b
+usqadd v0.2d, v0.2d
+usqadd v0.2s, v0.2s
+usqadd v0.4h, v0.4h
+usqadd v0.4s, v0.4s
+usqadd v0.8b, v0.8b
+usqadd v0.8h, v0.8h
+usra d20, d13, #61
+usra v0.16b, v0.16b, #3
+usra v0.2d, v0.2d, #3
+usra v0.2s, v0.2s, #3
+usra v0.4h, v0.4h, #3
+usra v0.4s, v0.4s, #3
+usra v0.8b, v0.8b, #3
+usra v0.8h, v0.8h, #3
+usubl v0.2d, v0.2s, v0.2s
+usubl v0.4s, v0.4h, v0.4h
+usubl v0.8h, v0.8b, v0.8b
+usubl2 v0.2d, v0.4s, v0.4s
+usubl2 v0.4s, v0.8h, v0.8h
+usubl2 v0.8h, v0.16b, v0.16b
+usubw v0.2d, v0.2d, v0.2s
+usubw v0.4s, v0.4s, v0.4h
+usubw v0.8h, v0.8h, v0.8b
+usubw2 v0.2d, v0.2d, v0.4s
+usubw2 v0.4s, v0.4s, v0.8h
+usubw2 v0.8h, v0.8h, v0.16b
+uzp1 v0.16b, v0.16b, v0.16b
+uzp1 v0.2d, v0.2d, v0.2d
+uzp1 v0.2s, v0.2s, v0.2s
+uzp1 v0.4h, v0.4h, v0.4h
+uzp1 v0.4s, v0.4s, v0.4s
+uzp1 v0.8b, v0.8b, v0.8b
+uzp1 v0.8h, v0.8h, v0.8h
+uzp2 v0.16b, v0.16b, v0.16b
+uzp2 v0.2d, v0.2d, v0.2d
+uzp2 v0.2s, v0.2s, v0.2s
+uzp2 v0.4h, v0.4h, v0.4h
+uzp2 v0.4s, v0.4s, v0.4s
+uzp2 v0.8b, v0.8b, v0.8b
+uzp2 v0.8h, v0.8h, v0.8h
+xtn v0.2s, v0.2d
+xtn v0.4h, v0.4s
+xtn v0.8b, v0.8h
+xtn2 v0.16b, v0.8h
+xtn2 v0.4s, v0.2d
+xtn2 v0.8h, v0.4s
+zip1 v0.16b, v0.16b, v0.16b
+zip1 v0.2d, v0.2d, v0.2d
+zip1 v0.2s, v0.2s, v0.2s
+zip1 v0.4h, v0.4h, v0.4h
+zip1 v0.4s, v0.4s, v0.4s
+zip1 v0.8b, v0.8b, v0.8b
+zip1 v0.8h, v0.8h, v0.8h
+zip2 v0.16b, v0.16b, v0.16b
+zip2 v0.2d, v0.2d, v0.2d
+zip2 v0.2s, v0.2s, v0.2s
+zip2 v0.4h, v0.4h, v0.4h
+zip2 v0.4s, v0.4s, v0.4s
+zip2 v0.8b, v0.8b, v0.8b
+zip2 v0.8h, v0.8h, v0.8h
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.50 abs d29, d24
+# CHECK-NEXT: 1 2 0.50 abs v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 abs v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 abs v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 abs v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 abs v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 abs v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 abs v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 add d17, d31, d29
+# CHECK-NEXT: 1 2 0.50 add v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 2 6 1.00 addhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 addhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 2 6 1.00 addhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 addhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 addhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 addhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 addp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 addp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 and v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 bic v0.4h, #15, lsl #8
+# CHECK-NEXT: 1 2 0.50 bic v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 bif v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 bit v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 bsl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 cls v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 cls v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 cls v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 cls v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 cls v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 cls v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 clz v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 clz v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 clz v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 clz v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 clz v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 clz v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 cmeq d20, d21, #0
+# CHECK-NEXT: 1 2 0.50 cmeq d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmeq v0.16b, v0.16b, #0
+# CHECK-NEXT: 1 2 0.50 cmeq v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 cmge d20, d21, #0
+# CHECK-NEXT: 1 2 0.50 cmge d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmge v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 cmge v0.8b, v0.8b, #0
+# CHECK-NEXT: 1 2 0.50 cmgt d20, d21, #0
+# CHECK-NEXT: 1 2 0.50 cmgt d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmgt v0.2s, v0.2s, #0
+# CHECK-NEXT: 1 2 0.50 cmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 cmhi d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmhi v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 cmhs d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmhs v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 cmle d20, d21, #0
+# CHECK-NEXT: 1 2 0.50 cmle v0.2d, v0.2d, #0
+# CHECK-NEXT: 1 2 0.50 cmlt d20, d21, #0
+# CHECK-NEXT: 1 2 0.50 cmlt v0.8h, v0.8h, #0
+# CHECK-NEXT: 1 2 0.50 cmtst d20, d21, d22
+# CHECK-NEXT: 1 2 0.50 cmtst v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 cnt v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 cnt v0.8b, v0.8b
+# CHECK-NEXT: 1 5 1.00 dup v0.16b, w28
+# CHECK-NEXT: 1 5 1.00 dup v0.2d, x28
+# CHECK-NEXT: 1 5 1.00 dup v0.2s, w28
+# CHECK-NEXT: 1 5 1.00 dup v0.4h, w28
+# CHECK-NEXT: 1 5 1.00 dup v0.4s, w28
+# CHECK-NEXT: 1 5 1.00 dup v0.8b, w28
+# CHECK-NEXT: 1 5 1.00 dup v0.8h, w28
+# CHECK-NEXT: 1 2 0.50 eor v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 ext v0.16b, v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 ext v0.8b, v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 fabd d29, d24, d20
+# CHECK-NEXT: 1 3 0.50 fabd s29, s24, s20
+# CHECK-NEXT: 1 3 0.50 fabd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fabs v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fabs v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fabs v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fabs v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fabs v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 facge d20, d21, d22
+# CHECK-NEXT: 1 3 0.50 facge s10, s11, s12
+# CHECK-NEXT: 1 3 0.50 facge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 facgt d20, d21, d22
+# CHECK-NEXT: 1 3 0.50 facgt s10, s11, s12
+# CHECK-NEXT: 1 3 0.50 facgt v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 faddp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 faddp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcmeq d20, d21, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmeq d20, d21, d22
+# CHECK-NEXT: 1 3 0.50 fcmeq s10, s11, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmeq s10, s11, s12
+# CHECK-NEXT: 1 3 0.50 fcmeq v0.2s, v0.2s, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmeq v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcmge d20, d21, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmge d20, d21, d22
+# CHECK-NEXT: 1 3 0.50 fcmge s10, s11, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmge s10, s11, s12
+# CHECK-NEXT: 1 3 0.50 fcmge v0.2d, v0.2d, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcmgt d20, d21, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmgt d20, d21, d22
+# CHECK-NEXT: 1 3 0.50 fcmgt s10, s11, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmgt s10, s11, s12
+# CHECK-NEXT: 1 3 0.50 fcmgt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcmle d20, d21, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmle s10, s11, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmle v0.2d, v0.2d, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmlt d20, d21, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmlt s10, s11, #0.0
+# CHECK-NEXT: 1 3 0.50 fcmlt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: 1 3 0.50 fcvtas d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtas s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtas v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtas v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtas v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtas v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtas v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtau d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtau s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtau v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtau v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtau v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtau v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtau v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtl v0.2d, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtl v0.4s, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtl2 v0.2d, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtl2 v0.4s, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtms d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtms s22, s13
+# CHECK-NEXT: 1 3 0.50 fcvtms v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtms v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtms v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtms v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtms v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtmu d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtmu s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtmu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtmu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtmu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtmu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtmu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtn v0.2s, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtn v0.4h, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtns d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtns s22, s13
+# CHECK-NEXT: 1 3 0.50 fcvtns v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtns v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtns v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtns v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtns v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtnu d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtnu s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtnu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtnu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtnu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtnu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtnu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtps d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtps s22, s13
+# CHECK-NEXT: 1 3 0.50 fcvtps v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtps v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtps v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtps v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtps v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtpu d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtpu s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtpu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtpu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtpu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtpu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtpu v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtxn s22, d13
+# CHECK-NEXT: 1 3 0.50 fcvtxn v0.2s, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtxn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtzs d21, d12, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtzs s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtzs s21, s12, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzs v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fcvtzu d21, d12, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu d21, d14
+# CHECK-NEXT: 1 3 0.50 fcvtzu s12, s13
+# CHECK-NEXT: 1 3 0.50 fcvtzu s21, s12, #1
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 fcvtzu v0.8h, v0.8h
+# CHECK-NEXT: 1 12 1.00 fdiv v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmax v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fmax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fmaxnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fmaxnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmaxnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fmaxnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fmaxnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmaxnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fmaxp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fmaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fmin v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fmin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fmin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fminnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fminnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fminnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fminnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fminnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fminnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fminp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.50 fmla d0, d1, v0.d[1]
+# CHECK-NEXT: 1 4 0.50 fmla s0, s1, v0.s[3]
+# CHECK-NEXT: 1 4 0.50 fmla v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 fmls d0, d4, v0.d[1]
+# CHECK-NEXT: 1 4 0.50 fmls s3, s5, v0.s[3]
+# CHECK-NEXT: 1 4 0.50 fmls v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 fmov v0.2d, #-1.25000000
+# CHECK-NEXT: 1 2 0.50 fmov v0.2s, #13.00000000
+# CHECK-NEXT: 1 2 0.50 fmov v0.4s, #1.00000000
+# CHECK-NEXT: 1 4 0.50 fmul d0, d1, v0.d[1]
+# CHECK-NEXT: 1 4 0.50 fmul s0, s1, v0.s[3]
+# CHECK-NEXT: 1 4 0.50 fmul v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 fmulx d0, d4, v0.d[1]
+# CHECK-NEXT: 1 4 0.50 fmulx d23, d11, d1
+# CHECK-NEXT: 1 4 0.50 fmulx s20, s22, s15
+# CHECK-NEXT: 1 4 0.50 fmulx s3, s5, v0.s[3]
+# CHECK-NEXT: 1 4 0.50 fmulx v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 4 0.50 fmulx v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 fmulx v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fneg v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 fneg v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 fneg v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 fneg v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 fneg v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 frecpe d13, d13
+# CHECK-NEXT: 2 6 1.00 frecpe s19, s14
+# CHECK-NEXT: 2 6 1.00 frecpe v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 frecpe v0.2s, v0.2s
+# CHECK-NEXT: 2 6 1.00 frecpe v0.4h, v0.4h
+# CHECK-NEXT: 2 6 1.00 frecpe v0.4s, v0.4s
+# CHECK-NEXT: 2 6 1.00 frecpe v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frecps v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frecps d22, d30, d21
+# CHECK-NEXT: 1 3 0.50 frecps s21, s16, s13
+# CHECK-NEXT: 1 3 0.50 frecpx d16, d19
+# CHECK-NEXT: 1 3 0.50 frecpx s18, s10
+# CHECK-NEXT: 1 3 0.50 frinta v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frinta v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frinta v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frinta v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frinta v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frinti v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frinti v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frinti v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frinti v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frinti v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frintm v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frintm v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frintm v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frintm v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frintm v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frintn v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frintn v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frintn v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frintn v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frintn v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frintp v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frintp v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frintp v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frintp v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frintp v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frintx v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frintx v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frintx v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frintx v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frintx v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frintz v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 frintz v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 frintz v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 frintz v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 frintz v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 frsqrte d21, d12
+# CHECK-NEXT: 2 6 1.00 frsqrte s22, s13
+# CHECK-NEXT: 2 6 1.00 frsqrte v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 frsqrte v0.2s, v0.2s
+# CHECK-NEXT: 2 6 1.00 frsqrte v0.4h, v0.4h
+# CHECK-NEXT: 2 6 1.00 frsqrte v0.4s, v0.4s
+# CHECK-NEXT: 2 6 1.00 frsqrte v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 frsqrts d8, d22, d18
+# CHECK-NEXT: 1 3 0.50 frsqrts s21, s5, s12
+# CHECK-NEXT: 1 3 0.50 frsqrts v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 63 1.00 fsqrt v0.2d, v0.2d
+# CHECK-NEXT: 1 33 1.00 fsqrt v0.2s, v0.2s
+# CHECK-NEXT: 1 39 1.00 fsqrt v0.4h, v0.4h
+# CHECK-NEXT: 1 33 1.00 fsqrt v0.4s, v0.4s
+# CHECK-NEXT: 1 39 1.00 fsqrt v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 fsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 4 0.50 * ld1 { v0.16b }, [x0]
+# CHECK-NEXT: 3 5 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: 4 5 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: 2 4 1.00 * ld1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 3 5 1.50 * ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: 4 5 2.00 * ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: 1 4 0.50 * ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 2 4 1.00 * ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 2 6 0.50 * ld1 { v0.b }[9], [x0]
+# CHECK-NEXT: 2 6 0.50 * ld1 { v0.b }[9], [x0], #1
+# CHECK-NEXT: 2 6 0.50 * ld1r { v0.16b }, [x0]
+# CHECK-NEXT: 2 6 0.50 * ld1r { v0.16b }, [x0], #1
+# CHECK-NEXT: 2 6 0.50 * ld1r { v0.8h }, [x15]
+# CHECK-NEXT: 2 6 0.50 * ld1r { v0.8h }, [x15], #2
+# CHECK-NEXT: 4 6 1.00 * ld2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: 5 8 1.50 * ld2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: 4 6 1.00 * ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: 4 6 1.00 * ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: 4 6 1.00 * ld2r { v0.2d, v1.2d }, [x0]
+# CHECK-NEXT: 4 6 1.00 * ld2r { v0.2d, v1.2d }, [x0], #16
+# CHECK-NEXT: 4 6 1.00 * ld2r { v0.4s, v1.4s }, [sp]
+# CHECK-NEXT: 4 6 1.00 * ld2r { v0.4s, v1.4s }, [sp], #8
+# CHECK-NEXT: 6 9 1.50 * ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 6 8 1.50 * ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: 6 7 1.50 * ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: 6 7 1.50 * ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: 6 7 1.50 * ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 6 7 1.50 * ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: 6 7 1.50 * ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: 6 7 1.50 * ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: 12 11 2.00 * ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 12 10 2.00 * ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: 8 7 2.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: 8 7 2.00 * ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: 8 7 2.00 * ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: 4 5 2.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: 4 5 2.00 * ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: 8 7 2.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 8 7 2.00 * ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: 1 3 0.50 mla v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 mls v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 mov b0, v0.b[15]
+# CHECK-NEXT: 1 3 0.50 mov d6, v0.d[1]
+# CHECK-NEXT: 1 3 0.50 mov h2, v0.h[5]
+# CHECK-NEXT: 1 3 0.50 mov s17, v0.s[2]
+# CHECK-NEXT: 1 2 0.50 mov v2.b[0], v0.b[0]
+# CHECK-NEXT: 1 2 0.50 mov v2.h[1], v0.h[1]
+# CHECK-NEXT: 1 2 0.50 mov v2.s[2], v0.s[2]
+# CHECK-NEXT: 1 2 0.50 mov v2.d[1], v0.d[1]
+# CHECK-NEXT: 2 7 1.00 mov v0.b[0], w8
+# CHECK-NEXT: 2 7 1.00 mov v0.h[1], w8
+# CHECK-NEXT: 2 7 1.00 mov v0.s[2], w8
+# CHECK-NEXT: 2 7 1.00 mov v0.d[1], x8
+# CHECK-NEXT: 1 2 0.50 mov v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 mov v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 movi d15, #0xff00ff00ff00ff
+# CHECK-NEXT: 1 2 0.50 movi v0.16b, #31
+# CHECK-NEXT: 1 2 0.50 movi v0.2d, #0xff0000ff0000ffff
+# CHECK-NEXT: 1 2 0.50 movi v0.2s, #8, msl #8
+# CHECK-NEXT: 1 2 0.50 movi v0.4s, #255, lsl #24
+# CHECK-NEXT: 1 2 0.50 movi v0.8b, #255
+# CHECK-NEXT: 1 3 0.50 mul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 mvni v0.2s, #0
+# CHECK-NEXT: 1 2 0.50 mvni v0.4s, #16, msl #16
+# CHECK-NEXT: 1 3 0.50 neg d29, d24
+# CHECK-NEXT: 1 3 0.50 neg v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 neg v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 neg v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 neg v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 neg v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 neg v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 neg v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 mvn v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 mvn v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 orn v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 mov v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 orr v0.8h, #31
+# CHECK-NEXT: 1 2 0.50 pmul v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 pmul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 pmull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 pmull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 2 6 1.00 raddhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 raddhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 2 6 1.00 raddhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 raddhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 raddhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 raddhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 rbit v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 rbit v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 rev16 v21.8b, v1.8b
+# CHECK-NEXT: 1 2 0.50 rev16 v30.16b, v31.16b
+# CHECK-NEXT: 1 2 0.50 rev32 v0.4h, v9.4h
+# CHECK-NEXT: 1 2 0.50 rev32 v21.8b, v1.8b
+# CHECK-NEXT: 1 2 0.50 rev32 v30.16b, v31.16b
+# CHECK-NEXT: 1 2 0.50 rev32 v4.8h, v7.8h
+# CHECK-NEXT: 1 2 0.50 rev64 v0.16b, v31.16b
+# CHECK-NEXT: 1 2 0.50 rev64 v1.8b, v9.8b
+# CHECK-NEXT: 1 2 0.50 rev64 v13.4h, v21.4h
+# CHECK-NEXT: 1 2 0.50 rev64 v2.8h, v4.8h
+# CHECK-NEXT: 1 2 0.50 rev64 v4.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 rev64 v6.4s, v8.4s
+# CHECK-NEXT: 2 6 1.00 rshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 rshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 2 6 1.00 rshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 rshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 rshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 rshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 2 6 1.00 rsubhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 rsubhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 2 6 1.00 rsubhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 rsubhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 2 6 1.00 rsubhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 2 6 1.00 rsubhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 saba v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sadalp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.50 sadalp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 sadalp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.50 sadalp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.50 sadalp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 sadalp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 saddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 saddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 saddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 saddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 saddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 saddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 saddlp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.50 saddlp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 saddlp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.50 saddlp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.50 saddlp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 saddlp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 saddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.50 saddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.50 saddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.50 saddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 saddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 saddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 3 0.50 scvtf d21, d12
+# CHECK-NEXT: 1 3 0.50 scvtf d21, d12, #64
+# CHECK-NEXT: 1 3 0.50 scvtf s22, s13
+# CHECK-NEXT: 1 3 0.50 scvtf s22, s13, #32
+# CHECK-NEXT: 1 3 0.50 scvtf v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 scvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 scvtf v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 scvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 scvtf v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 scvtf v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 scvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 scvtf v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 shadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 shl d7, d10, #12
+# CHECK-NEXT: 1 3 0.50 shl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 shl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 shl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 shl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 shll v0.2d, v0.2s, #32
+# CHECK-NEXT: 1 3 0.50 shll v0.4s, v0.4h, #16
+# CHECK-NEXT: 1 3 0.50 shll v0.8h, v0.8b, #8
+# CHECK-NEXT: 1 3 0.50 shll v0.2d, v0.2s, #32
+# CHECK-NEXT: 1 3 0.50 shll v0.4s, v0.4h, #16
+# CHECK-NEXT: 1 3 0.50 shll v0.8h, v0.8b, #8
+# CHECK-NEXT: 1 3 0.50 shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: 1 3 0.50 shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: 1 3 0.50 shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: 1 3 0.50 shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: 1 3 0.50 shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: 1 3 0.50 shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: 2 6 1.00 shrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 shrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 2 6 1.00 shrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 shrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 shrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 shrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 shsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 shsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sli d10, d14, #12
+# CHECK-NEXT: 1 3 0.50 sli v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 sli v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 smax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 smax v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 smax v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 smaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 smaxp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 smaxp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 smin v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 smin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 smin v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sminp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sminp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 smlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 smlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 smlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 smlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 smlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 smlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 smlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 smlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 smlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 smlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 smlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 smlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 smull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 smull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 smull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 smull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 smull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 smull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sqabs b19, b14
+# CHECK-NEXT: 1 2 0.50 sqabs d18, d12
+# CHECK-NEXT: 1 2 0.50 sqabs h21, h15
+# CHECK-NEXT: 1 2 0.50 sqabs s20, s12
+# CHECK-NEXT: 1 2 0.50 sqabs v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sqabs v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqabs v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sqabs v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sqabs v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqabs v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sqabs v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqadd b20, b11, b15
+# CHECK-NEXT: 1 2 0.50 sqadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sqadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sqdmlal d19, s24, s12
+# CHECK-NEXT: 1 3 0.50 sqdmlal d8, s9, v0.s[1]
+# CHECK-NEXT: 1 3 0.50 sqdmlal s0, h0, v0.h[3]
+# CHECK-NEXT: 1 3 0.50 sqdmlal s17, h27, h12
+# CHECK-NEXT: 1 3 0.50 sqdmlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sqdmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sqdmlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 sqdmlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 sqdmlsl d12, s23, s13
+# CHECK-NEXT: 1 3 0.50 sqdmlsl d8, s9, v0.s[1]
+# CHECK-NEXT: 1 3 0.50 sqdmlsl s0, h0, v0.h[3]
+# CHECK-NEXT: 1 3 0.50 sqdmlsl s14, h12, h25
+# CHECK-NEXT: 1 3 0.50 sqdmlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sqdmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sqdmlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 sqdmlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 sqdmulh h10, h11, h12
+# CHECK-NEXT: 1 3 0.50 sqdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: 1 3 0.50 sqdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: 1 3 0.50 sqdmulh s20, s21, s2
+# CHECK-NEXT: 1 3 0.50 sqdmulh v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sqdmulh v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 sqdmull d1, s1, v0.s[1]
+# CHECK-NEXT: 1 3 0.50 sqdmull d15, s22, s12
+# CHECK-NEXT: 1 3 0.50 sqdmull s1, h1, v0.h[3]
+# CHECK-NEXT: 1 3 0.50 sqdmull s12, h22, h12
+# CHECK-NEXT: 1 3 0.50 sqdmull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sqdmull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sqdmull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 sqdmull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqneg b19, b14
+# CHECK-NEXT: 1 2 0.50 sqneg d18, d12
+# CHECK-NEXT: 1 2 0.50 sqneg h21, h15
+# CHECK-NEXT: 1 2 0.50 sqneg s20, s12
+# CHECK-NEXT: 1 2 0.50 sqneg v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 sqneg v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqneg v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sqneg v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sqneg v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqneg v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sqneg v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 sqrdmulh h10, h11, h12
+# CHECK-NEXT: 1 3 0.50 sqrdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: 1 3 0.50 sqrdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: 1 3 0.50 sqrdmulh s20, s21, s2
+# CHECK-NEXT: 1 3 0.50 sqrdmulh v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sqrdmulh v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqrshl d31, d31, d31
+# CHECK-NEXT: 1 2 0.50 sqrshl h3, h4, h15
+# CHECK-NEXT: 1 2 0.50 sqrshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sqrshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sqrshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 sqrshrn b10, h13, #2
+# CHECK-NEXT: 1 3 0.50 sqrshrn h15, s10, #6
+# CHECK-NEXT: 1 3 0.50 sqrshrn s15, d12, #9
+# CHECK-NEXT: 1 2 0.50 sqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 sqrshrun b17, h10, #6
+# CHECK-NEXT: 1 3 0.50 sqrshrun h10, s13, #15
+# CHECK-NEXT: 1 3 0.50 sqrshrun s22, d16, #31
+# CHECK-NEXT: 1 2 0.50 sqrshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqrshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqshl b11, b19, #7
+# CHECK-NEXT: 1 2 0.50 sqshl d15, d16, #51
+# CHECK-NEXT: 1 2 0.50 sqshl d31, d31, d31
+# CHECK-NEXT: 1 2 0.50 sqshl h13, h18, #11
+# CHECK-NEXT: 1 2 0.50 sqshl h3, h4, h15
+# CHECK-NEXT: 1 2 0.50 sqshl s14, s17, #22
+# CHECK-NEXT: 1 2 0.50 sqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 sqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 sqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 sqshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu b15, b18, #6
+# CHECK-NEXT: 1 2 0.50 sqshlu d11, d13, #32
+# CHECK-NEXT: 1 2 0.50 sqshlu h19, h17, #6
+# CHECK-NEXT: 1 2 0.50 sqshlu s16, s14, #25
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 sqshlu v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 sqshrn b10, h15, #5
+# CHECK-NEXT: 1 3 0.50 sqshrn h17, s10, #4
+# CHECK-NEXT: 1 3 0.50 sqshrn s18, d10, #31
+# CHECK-NEXT: 2 6 1.00 sqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 sqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 2 6 1.00 sqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 sqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 sqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 sqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 sqshrun b15, h10, #7
+# CHECK-NEXT: 1 3 0.50 sqshrun h20, s14, #3
+# CHECK-NEXT: 1 3 0.50 sqshrun s10, d15, #15
+# CHECK-NEXT: 2 6 1.00 sqshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 sqshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: 2 6 1.00 sqshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 sqshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 2 6 1.00 sqshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 2 6 1.00 sqshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 sqsub s20, s10, s7
+# CHECK-NEXT: 1 2 0.50 sqsub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqsub v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 sqxtn b18, h18
+# CHECK-NEXT: 1 2 0.50 sqxtn h20, s17
+# CHECK-NEXT: 1 2 0.50 sqxtn s19, d14
+# CHECK-NEXT: 1 2 0.50 sqxtn v0.2s, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqxtn v0.4h, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqxtn v0.8b, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqxtun b19, h14
+# CHECK-NEXT: 1 2 0.50 sqxtun h21, s15
+# CHECK-NEXT: 1 2 0.50 sqxtun s20, d12
+# CHECK-NEXT: 1 2 0.50 sqxtun v0.2s, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqxtun v0.4h, v0.4s
+# CHECK-NEXT: 1 2 0.50 sqxtun v0.8b, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqxtun2 v0.16b, v0.8h
+# CHECK-NEXT: 1 2 0.50 sqxtun2 v0.4s, v0.2d
+# CHECK-NEXT: 1 2 0.50 sqxtun2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.50 srhadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 srhadd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 srhadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 sri d10, d12, #14
+# CHECK-NEXT: 1 3 0.50 sri v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 sri v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 srshl d16, d16, d16
+# CHECK-NEXT: 1 3 0.50 srshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 srshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 srshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 srshr d19, d18, #7
+# CHECK-NEXT: 1 3 0.50 srshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 srshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 srsra d15, d11, #19
+# CHECK-NEXT: 1 2 0.50 srsra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 srsra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 sshl d31, d31, d31
+# CHECK-NEXT: 1 2 0.50 sshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 sshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 sshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 sshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 sshll v0.2d, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 sshll2 v0.4s, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 sshr d15, d16, #12
+# CHECK-NEXT: 1 3 0.50 sshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 sshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 ssra d18, d12, #21
+# CHECK-NEXT: 1 2 0.50 ssra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 ssra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 ssubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 ssubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 ssubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 ssubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 ssubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 ssubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 ssubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.50 ssubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.50 ssubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.50 ssubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 ssubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 ssubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 2 2 1.00 * st1 { v0.16b }, [x0]
+# CHECK-NEXT: 6 4 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: 8 5 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: 4 3 2.00 * st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: 6 4 3.00 * st1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: 8 5 4.00 * st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: 2 2 1.00 * st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: 4 3 2.00 * st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: 3 4 1.00 * st1 { v0.d }[1], [x0]
+# CHECK-NEXT: 3 4 1.00 * st1 { v0.d }[1], [x0], #8
+# CHECK-NEXT: 6 5 2.00 * st2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: 6 6 2.00 * st2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: 6 5 2.00 * st2 { v0.s, v1.s }[3], [sp]
+# CHECK-NEXT: 6 5 2.00 * st2 { v0.s, v1.s }[3], [sp], #8
+# CHECK-NEXT: 9 6 3.00 * st3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: 9 6 3.00 * st3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: 9 6 3.00 * st3 { v0.h, v1.h, v2.h }[7], [x15]
+# CHECK-NEXT: 9 6 3.00 * st3 { v0.h, v1.h, v2.h }[7], [x15], #6
+# CHECK-NEXT: 14 9 4.00 * st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: 12 7 4.00 * st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: 12 7 4.00 * st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
+# CHECK-NEXT: 12 7 4.00 * st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
+# CHECK-NEXT: 1 2 0.50 sub d15, d5, d16
+# CHECK-NEXT: 1 2 0.50 sub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 suqadd b19, b14
+# CHECK-NEXT: 1 2 0.50 suqadd d18, d22
+# CHECK-NEXT: 1 2 0.50 suqadd h20, h15
+# CHECK-NEXT: 1 2 0.50 suqadd s21, s12
+# CHECK-NEXT: 1 2 0.50 suqadd v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 suqadd v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 suqadd v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 suqadd v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 suqadd v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 suqadd v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 suqadd v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 tbl v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: 2 4 1.00 tbl v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: 3 6 1.50 tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: 4 8 2.00 tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: 1 2 0.50 tbl v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: 2 4 1.00 tbl v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: 3 6 1.50 tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: 4 8 2.00 tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: 1 2 0.50 tbx v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: 2 4 1.00 tbx v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: 3 6 1.50 tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: 4 8 2.00 tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: 1 2 0.50 tbx v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: 2 4 1.00 tbx v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: 3 6 1.50 tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: 4 8 2.00 tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: 1 2 0.50 trn1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 trn1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 trn1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 trn1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 trn1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 trn1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 trn1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 trn2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 trn2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 trn2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 trn2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 trn2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 trn2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 trn2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uaba v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uadalp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.50 uadalp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 uadalp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.50 uadalp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.50 uadalp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 uadalp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 uaddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uaddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uaddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uaddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uaddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uaddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.1d, v0.2s
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.2s, v0.4h
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.4h, v0.8b
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 uaddlp v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 uaddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.50 uaddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.50 uaddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.50 uaddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 uaddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 uaddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 3 0.50 ucvtf d21, d14
+# CHECK-NEXT: 1 3 0.50 ucvtf d21, d14, #64
+# CHECK-NEXT: 1 3 0.50 ucvtf s22, s13
+# CHECK-NEXT: 1 3 0.50 ucvtf s22, s13, #32
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 ucvtf v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uhsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 umax v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 umax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 umax v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 umaxp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 umaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 umaxp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 umin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 umin v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 umin v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uminp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uminp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 umlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 umlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 umlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 umlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 umlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 umlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 umlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 umlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 umlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 umlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 umlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 umlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 umull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 umull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 umull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 umull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 umull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 umull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uqadd h0, h1, h5
+# CHECK-NEXT: 1 2 0.50 uqadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uqrshl b11, b20, b30
+# CHECK-NEXT: 1 2 0.50 uqrshl s23, s20, s16
+# CHECK-NEXT: 1 2 0.50 uqrshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uqrshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uqrshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uqrshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 uqrshrn b10, h12, #5
+# CHECK-NEXT: 1 3 0.50 uqrshrn h12, s10, #14
+# CHECK-NEXT: 1 3 0.50 uqrshrn s10, d10, #25
+# CHECK-NEXT: 1 2 0.50 uqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 uqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 uqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 uqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 uqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 uqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 uqshl b11, b20, b30
+# CHECK-NEXT: 1 2 0.50 uqshl b18, b15, #6
+# CHECK-NEXT: 1 2 0.50 uqshl d15, d12, #19
+# CHECK-NEXT: 1 2 0.50 uqshl h11, h18, #7
+# CHECK-NEXT: 1 2 0.50 uqshl s14, s19, #18
+# CHECK-NEXT: 1 2 0.50 uqshl s23, s20, s16
+# CHECK-NEXT: 1 2 0.50 uqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 uqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 uqshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 uqshrn b12, h10, #7
+# CHECK-NEXT: 1 3 0.50 uqshrn h10, s14, #5
+# CHECK-NEXT: 1 3 0.50 uqshrn s10, d12, #13
+# CHECK-NEXT: 1 2 0.50 uqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 uqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 uqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 uqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 uqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 uqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 uqsub d16, d16, d16
+# CHECK-NEXT: 1 2 0.50 uqsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 2 6 1.00 uqxtn b18, h18
+# CHECK-NEXT: 2 6 1.00 uqxtn h20, s17
+# CHECK-NEXT: 2 6 1.00 uqxtn s19, d14
+# CHECK-NEXT: 2 6 1.00 uqxtn v0.2s, v0.2d
+# CHECK-NEXT: 2 6 1.00 uqxtn v0.4h, v0.4s
+# CHECK-NEXT: 2 6 1.00 uqxtn v0.8b, v0.8h
+# CHECK-NEXT: 2 6 1.00 uqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: 2 6 1.00 uqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: 2 6 1.00 uqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.50 urecpe v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 urecpe v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 urhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 urhadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 urhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 urshl d8, d7, d4
+# CHECK-NEXT: 1 3 0.50 urshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 urshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 urshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 urshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 urshr d20, d23, #31
+# CHECK-NEXT: 1 3 0.50 urshr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 urshr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 ursqrte v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 ursqrte v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 ursra d18, d10, #13
+# CHECK-NEXT: 1 2 0.50 ursra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 ursra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 3 0.50 ushl d0, d0, d0
+# CHECK-NEXT: 1 2 0.50 ushl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 ushl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 ushl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 ushll v0.4s, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 ushll2 v0.8h, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 ushr d10, d17, #18
+# CHECK-NEXT: 1 3 0.50 ushr v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 3 0.50 ushr v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 usqadd b19, b14
+# CHECK-NEXT: 1 2 0.50 usqadd d18, d22
+# CHECK-NEXT: 1 2 0.50 usqadd h20, h15
+# CHECK-NEXT: 1 2 0.50 usqadd s21, s12
+# CHECK-NEXT: 1 2 0.50 usqadd v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 usqadd v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 usqadd v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 usqadd v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 usqadd v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 usqadd v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 usqadd v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 usra d20, d13, #61
+# CHECK-NEXT: 1 2 0.50 usra v0.16b, v0.16b, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.2d, v0.2d, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.2s, v0.2s, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.4h, v0.4h, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.4s, v0.4s, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.8b, v0.8b, #3
+# CHECK-NEXT: 1 2 0.50 usra v0.8h, v0.8h, #3
+# CHECK-NEXT: 1 2 0.50 usubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 usubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 usubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 usubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 usubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 usubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 usubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: 1 2 0.50 usubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: 1 2 0.50 usubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: 1 2 0.50 usubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: 1 2 0.50 usubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: 1 2 0.50 usubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uzp1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 uzp2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 xtn v0.2s, v0.2d
+# CHECK-NEXT: 1 2 0.50 xtn v0.4h, v0.4s
+# CHECK-NEXT: 1 2 0.50 xtn v0.8b, v0.8h
+# CHECK-NEXT: 1 2 0.50 xtn2 v0.16b, v0.8h
+# CHECK-NEXT: 1 2 0.50 xtn2 v0.4s, v0.2d
+# CHECK-NEXT: 1 2 0.50 xtn2 v0.8h, v0.4s
+# CHECK-NEXT: 1 2 0.50 zip1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 zip1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 zip1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 zip1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 zip1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 zip1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 zip1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 1 2 0.50 zip2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 1 2 0.50 zip2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 2 0.50 zip2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: 1 2 0.50 zip2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: 1 2 0.50 zip2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 1 2 0.50 zip2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 2 0.50 zip2 v0.8h, v0.8h, v0.8h
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - Ampere1BUnitA
+# CHECK-NEXT: [0.1] - Ampere1BUnitA
+# CHECK-NEXT: [1.0] - Ampere1BUnitB
+# CHECK-NEXT: [1.1] - Ampere1BUnitB
+# CHECK-NEXT: [2] - Ampere1BUnitBS
+# CHECK-NEXT: [3.0] - Ampere1BUnitL
+# CHECK-NEXT: [3.1] - Ampere1BUnitL
+# CHECK-NEXT: [4.0] - Ampere1BUnitS
+# CHECK-NEXT: [4.1] - Ampere1BUnitS
+# CHECK-NEXT: [5] - Ampere1BUnitX
+# CHECK-NEXT: [6] - Ampere1BUnitY
+# CHECK-NEXT: [7] - Ampere1BUnitZ
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7]
+# CHECK-NEXT: - - - - 11.00 51.00 51.00 29.00 29.00 604.50 584.50 58.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4.0] [4.1] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs d29, d24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - abs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - add d17, d31, d29
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - add v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - addhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - addp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - addp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - and v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - bic v0.4h, #15, lsl #8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - bic v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - bif v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - bit v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - bsl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cls v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - clz v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmeq d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmeq d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmeq v0.16b, v0.16b, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmeq v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmge d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmge d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmge v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmge v0.8b, v0.8b, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmgt d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmgt d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmgt v0.2s, v0.2s, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmhi d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmhi v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmhs d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmhs v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmle d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmle v0.2d, v0.2d, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmlt d20, d21, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmlt v0.8h, v0.8h, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmtst d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cmtst v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cnt v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - cnt v0.8b, v0.8b
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.16b, w28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.2d, x28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.2s, w28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.4h, w28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.4s, w28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.8b, w28
+# CHECK-NEXT: - - - - 1.00 - - - - - - - dup v0.8h, w28
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - eor v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ext v0.16b, v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ext v0.8b, v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabd d29, d24, d20
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabd s29, s24, s20
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fabs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facge d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facge s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facgt d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facgt s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - facgt v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - faddp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - faddp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq d20, d21, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq s10, s11, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq v0.2s, v0.2s, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmeq v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge d20, d21, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge s10, s11, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge v0.2d, v0.2d, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmge v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt d20, d21, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt d20, d21, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt s10, s11, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt s10, s11, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmgt v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmle d20, d21, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmle s10, s11, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmle v0.2d, v0.2d, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmlt d20, d21, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmlt s10, s11, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcmlt v0.4s, v0.4s, #0.0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtas v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtau v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtl v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtl v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtl2 v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtl2 v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms s22, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtms v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtmu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns s22, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtns v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtnu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps s22, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtps v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtpu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtxn s22, d13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtxn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtxn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs d21, d12, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs s21, s12, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu d21, d12, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu s12, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu s21, s12, #1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fcvtzu v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fdiv v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmax v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmin v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnm v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnm v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnm v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnmp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnmp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminnmp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmla d0, d1, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmla s0, s1, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmla v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmls d0, d4, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmls s3, s5, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmls v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov v0.2d, #-1.25000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov v0.2s, #13.00000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmov v0.4s, #1.00000000
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmul d0, d1, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmul s0, s1, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmul v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx d0, d4, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx d23, d11, d1
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx s20, s22, s15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx s3, s5, v0.s[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fmulx v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fneg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe d13, d13
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe s19, s14
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frecpe v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frecps v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frecps d22, d30, d21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frecps s21, s16, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frecpx d16, d19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frecpx s18, s10
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinta v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frinti v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintm v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintn v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintp v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintx v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frintz v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte d21, d12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte s22, s13
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - frsqrte v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frsqrts d8, d22, d18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frsqrts s21, s5, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - frsqrts v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 - - fsqrt v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - fsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ld1 { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - 1.50 1.50 - - - - - ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ld1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: - - - - - 1.50 1.50 - - - - - ld1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - ld1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - ld1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1 { v0.b }[9], [x0]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1 { v0.b }[9], [x0], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1r { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1r { v0.16b }, [x0], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1r { v0.8h }, [x15]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - 0.50 0.50 - ld1r { v0.8h }, [x15], #2
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.50 1.50 - ld2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2 { v0.h, v1.h }[7], [x15]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2 { v0.h, v1.h }[7], [x15], #4
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2r { v0.2d, v1.2d }, [x0]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2r { v0.2d, v1.2d }, [x0], #16
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2r { v0.4s, v1.4s }, [sp]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - 1.00 1.00 - ld2r { v0.4s, v1.4s }, [sp], #8
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3 { v0.s, v1.s, v2.s }[3], [sp]
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3 { v0.s, v1.s, v2.s }[3], [sp], x3
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3r { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3r { v0.8b, v1.8b, v2.8b }, [x0]
+# CHECK-NEXT: - - - - - 1.50 1.50 - - 1.50 1.50 - ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - - ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - 2.00 2.00 - ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mla v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mls v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov b0, v0.b[15]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov d6, v0.d[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov h2, v0.h[5]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov s17, v0.s[2]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v2.b[0], v0.b[0]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v2.h[1], v0.h[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v2.s[2], v0.s[2]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v2.d[1], v0.d[1]
+# CHECK-NEXT: - - - - 1.00 - - - - 0.50 0.50 - mov v0.b[0], w8
+# CHECK-NEXT: - - - - 1.00 - - - - 0.50 0.50 - mov v0.h[1], w8
+# CHECK-NEXT: - - - - 1.00 - - - - 0.50 0.50 - mov v0.s[2], w8
+# CHECK-NEXT: - - - - 1.00 - - - - 0.50 0.50 - mov v0.d[1], x8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi d15, #0xff00ff00ff00ff
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi v0.16b, #31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi v0.2d, #0xff0000ff0000ffff
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi v0.2s, #8, msl #8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi v0.4s, #255, lsl #24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - movi v0.8b, #255
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mvni v0.2s, #0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mvni v0.4s, #16, msl #16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg d29, d24
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - neg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mvn v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mvn v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - orn v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - mov v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - orr v0.8h, #31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - pmul v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - pmul v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - pmull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - pmull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - raddhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rbit v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rbit v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev16 v21.8b, v1.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev16 v30.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev32 v0.4h, v9.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev32 v21.8b, v1.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev32 v30.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev32 v4.8h, v7.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v0.16b, v31.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v1.8b, v9.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v13.4h, v21.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v2.8h, v4.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v4.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - rev64 v6.4s, v8.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - rsubhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saba v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sadalp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddlp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - saddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf d21, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf d21, d12, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf s22, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf s22, s13, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - scvtf v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shl d7, d10, #12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shl v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shl v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shl v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shl v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.2d, v0.2s, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.4s, v0.4h, #16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.8h, v0.8b, #8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.2d, v0.2s, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.4s, v0.4h, #16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll v0.8h, v0.8b, #8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.2d, v0.4s, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.4s, v0.8h, #16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shll2 v0.8h, v0.16b, #8
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - shrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shsub v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - shsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli d10, d14, #12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sli v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smax v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smax v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smax v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smaxp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smaxp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smaxp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smin v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smin v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smin v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sminp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sminp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sminp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - smull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs b19, b14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs d18, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs h21, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs s20, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqabs v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqadd b20, b11, b15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal d19, s24, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal d8, s9, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal s0, h0, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal s17, h27, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl d12, s23, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl d8, s9, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl s0, h0, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl s14, h12, h25
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh h10, h11, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh s20, s21, s2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmulh v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull d1, s1, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull d15, s22, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull s1, h1, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull s12, h22, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqdmull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg b19, b14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg d18, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg h21, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg s20, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqneg v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh h10, h11, h12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh h7, h15, v0.h[3]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh s15, s14, v0.s[1]
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh s20, s21, s2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrdmulh v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshl h3, h4, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn b10, h13, #2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn h15, s10, #6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn s15, d12, #9
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun b17, h10, #6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun h10, s13, #15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun s22, d16, #31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqrshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl b11, b19, #7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl d15, d16, #51
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl h13, h18, #11
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl h3, h4, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl s14, s17, #22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu b15, b18, #6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu d11, d13, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu h19, h17, #6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu s16, s14, #25
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshlu v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrn b10, h15, #5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrn h17, s10, #4
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrn s18, d10, #31
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrun b15, h10, #7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrun h20, s14, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqshrun s10, d15, #15
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - sqshrun2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqsub s20, s10, s7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqsub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqsub v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn b18, h18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn h20, s17
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn s19, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun b19, h14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun h21, s15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun s20, d12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sqxtun2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srhadd v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srhadd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srhadd v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri d10, d12, #14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sri v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshl d16, d16, d16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr d19, d18, #7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra d15, d11, #19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - srsra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshl d31, d31, d31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshl v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshl v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshl v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshll v0.2d, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshll2 v0.4s, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr d15, d16, #12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra d18, d12, #21
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ssubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 st1 { v0.16b }, [x0]
+# CHECK-NEXT: - - - - - - - 1.50 1.50 - - 3.00 st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
+# CHECK-NEXT: - - - - - - - 2.00 2.00 - - 4.00 st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 st1 { v0.4s, v1.4s }, [sp], #32
+# CHECK-NEXT: - - - - - - - 1.50 1.50 - - 3.00 st1 { v0.4s, v1.4s, v2.4s }, [sp]
+# CHECK-NEXT: - - - - - - - 2.00 2.00 - - 4.00 st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - 1.00 st1 { v0.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - 1.00 1.00 - - 2.00 st1 { v0.8h, v1.8h }, [x15]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.50 0.50 1.00 st1 { v0.d }[1], [x0]
+# CHECK-NEXT: - - - - - - - 0.50 0.50 0.50 0.50 1.00 st1 { v0.d }[1], [x0], #8
+# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 1.00 2.00 st2 { v0.16b, v1.16b }, [x0], x1
+# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 1.00 2.00 st2 { v0.8b, v1.8b }, [x0]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 1.00 2.00 st2 { v0.s, v1.s }[3], [sp]
+# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 1.00 2.00 st2 { v0.s, v1.s }[3], [sp], #8
+# CHECK-NEXT: - - - - - - - 1.50 1.50 1.50 1.50 3.00 st3 { v0.4h, v1.4h, v2.4h }, [x15]
+# CHECK-NEXT: - - - - - - - 1.50 1.50 1.50 1.50 3.00 st3 { v0.8h, v1.8h, v2.8h }, [x15], x2
+# CHECK-NEXT: - - - - - - - 1.50 1.50 1.50 1.50 3.00 st3 { v0.h, v1.h, v2.h }[7], [x15]
+# CHECK-NEXT: - - - - - - - 1.50 1.50 1.50 1.50 3.00 st3 { v0.h, v1.h, v2.h }[7], [x15], #6
+# CHECK-NEXT: - - - - - - - 2.00 2.00 3.00 3.00 4.00 st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 4.00 st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 4.00 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 4.00 st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sub d15, d5, d16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - sub v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd b19, b14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd d18, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd h20, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd s21, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - suqadd v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - tbl v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - tbl v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 - tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - tbl v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - tbl v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 - tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - tbx v0.16b, { v0.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - tbx v0.16b, { v0.16b, v1.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 - tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - tbx v0.8b, { v0.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - tbx v0.8b, { v0.16b, v1.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 1.50 1.50 - tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 2.00 2.00 - tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - trn2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaba v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabd v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uabdl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uadalp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.1d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.2s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.4h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddlp v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uaddw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf d21, d14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf d21, d14, #64
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf s22, s13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf s22, s13, #32
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ucvtf v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uhsub v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umax v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umax v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umax v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umaxp v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umaxp v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umaxp v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umin v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umin v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umin v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uminp v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uminp v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uminp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlal2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umlsl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - umull2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqadd h0, h1, h5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl b11, b20, b30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl s23, s20, s16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn b10, h12, #5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn h12, s10, #14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn s10, d10, #25
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqrshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl b11, b20, b30
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl b18, b15, #6
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl d15, d12, #19
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl h11, h18, #7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl s14, s19, #18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl s23, s20, s16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn b12, h10, #7
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn h10, s14, #5
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn s10, d12, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn v0.2s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn v0.4h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn v0.8b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn2 v0.16b, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn2 v0.4s, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqshrn2 v0.8h, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqsub d16, d16, d16
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uqsub v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn b18, h18
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn h20, s17
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn s19, d14
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 1.00 1.00 - uqxtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urecpe v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urecpe v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urhadd v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urhadd v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urhadd v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshl d8, d7, d4
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshl v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr d20, d23, #31
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - urshr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursqrte v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursqrte v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra d18, d10, #13
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ursra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushl d0, d0, d0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushl v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushl v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushl v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushll v0.4s, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushll2 v0.8h, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr d10, d17, #18
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - ushr v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd b19, b14
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd d18, d22
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd h20, h15
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd s21, s12
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usqadd v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra d20, d13, #61
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.16b, v0.16b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.2d, v0.2d, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.2s, v0.2s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.4h, v0.4h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.4s, v0.4s, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.8b, v0.8b, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usra v0.8h, v0.8h, #3
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl v0.2d, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl v0.4s, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl v0.8h, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl2 v0.2d, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl2 v0.4s, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubl2 v0.8h, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw v0.2d, v0.2d, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw v0.4s, v0.4s, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw v0.8h, v0.8h, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw2 v0.2d, v0.2d, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw2 v0.4s, v0.4s, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - usubw2 v0.8h, v0.8h, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - uzp2 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn v0.2s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn v0.4h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn v0.8b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn2 v0.16b, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn2 v0.4s, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - xtn2 v0.8h, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip1 v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.2s, v0.2s, v0.2s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.4h, v0.4h, v0.4h
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - zip2 v0.8h, v0.8h, v0.8h
diff --git a/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s
new file mode 100644
index 00000000000000..27e0279a701013
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -march=aarch64 -mcpu=ampere1b -resource-pressure=false < %s | FileCheck %s
+
+ add w0, w1, w2, lsl #0
+ sub x3, x4, x5, lsl #1
+ adds x6, x7, x8, lsr #2
+ subs x9, x10, x11, asr #3
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 156
+# CHECK-NEXT: Total uOps: 600
+
+# CHECK: Dispatch Width: 12
+# CHECK-NEXT: uOps Per Cycle: 3.85
+# CHECK-NEXT: IPC: 2.56
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 add w0, w1, w2
+# CHECK-NEXT: 1 1 0.25 sub x3, x4, x5, lsl #1
+# CHECK-NEXT: 2 2 0.50 adds x6, x7, x8, lsr #2
+# CHECK-NEXT: 2 2 0.50 subs x9, x10, x11, asr #3
>From 6d94a9811d0cec3b4de718adfd72e20619644fea Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: Wed, 14 Feb 2024 16:54:08 -0800
Subject: [PATCH 4/4] [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1
(#81744)
One of the whitespace fixes didn't get added to the commit introducing
the Ampere1B model.
Clean it up.
(cherry picked from commit 3369e341288b3d9bb59827f9a2911ebf3d36408d)
---
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 7e041dbd2abaea..613db353cb0aaa 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -29,7 +29,7 @@ def NeoverseV1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
[HasMTE, HasCPA,
- HasCSSC]);
+ HasCSSC]);
}
//===----------------------------------------------------------------------===//
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