[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

[Dhruv Chawla via llvm-branch-commits]

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@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
                  {s16, v8s16},
                  {s32, v2s32},
                  {s32, v4s32}})
+      .moreElementsIf(
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dc03-work wrote:

As I noted in my commit message, unfortunately that causes regressions for odd-sized `i8` vectors: https://gist.github.com/dc03-work/3d749a7be0dc893d86d2df0fbc31709a (except for the very last case... for some reason). I was noticing another test failure when I enabled it for even-sized vectors, however that seems to have gone away now.

https://github.com/llvm/llvm-project/pull/81831