[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

Dhruv Chawla via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Feb 14 23:37:29 PST 2024

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https://github.com/dc03-work created https://github.com/llvm/llvm-project/pull/81831

i8 vectors do not have their sizes changed as I noticed regressions in some
tests when that was done.

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