[llvm-branch-commits] [llvm] [SelectionDAG] Legalize <1 x T> vector types for atomic load (PR #120385)

[via llvm-branch-commits]

jofrn wrote:

> * New IR allowed in the verifier. It will not yet compile, but bitcode/textual IR creation/reading/writing works.
> * AtomicExpandPass handles vector types correctly. Now the IR-level transform works; backend target lowering still broken.
> * Generic SelectionDAG legalization support added. (prerequisite work for next PRs)
> * X86 backend support. Now, `store atomic <N x T>` and `load atomic <N x T>` should correctly compile on x86/x86_64 platforms (for all N and T), when using SelectionDAG.
> * GlobalISel
> * Other targets
> * Now, the new operations are fully functional.

This all makes sense. Thanks. The next split to be will be to address AtomicExpandPass, as I see this as causing trouble for atomics. Generic SelectionDAG is addressed in any PR with prefix `[SelectionDAG]` in the title. X86 backend is only to add the promotion at the moment. GlobalISel is not yet addressed nor are other targets.

https://github.com/llvm/llvm-project/pull/120385