[llvm-branch-commits] [llvm] release/19.x: [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246) (PR #120296)

[via llvm-branch-commits]

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/120296

Backport e8ce6c4

Requested by: @topperc

>From 032b352c2ba61eab447d08fd7cd86fbaee36be10 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <phvankempen at googlemail.com>
Date: Tue, 17 Dec 2024 21:20:17 +0100
Subject: [PATCH] [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)

This typo in
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701
caused a compiler crash in 'RISC-V Assembly Printer' because
CV_SH_ri_inc was selected, leading to `getImmOpValue` being called for a
register operand.

This bug did not affect the Assembler output and therefore does not
trigger any existing unit tests, but is visible by examining the final
MIR function.

(cherry picked from commit e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3)
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 3bd6da28682863..99485981701479 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -694,7 +694,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStriPat<post_store, CV_SW_ri_inc>;
 
   def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
-  def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+  def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
   def : CVStrriPat<post_store, CV_SW_rr_inc>;
 
   def : CVStrrPat<truncstorei8, CV_SB_rr>;