[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

[Matt Arsenault via llvm-branch-commits]

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@@ -123,6 +123,7 @@ namespace {
     const TargetRegisterInfo *TRI = nullptr;
     const MachineFrameInfo *MFI = nullptr;
     MachineRegisterInfo *MRI = nullptr;
+    RegisterClassInfo RegClassInfo;
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arsenm wrote:

Relatedly, we also do not serialize the set of reserved registers in MIR 

https://github.com/llvm/llvm-project/pull/119194