[llvm-branch-commits] [llvm] Spiller: Detach legacy pass and supply analyses instead (PR #119181)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Dec 9 00:38:29 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
Author: Akshat Oke (optimisan)
<details>
<summary>Changes</summary>
Makes Inline Spiller amenable for the new PM.
---
Full diff: https://github.com/llvm/llvm-project/pull/119181.diff
5 Files Affected:
- (modified) llvm/include/llvm/CodeGen/Spiller.h (+14-2)
- (modified) llvm/lib/CodeGen/InlineSpiller.cpp (+14-22)
- (modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+11-5)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+3-1)
- (modified) llvm/lib/CodeGen/RegAllocPBQP.cpp (+4-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/Spiller.h b/llvm/include/llvm/CodeGen/Spiller.h
index 51ad36bc6b1f8b..3132cefeb6c68a 100644
--- a/llvm/include/llvm/CodeGen/Spiller.h
+++ b/llvm/include/llvm/CodeGen/Spiller.h
@@ -19,6 +19,10 @@ class MachineFunction;
class MachineFunctionPass;
class VirtRegMap;
class VirtRegAuxInfo;
+class LiveIntervals;
+class LiveStacks;
+class MachineDominatorTree;
+class MachineBlockFrequencyInfo;
/// Spiller interface.
///
@@ -41,12 +45,20 @@ class Spiller {
virtual ArrayRef<Register> getReplacedRegs() = 0;
virtual void postOptimization() {}
+
+ struct RequiredAnalyses {
+ LiveIntervals &LIS;
+ LiveStacks &LSS;
+ MachineDominatorTree &MDT;
+ const MachineBlockFrequencyInfo &MBFI;
+ };
};
/// Create and return a spiller that will insert spill code directly instead
/// of deferring though VirtRegMap.
-Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF,
- VirtRegMap &VRM, VirtRegAuxInfo &VRAI);
+Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI);
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 64f290f5930a1b..b9768d5c63a5d1 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -75,7 +75,6 @@ RestrictStatepointRemat("restrict-statepoint-remat",
cl::desc("Restrict remat for statepoint operands"));
namespace {
-
class HoistSpillHelper : private LiveRangeEdit::Delegate {
MachineFunction &MF;
LiveIntervals &LIS;
@@ -128,15 +127,11 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
public:
- HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
- VirtRegMap &vrm)
- : MF(mf), LIS(pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
- LSS(pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()),
- MDT(pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
+ HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
+ MachineFunction &mf, VirtRegMap &vrm)
+ : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
- TRI(*mf.getSubtarget().getRegisterInfo()),
- MBFI(
- pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()),
+ TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
IPA(LIS, mf.getNumBlockIDs()) {}
void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
@@ -190,16 +185,12 @@ class InlineSpiller : public Spiller {
~InlineSpiller() override = default;
public:
- InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM,
- VirtRegAuxInfo &VRAI)
- : MF(MF), LIS(Pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
- LSS(Pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()),
- MDT(Pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
+ InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
+ VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
+ : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
- TRI(*MF.getSubtarget().getRegisterInfo()),
- MBFI(
- Pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()),
- HSpiller(Pass, MF, VRM), VRAI(VRAI) {}
+ TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
+ HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
void spill(LiveRangeEdit &) override;
ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; }
@@ -237,10 +228,11 @@ Spiller::~Spiller() = default;
void Spiller::anchor() {}
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
- MachineFunction &MF, VirtRegMap &VRM,
- VirtRegAuxInfo &VRAI) {
- return new InlineSpiller(Pass, MF, VRM, VRAI);
+Spiller *
+llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
+ MachineFunction &MF, VirtRegMap &VRM,
+ VirtRegAuxInfo &VRAI) {
+ return new InlineSpiller(Analyses, MF, VRM, VRAI);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index c05aa1e40e4779..f3f34f890be11e 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
+#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
@@ -187,6 +188,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<ProfileSummaryInfoWrapperPass>();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequiredID(MachineDominatorsID);
AU.addPreservedID(MachineDominatorsID);
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -310,16 +312,20 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
<< "********** Function: " << mf.getName() << '\n');
MF = &mf;
+ auto &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+ auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+
RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
- VirtRegAuxInfo VRAI(
- *MF, *LIS, *VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
- getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(),
- &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
+ VirtRegAuxInfo VRAI(*MF, *LIS, *VRM,
+ getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI,
+ &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
VRAI.calculateSpillWeightsAndHints();
- SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, VRAI));
+ SpillerInstance.reset(
+ createInlineSpiller({*LIS, LiveStks, MDT, MBFI}, *MF, *VRM, VRAI));
allocatePhysRegs();
postOptimization();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index d3a7f4cb6f1206..033f048ca7499b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2733,6 +2733,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+ auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
initializeCSRCost();
@@ -2755,7 +2756,8 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
*this);
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
- SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, *VRAI));
+ SpillerInstance.reset(
+ createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
VRAI->calculateSpillWeightsAndHints();
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 696c312e4ba00a..e230a1be95c9fa 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -794,6 +794,9 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
MachineBlockFrequencyInfo &MBFI =
getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+ auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
PBQPVirtRegAuxInfo VRAI(
@@ -807,7 +810,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
VirtRegAuxInfo DefaultVRAI(
MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);
std::unique_ptr<Spiller> VRegSpiller(
- createInlineSpiller(*this, MF, VRM, DefaultVRAI));
+ createInlineSpiller({LIS, LiveStks, MDT, MBFI}, MF, VRM, DefaultVRAI));
MF.getRegInfo().freezeReservedRegs();
``````````
</details>
https://github.com/llvm/llvm-project/pull/119181
More information about the llvm-branch-commits
mailing list