[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port MachineCSE pass to new pass manager. (PR #106605)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Aug 29 11:30:22 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-nvptx
@llvm/pr-subscribers-backend-amdgpu
Author: Christudasan Devadasan (cdevadas)
<details>
<summary>Changes</summary>
---
Patch is 33.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/106605.diff
21 Files Affected:
- (added) llvm/include/llvm/CodeGen/MachineCSE.h (+29)
- (modified) llvm/include/llvm/CodeGen/Passes.h (+1-1)
- (modified) llvm/include/llvm/InitializePasses.h (+1-1)
- (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+1)
- (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+1-1)
- (modified) llvm/lib/CodeGen/CodeGen.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MachineCSE.cpp (+161-122)
- (modified) llvm/lib/CodeGen/TargetPassConfig.cpp (+3-3)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/sve-pfalse-machine-cse.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir (+5-3)
- (modified) llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir (+1)
- (modified) llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir (+1)
- (modified) llvm/test/CodeGen/Thumb/machine-cse-physreg.mir (+1)
- (modified) llvm/test/CodeGen/X86/cse-two-preds.mir (+1)
- (modified) llvm/test/DebugInfo/MIR/X86/machine-cse.mir (+1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineCSE.h b/llvm/include/llvm/CodeGen/MachineCSE.h
new file mode 100644
index 00000000000000..7440068e3e6f46
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineCSE.h
@@ -0,0 +1,29 @@
+//===- llvm/CodeGen/MachineCSE.h -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINECSE_H
+#define LLVM_CODEGEN_MACHINECSE_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class MachineCSEPass : public PassInfoMixin<MachineCSEPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINECSE_H
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index dbdd110b0600e5..ddb2012cd2bffc 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -330,7 +330,7 @@ namespace llvm {
extern char &GCMachineCodeAnalysisID;
/// MachineCSE - This pass performs global CSE on machine instructions.
- extern char &MachineCSEID;
+ extern char &MachineCSELegacyID;
/// MIRCanonicalizer - This pass canonicalizes MIR by renaming vregs
/// according to the semantics of the instruction as well as hoists
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 47a1ca15fc0d1f..6605c6fde92510 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -188,7 +188,7 @@ void initializeMachineBlockPlacementPass(PassRegistry &);
void initializeMachineBlockPlacementStatsPass(PassRegistry &);
void initializeMachineBranchProbabilityInfoWrapperPassPass(PassRegistry &);
void initializeMachineCFGPrinterPass(PassRegistry &);
-void initializeMachineCSEPass(PassRegistry &);
+void initializeMachineCSELegacyPass(PassRegistry &);
void initializeMachineCombinerPass(PassRegistry &);
void initializeMachineCopyPropagationPass(PassRegistry &);
void initializeMachineCycleInfoPrinterPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index eb15beb835b535..6c34747b9da406 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -42,6 +42,7 @@
#include "llvm/CodeGen/LocalStackSlotAllocation.h"
#include "llvm/CodeGen/LowerEmuTLS.h"
#include "llvm/CodeGen/MIRPrinter.h"
+#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index b710b1c46f643f..cb781532e266e6 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -131,6 +131,7 @@ MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
#endif
MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass())
MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
+MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
@@ -219,7 +220,6 @@ DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass)
DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass)
-DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 177702054a0e31..16b8d456748fac 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -75,7 +75,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachineBlockPlacementPass(Registry);
initializeMachineBlockPlacementStatsPass(Registry);
initializeMachineCFGPrinterPass(Registry);
- initializeMachineCSEPass(Registry);
+ initializeMachineCSELegacyPass(Registry);
initializeMachineCombinerPass(Registry);
initializeMachineCopyPropagationPass(Registry);
initializeMachineCycleInfoPrinterPassPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 2ac1fae9ea48c1..2ab95fb4d9641a 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -12,6 +12,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/ScopedHashTable.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -25,6 +26,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
@@ -69,110 +71,110 @@ static cl::opt<bool> AggressiveMachineCSE(
namespace {
- class MachineCSE : public MachineFunctionPass {
- const TargetInstrInfo *TII = nullptr;
- const TargetRegisterInfo *TRI = nullptr;
- MachineDominatorTree *DT = nullptr;
- MachineRegisterInfo *MRI = nullptr;
- MachineBlockFrequencyInfo *MBFI = nullptr;
-
- public:
- static char ID; // Pass identification
-
- MachineCSE() : MachineFunctionPass(ID) {
- initializeMachineCSEPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- AU.addPreservedID(MachineLoopInfoID);
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addPreserved<MachineDominatorTreeWrapperPass>();
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
- }
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties()
- .set(MachineFunctionProperties::Property::IsSSA);
- }
+class MachineCSEImpl {
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineDominatorTree *DT = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+
+public:
+ MachineCSEImpl(MachineDominatorTree *DT, MachineBlockFrequencyInfo *MBFI)
+ : DT(DT), MBFI(MBFI) {}
+ bool run(MachineFunction &MF);
+
+private:
+ using AllocatorTy =
+ RecyclingAllocator<BumpPtrAllocator,
+ ScopedHashTableVal<MachineInstr *, unsigned>>;
+ using ScopedHTType =
+ ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
+ AllocatorTy>;
+ using ScopeType = ScopedHTType::ScopeTy;
+ using PhysDefVector = SmallVector<std::pair<unsigned, unsigned>, 2>;
+
+ unsigned LookAheadLimit = 0;
+ DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
+ DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait>
+ PREMap;
+ ScopedHTType VNT;
+ SmallVector<MachineInstr *, 64> Exps;
+ unsigned CurrVN = 0;
+
+ bool PerformTrivialCopyPropagation(MachineInstr *MI, MachineBasicBlock *MBB);
+ bool isPhysDefTriviallyDead(MCRegister Reg,
+ MachineBasicBlock::const_iterator I,
+ MachineBasicBlock::const_iterator E) const;
+ bool hasLivePhysRegDefUses(const MachineInstr *MI,
+ const MachineBasicBlock *MBB,
+ SmallSet<MCRegister, 8> &PhysRefs,
+ PhysDefVector &PhysDefs, bool &PhysUseDef) const;
+ bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
+ SmallSet<MCRegister, 8> &PhysRefs,
+ PhysDefVector &PhysDefs, bool &NonLocal) const;
+ bool isCSECandidate(MachineInstr *MI);
+ bool isProfitableToCSE(Register CSReg, Register Reg, MachineBasicBlock *CSBB,
+ MachineInstr *MI);
+ void EnterScope(MachineBasicBlock *MBB);
+ void ExitScope(MachineBasicBlock *MBB);
+ bool ProcessBlockCSE(MachineBasicBlock *MBB);
+ void ExitScopeIfDone(MachineDomTreeNode *Node,
+ DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren);
+ bool PerformCSE(MachineDomTreeNode *Node);
+
+ bool isPRECandidate(MachineInstr *MI, SmallSet<MCRegister, 8> &PhysRefs);
+ bool ProcessBlockPRE(MachineDominatorTree *MDT, MachineBasicBlock *MBB);
+ bool PerformSimplePRE(MachineDominatorTree *DT);
+ /// Heuristics to see if it's profitable to move common computations of MBB
+ /// and MBB1 to CandidateBB.
+ bool isProfitableToHoistInto(MachineBasicBlock *CandidateBB,
+ MachineBasicBlock *MBB, MachineBasicBlock *MBB1);
+ void releaseMemory();
+};
+
+class MachineCSELegacy : public MachineFunctionPass {
+public:
+ static char ID; // Pass identification
+
+ MachineCSELegacy() : MachineFunctionPass(ID) {
+ initializeMachineCSELegacyPass(*PassRegistry::getPassRegistry());
+ }
- void releaseMemory() override {
- ScopeMap.clear();
- PREMap.clear();
- Exps.clear();
- }
+ bool runOnMachineFunction(MachineFunction &MF) override;
- private:
- using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
- ScopedHashTableVal<MachineInstr *, unsigned>>;
- using ScopedHTType =
- ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
- AllocatorTy>;
- using ScopeType = ScopedHTType::ScopeTy;
- using PhysDefVector = SmallVector<std::pair<unsigned, unsigned>, 2>;
-
- unsigned LookAheadLimit = 0;
- DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
- DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait>
- PREMap;
- ScopedHTType VNT;
- SmallVector<MachineInstr *, 64> Exps;
- unsigned CurrVN = 0;
-
- bool PerformTrivialCopyPropagation(MachineInstr *MI,
- MachineBasicBlock *MBB);
- bool isPhysDefTriviallyDead(MCRegister Reg,
- MachineBasicBlock::const_iterator I,
- MachineBasicBlock::const_iterator E) const;
- bool hasLivePhysRegDefUses(const MachineInstr *MI,
- const MachineBasicBlock *MBB,
- SmallSet<MCRegister, 8> &PhysRefs,
- PhysDefVector &PhysDefs, bool &PhysUseDef) const;
- bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
- SmallSet<MCRegister, 8> &PhysRefs,
- PhysDefVector &PhysDefs, bool &NonLocal) const;
- bool isCSECandidate(MachineInstr *MI);
- bool isProfitableToCSE(Register CSReg, Register Reg,
- MachineBasicBlock *CSBB, MachineInstr *MI);
- void EnterScope(MachineBasicBlock *MBB);
- void ExitScope(MachineBasicBlock *MBB);
- bool ProcessBlockCSE(MachineBasicBlock *MBB);
- void ExitScopeIfDone(MachineDomTreeNode *Node,
- DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
- bool PerformCSE(MachineDomTreeNode *Node);
-
- bool isPRECandidate(MachineInstr *MI, SmallSet<MCRegister, 8> &PhysRefs);
- bool ProcessBlockPRE(MachineDominatorTree *MDT, MachineBasicBlock *MBB);
- bool PerformSimplePRE(MachineDominatorTree *DT);
- /// Heuristics to see if it's profitable to move common computations of MBB
- /// and MBB1 to CandidateBB.
- bool isProfitableToHoistInto(MachineBasicBlock *CandidateBB,
- MachineBasicBlock *MBB,
- MachineBasicBlock *MBB1);
- };
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
+ }
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
} // end anonymous namespace
-char MachineCSE::ID = 0;
+char MachineCSELegacy::ID = 0;
-char &llvm::MachineCSEID = MachineCSE::ID;
+char &llvm::MachineCSELegacyID = MachineCSELegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineCSE, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineCSELegacy, DEBUG_TYPE,
"Machine Common Subexpression Elimination", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineCSELegacy, DEBUG_TYPE,
"Machine Common Subexpression Elimination", false, false)
/// The source register of a COPY machine instruction can be propagated to all
/// its users, and this propagation could increase the probability of finding
/// common subexpressions. If the COPY has only one user, the COPY itself can
/// be removed.
-bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
- MachineBasicBlock *MBB) {
+bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI,
+ MachineBasicBlock *MBB) {
bool Changed = false;
for (MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
@@ -225,7 +227,7 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
return Changed;
}
-bool MachineCSE::isPhysDefTriviallyDead(
+bool MachineCSEImpl::isPhysDefTriviallyDead(
MCRegister Reg, MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator E) const {
unsigned LookAheadLeft = LookAheadLimit;
@@ -282,11 +284,11 @@ static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
/// physical registers (except for dead defs of physical registers). It also
/// returns the physical register def by reference if it's the only one and the
/// instruction does not uses a physical register.
-bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
- const MachineBasicBlock *MBB,
- SmallSet<MCRegister, 8> &PhysRefs,
- PhysDefVector &PhysDefs,
- bool &PhysUseDef) const {
+bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
+ const MachineBasicBlock *MBB,
+ SmallSet<MCRegister, 8> &PhysRefs,
+ PhysDefVector &PhysDefs,
+ bool &PhysUseDef) const {
// First, add all uses to PhysRefs.
for (const MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
@@ -333,10 +335,10 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
return !PhysRefs.empty();
}
-bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
- SmallSet<MCRegister, 8> &PhysRefs,
- PhysDefVector &PhysDefs,
- bool &NonLocal) const {
+bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
+ SmallSet<MCRegister, 8> &PhysRefs,
+ PhysDefVector &PhysDefs,
+ bool &NonLocal) const {
// For now conservatively returns false if the common subexpression is
// not in the same basic block as the given instruction. The only exception
// is if the common subexpression is in the sole predecessor block.
@@ -400,7 +402,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
return false;
}
-bool MachineCSE::isCSECandidate(MachineInstr *MI) {
+bool MachineCSEImpl::isCSECandidate(MachineInstr *MI) {
if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
MI->isInlineAsm() || MI->isDebugInstr() || MI->isJumpTableDebugInfo() ||
MI->isFakeUse())
@@ -437,8 +439,9 @@ bool MachineCSE::isCSECandidate(MachineInstr *MI) {
/// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
/// common expression that defines Reg. CSBB is basic block where CSReg is
/// defined.
-bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg,
- MachineBasicBlock *CSBB, MachineInstr *MI) {
+bool MachineCSEImpl::isProfitableToCSE(Register CSReg, Register Reg,
+ MachineBasicBlock *CSBB,
+ MachineInstr *MI) {
if (AggressiveMachineCSE)
return true;
@@ -513,13 +516,13 @@ bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg,
return !HasPHI;
}
-void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
+void MachineCSEImpl::EnterScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
ScopeType *Scope = new ScopeType(VNT);
ScopeMap[MBB] = Scope;
}
-void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
+void MachineCSEImpl::ExitScope(MachineBasicBlock *MBB) {
LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
assert(SI != ScopeMap.end());
@@ -527,7 +530,7 @@ void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
ScopeMap.erase(SI);
}
-bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
+bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
bool Changed = false;
SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
@@ -748,9 +751,9 @@ bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
/// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
/// dominator tree node if its a leaf or all of its children are done. Walk
/// up the dominator tree to destroy ancestors which are now done.
-void
-MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
- DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
+void MachineCSEImpl::ExitScopeIfDone(
+ MachineDomTreeNode *Node,
+ DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren) {
if (OpenChildren[Node])
return;
@@ -767,7 +770,7 @@ MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
}
}
-bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
+bool MachineCSEImpl::PerformCSE(MachineDomTreeNode *Node) {
SmallVector<MachineDomTreeNode*, 32> Scopes;
SmallVector<MachineDomTreeNode*, 8> WorkList;
DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
@@ -799,8 +802,8 @@ bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
// We use stronger checks for PRE candidate rather than for CSE ones to embrace
// checks inside ProcessBlockCSE(), not only inside isCSECandidate(). This helps
// to exclude instrs created by PRE that won't be CSEed later.
-bool MachineCSE::isPRECandidate(MachineInstr *MI,
- SmallSet<MCRegister, 8> &PhysRefs) {
+bool MachineCSEImpl::isPRECandidate(MachineInstr *MI,
+ SmallSet<MCRegister, 8...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/106605
More information about the llvm-branch-commits
mailing list