[llvm-branch-commits] [llvm] [AMDGPU] GFX12 VMEM instructions can write VGPR results out of order (PR #105549)

[Jay Foad via llvm-branch-commits]

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@@ -1778,11 +1778,12 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
           if (IsVGPR) {
             // RAW always needs an s_waitcnt. WAW needs an s_waitcnt unless the
             // previous write and this write are the same type of VMEM
-            // instruction, in which case they're guaranteed to write their
-            // results in order anyway.
+            // instruction, in which case they are (in some architectures)
+            // guaranteed to write their results in order anyway.
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jayfoad wrote:

No this is nothing to do with storing data to memory. We are only talking about loads (or atomic with results) and the order in which they write the loaded data into the result VGPR.

https://github.com/llvm/llvm-project/pull/105549