[llvm-branch-commits] [llvm] [AMDGPU] GFX12 VMEM instructions can write VGPR results out of order (PR #105549)

[Juan Manuel Martinez Caamaño via llvm-branch-commits]

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@@ -1778,11 +1778,12 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
           if (IsVGPR) {
             // RAW always needs an s_waitcnt. WAW needs an s_waitcnt unless the
             // previous write and this write are the same type of VMEM
-            // instruction, in which case they're guaranteed to write their
-            // results in order anyway.
+            // instruction, in which case they are (in some architectures)
+            // guaranteed to write their results in order anyway.
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jmmartinez wrote:

Hi, the change looks good to me, but I have a question:

That means that 2 vector writes of the same type on unrelated memory addresses may introduce a wait, even if they do not alias ? Since we're not considering aliasing information here. 

The same happens for RAW consecutive write/load pairs of instructions. Right ?

https://github.com/llvm/llvm-project/pull/105549