[llvm-branch-commits] [llvm] release/19.x: [AArch64] Don't replace dst of SWP instructions with (X|W)ZR (#102139) (PR #102316)

[Luke Geeson via llvm-branch-commits]

lukeg101 wrote:

Prevents a concurrency-related compiler bug (a reordering bug introduced by LLVM) that arises when optimisations rewrite the destination register of SWP instructions to be the zero register when compiling an atomic exchange operation. For more information on this bug and how it was found, please see: https://lukegeeson.com/publications/2024-03-05-CGO/



https://github.com/llvm/llvm-project/pull/102316