[llvm-branch-commits] [clang] [llvm] [AArch64] Fix a bug where user could not disable certain architecture features (PR #104752)
Tomas Matheson via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 19 05:55:35 PDT 2024
https://github.com/tmatheson-arm updated https://github.com/llvm/llvm-project/pull/104752
>From b523150d05242d9e00dc2dcf1694a1cf7dde088f Mon Sep 17 00:00:00 2001
From: Tomas Matheson <Tomas.Matheson at arm.com>
Date: Sat, 17 Aug 2024 13:36:40 +0100
Subject: [PATCH 1/3] [AArch64] Add a check for invalid default features
(#104435)
This adds a check that all ExtensionWithMArch which are marked as
implied features for an architecture are also present in the list of
default features. It doesn't make sense to have something mandatory but
not on by default.
There were a number of existing cases that violated this rule, and some
changes to which features are mandatory (indicated by the Implies
field).
This resulted in a bug where if a feature was marked as `Implies` but
was not added to `DefaultExt`, then for `-march=base_arch+nofeat` the
Driver would consider `feat` to have never been added and therefore
would do nothing to disable it (no `-target-feature -feat` would be
added, but the backend would enable the feature by default because of
`Implies`). See
clang/test/Driver/aarch64-negative-modifiers-for-default-features.c.
Note that the processor definitions do not respect the architecture
DefaultExts. These apply only when specifying `-march=<some architecture
version>`. So when a feature is moved from `Implies` to `DefaultExts` on
the Architecture definition, the feature needs to be added to all
processor definitions (that are based on that architecture) in order to
preserve the existing behaviour. I have checked the TRMs for many cases
(see specific commit messages) but in other cases I have just kept the
current behaviour and not tried to fix it.
---
clang/test/CodeGen/aarch64-targetattr.c | 12 +--
...-negative-modifiers-for-default-features.c | 12 +++
clang/test/Driver/arm-sb.c | 2 +-
.../aarch64-apple-a12.c | 1 -
.../aarch64-apple-a13.c | 1 -
.../aarch64-apple-a14.c | 1 -
.../aarch64-apple-a15.c | 1 -
.../aarch64-apple-a16.c | 1 -
.../aarch64-apple-a17.c | 1 -
.../aarch64-apple-m4.c | 2 -
.../aarch64-cortex-r82.c | 1 -
.../aarch64-cortex-r82ae.c | 1 -
llvm/lib/Target/AArch64/AArch64Features.td | 19 ++--
llvm/lib/Target/AArch64/AArch64Processors.td | 46 +++++++--
llvm/test/MC/AArch64/arm64-system-encoding.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs-error.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-ssbs.s | 2 +-
.../MC/Disassembler/AArch64/armv8.5a-ssbs.txt | 2 +-
.../AArch64/basic-a64-instructions.txt | 2 +-
.../TargetParser/TargetParserTest.cpp | 97 +++++++++++--------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 32 +++++-
21 files changed, 156 insertions(+), 84 deletions(-)
create mode 100644 clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 4f891f938b6186..d6227be2ebef83 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -195,19 +195,19 @@ void minusarch() {}
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
-// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
+// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
+// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
-// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
//.
diff --git a/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c b/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
new file mode 100644
index 00000000000000..03dd8af7588cae
--- /dev/null
+++ b/clang/test/Driver/aarch64-negative-modifiers-for-default-features.c
@@ -0,0 +1,12 @@
+// Test that default features (e.g. flagm/sb/ssbs for 8.5) can be disabled via -march.
+
+// RUN: %clang --target=aarch64 -march=armv8.5-a+noflagm+nosb+nossbs -c %s -### 2>&1 | FileCheck %s
+// CHECK: "-triple" "aarch64"
+// CHECK-SAME: "-target-feature" "+v8.5a"
+// CHECK-SAME: "-target-feature" "-flagm"
+// CHECK-SAME: "-target-feature" "-sb"
+// CHECK-SAME: "-target-feature" "-ssbs"
+
+// CHECK-NOT: "-target-feature" "+flagm"
+// CHECK-NOT: "-target-feature" "+sb"
+// CHECK-NOT: "-target-feature" "+ssbs"
diff --git a/clang/test/Driver/arm-sb.c b/clang/test/Driver/arm-sb.c
index f2704f33c27111..9c0f381171cb6d 100644
--- a/clang/test/Driver/arm-sb.c
+++ b/clang/test/Driver/arm-sb.c
@@ -11,6 +11,6 @@
// RUN: %clang -### -target arm-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT
// RUN: %clang -### -target aarch64-none-elf %s 2>&1 | FileCheck %s --check-prefix=ABSENT
-// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=ABSENT
+// RUN: %clang -### -target aarch64-none-elf -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=NOSB
// ABSENT-NOT: "-target-feature" "+sb"
// ABSENT-NOT: "-target-feature" "-sb"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
index 27f066a3107086..fcc8b674df33f4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
@@ -6,7 +6,6 @@
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
index 197b2102599510..dae95b1297e145 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
@@ -7,7 +7,6 @@
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
index f1731ef034a0c1..8ddcddede4110d 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
@@ -7,7 +7,6 @@
// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
index 267287eaf7b6e9..302661a80db30b 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
@@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
index de382a3497b81b..a3f5150f87c287 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
@@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
index 641aa3f82387b7..dec90ffddb6ee8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
@@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
index 5096bc6940520f..0a815174033dc8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
@@ -10,7 +10,6 @@
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
@@ -51,7 +50,6 @@
// CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions
// CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
-// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
index 2b85201c2c6fe6..9875c6922d379a 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82.c
@@ -5,7 +5,6 @@
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
index 417687b4af287d..2db44d7827aadb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-r82ae.c
@@ -5,7 +5,6 @@
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
-// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 69af6f7efa7837..a4f8f8c2d9629f 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -787,27 +787,26 @@ def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a",
[HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP],
!listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>;
def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a",
- [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX,
- FeatureComplxNum],
+ [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureComplxNum],
!listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS,
- FeaturePAuth, FeatureRCPC])>;
+ FeaturePAuth, FeatureRCPC, FeatureCCIDX])>;
def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a",
[HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM,
FeatureRCPC_IMMO, FeatureLSE2],
- !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>;
+ !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureFlagM])>;
def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
+ FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureBranchTargetId],
- !listconcat(HasV8_4aOps.DefaultExts, [])>;
+ !listconcat(HasV8_4aOps.DefaultExts, [FeaturePredRes, FeatureSSBS, FeatureBranchTargetId, FeatureSB])>;
def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
- !listconcat(HasV8_6aOps.DefaultExts, [])>;
+ !listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>;
def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
[HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
!listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
@@ -825,7 +824,7 @@ def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
!listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>;
def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",
[HasV8_7aOps, HasV9_1aOps],
- !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC])>;
+ !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>;
def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
[HasV8_8aOps, HasV9_2aOps],
!listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
@@ -842,7 +841,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
//v8.2
FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
//v8.3
- FeatureCCIDX, FeaturePAuth, FeatureRCPC,
+ FeaturePAuth, FeatureRCPC,
//v8.4
FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2,
FeatureRCPC_IMMO,
@@ -853,7 +852,7 @@ def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
// For v8-R, we do not enable crypto and align with GCC that enables a more
// minimal set of optional architecture extensions.
!listconcat(
- !listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]),
+ !listremove(HasV8_5aOps.DefaultExts, [FeatureBranchTargetId, FeaturePredRes]),
[FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB]
)>;
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 71384a23c49afc..cd6e7051b8bdf1 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -688,6 +688,7 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
+ FeatureCCIDX,
FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2,
FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8,FeatureFullFP16, FeatureJS, FeatureLSE,
@@ -695,6 +696,7 @@ def ProcessorFeatures {
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
+ FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS,
@@ -703,6 +705,7 @@ def ProcessorFeatures {
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
+ FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS,
@@ -734,12 +737,14 @@ def ProcessorFeatures {
FeaturePerfMon, FeatureRCPC, FeatureSPE,
FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
+ FeatureCCIDX, FeatureSSBS,
FeatureETE, FeatureMTE, FeatureFP16FML,
FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8,
FeaturePAuth, FeatureFlagM, FeatureSB, FeatureSVE, FeatureSVE2,
FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE,
+ FeatureCCIDX,
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8, FeatureSPE,
@@ -749,6 +754,7 @@ def ProcessorFeatures {
FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ FeatureCCIDX,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
@@ -757,6 +763,7 @@ def ProcessorFeatures {
FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS,
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ FeatureCCIDX,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
@@ -765,6 +772,7 @@ def ProcessorFeatures {
FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS,
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
@@ -800,6 +808,7 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
+ FeatureCCIDX,
FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureFlagM,
FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16,
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
@@ -808,6 +817,7 @@ def ProcessorFeatures {
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
FeatureFP16FML,
+ FeatureCCIDX,
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS,
FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS,
FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureDotProd];
@@ -815,11 +825,13 @@ def ProcessorFeatures {
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
FeatureFP16FML, FeatureSPE_EEF,
+ FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS, FeatureLSE,
FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureBF16];
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
@@ -863,23 +875,26 @@ def ProcessorFeatures {
list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
- FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
- FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
- FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleM4 = [HasV9_2aOps, FeatureSHA2, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
@@ -909,6 +924,7 @@ def ProcessorFeatures {
FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
FeatureSVE2BitPerm, FeatureTRBE,
FeaturePerfMon,
+ FeatureCCIDX,
FeatureDotProd, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureSVE,
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeatureNEON, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
@@ -916,6 +932,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureMTE, FeaturePerfMon,
FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
FeatureSVE2BitPerm,
+ FeatureCCIDX,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum,
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
@@ -926,6 +943,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSSBS, FeatureSVE,
+ FeatureCCIDX,
FeatureSHA3, FeatureSM4, FeatureDotProd, FeatureComplxNum,
FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM];
@@ -934,6 +952,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSSBS, FeatureSVE,
+ FeatureCCIDX,
FeatureSHA3, FeatureSM4, FeatureDotProd, FeatureComplxNum,
FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM];
@@ -941,12 +960,14 @@ def ProcessorFeatures {
FeaturePerfMon, FeatureETE, FeatureMatMulInt8,
FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML,
FeatureMTE, FeatureRandGen,
+ FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd,
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
+ FeatureCCIDX,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
@@ -957,12 +978,14 @@ def ProcessorFeatures {
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
+ FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS,
FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureRME];
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeatureSPE, FeaturePerfMon, FeatureCRC,
+ FeatureCCIDX,
FeatureLSE, FeatureRDM, FeatureRAS, FeatureRCPC];
list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
@@ -971,6 +994,7 @@ def ProcessorFeatures {
FeatureRDM];
list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureSHA2, FeatureAES,
FeatureFPARMv8, FeatureNEON, FeatureLSE,
+ FeatureCCIDX,
FeaturePAuth, FeaturePerfMon, FeatureComplxNum,
FeatureJS, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -983,6 +1007,7 @@ def ProcessorFeatures {
FeatureSHA2, FeatureSHA3, FeatureAES,
FeatureFullFP16, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS,
+ FeatureCCIDX,
FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureMTE, FeatureSSBS, FeatureRandGen,
@@ -991,6 +1016,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureBF16, FeatureComplxNum,
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
+ FeatureCCIDX,
FeatureRDM];
list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
FeatureMTE, FeatureSSBS, FeatureRandGen,
@@ -999,6 +1025,7 @@ def ProcessorFeatures {
FeatureWFxT, FeatureFullFP16, FeatureBF16, FeatureComplxNum,
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
+ FeatureCCIDX,
FeatureRDM];
list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
@@ -1007,6 +1034,7 @@ def ProcessorFeatures {
FeatureSHA3, FeatureAES,
FeatureSPE, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
+ FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
// ETE and TRBE are future architecture extensions. We temporarily enable them
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index 313ec911774603..c58a8f0cb841cb 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -1,5 +1,5 @@
; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
-; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+v8.3a -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83
+; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+ccidx -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
foo:
diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s b/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s
index a7c9f4c4fbb5c3..cd5ab43046c798 100644
--- a/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s
+++ b/llvm/test/MC/AArch64/armv8.5a-ssbs-error.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
msr SSBS, #16
diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs.s b/llvm/test/MC/AArch64/armv8.5a-ssbs.s
index ec6670f8ecc34c..2a8b7b000646ad 100644
--- a/llvm/test/MC/AArch64/armv8.5a-ssbs.s
+++ b/llvm/test/MC/AArch64/armv8.5a-ssbs.s
@@ -1,5 +1,5 @@
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65 < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65ae < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76 < %s | FileCheck %s
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
index 7698751c88076b..84d4fa6accccf4 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
@@ -1,5 +1,5 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mcpu=cortex-a76ae -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8r -disassemble < %s | FileCheck %s --check-prefix=NOSPECID
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index c76bb0b9020967..f46301e8c1c15b 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -2,7 +2,7 @@
# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
# RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82
-# RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
+# RUN: llvm-mc -triple=arm64 -mattr=+ccidx -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
#------------------------------------------------------------------------------
# Add/sub (immediate)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 9d08dd83684c90..e3ec0c31e99000 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1141,7 +1141,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_FP16, AArch64::AEK_FP16FML,
AArch64::AEK_SB, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE, AArch64::AEK_AM}),
+ AArch64::AEK_ETE, AArch64::AEK_AM,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a520", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1156,7 +1157,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PERFMON, AArch64::AEK_AM,
- AArch64::AEK_ETE}),
+ AArch64::AEK_ETE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a520ae", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1171,7 +1172,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PERFMON, AArch64::AEK_AM,
- AArch64::AEK_ETE}),
+ AArch64::AEK_ETE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a57", "armv8-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_FP,
@@ -1256,7 +1257,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM, AArch64::AEK_PAUTH,
AArch64::AEK_FLAGM, AArch64::AEK_SB, AArch64::AEK_I8MM,
AArch64::AEK_BF16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PERFMON, AArch64::AEK_ETE}),
+ AArch64::AEK_PERFMON, AArch64::AEK_ETE, AArch64::AEK_CCIDX,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams("cortex-a715", "armv9-a",
{AArch64::AEK_CRC, AArch64::AEK_FP,
AArch64::AEK_BF16, AArch64::AEK_SIMD,
@@ -1271,7 +1273,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_FP16FML, AArch64::AEK_FP16,
AArch64::AEK_FLAGM, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE, AArch64::AEK_TRBE}),
+ AArch64::AEK_ETE, AArch64::AEK_TRBE,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a720", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1287,7 +1290,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
- AArch64::AEK_TRBE}),
+ AArch64::AEK_TRBE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a720ae", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1303,7 +1306,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
- AArch64::AEK_TRBE}),
+ AArch64::AEK_TRBE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-a725", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1318,7 +1321,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_ETE,
- AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE}),
+ AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"neoverse-v1", "armv8.4-a",
{AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS,
@@ -1329,7 +1333,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16,
AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("neoverse-v2", "armv9-a",
{AArch64::AEK_RAS, AArch64::AEK_SVE,
AArch64::AEK_SSBS, AArch64::AEK_RCPC,
@@ -1343,7 +1348,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SVE2BITPERM, AArch64::AEK_RAND,
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE}),
+ AArch64::AEK_ETE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("neoverse-v3", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1361,7 +1366,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
- AArch64::AEK_RME}),
+ AArch64::AEK_RME, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("neoverse-v3ae", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1379,7 +1384,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
- AArch64::AEK_RME}),
+ AArch64::AEK_RME, AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"cortex-r82", "armv8-r",
{AArch64::AEK_CRC, AArch64::AEK_RDM, AArch64::AEK_SSBS,
@@ -1427,7 +1432,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_FP16FML, AArch64::AEK_FLAGM,
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PERFMON, AArch64::AEK_AM,
- AArch64::AEK_ETE}),
+ AArch64::AEK_ETE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-x3", "armv9-a",
{AArch64::AEK_CRC, AArch64::AEK_FP,
AArch64::AEK_BF16, AArch64::AEK_SIMD,
@@ -1442,7 +1447,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PREDRES, AArch64::AEK_FLAGM,
AArch64::AEK_SSBS, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE, AArch64::AEK_TRBE}),
+ AArch64::AEK_ETE, AArch64::AEK_TRBE,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-x4", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1458,7 +1464,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
- AArch64::AEK_TRBE}),
+ AArch64::AEK_TRBE, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cortex-x925", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1473,7 +1479,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_ETE,
- AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE}),
+ AArch64::AEK_SPE_EEF, AArch64::AEK_TRBE,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("cyclone", "armv8-a",
{AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_FP, AArch64::AEK_SIMD,
@@ -1591,7 +1598,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-m2", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1600,7 +1608,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-a16", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1609,7 +1618,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX, AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-m3", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1618,7 +1628,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX, AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-a17", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1627,7 +1638,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX, AArch64::AEK_SSBS}),
AArch64CPUTestParams("apple-m4", "armv9.2-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_SHA3,
@@ -1692,7 +1704,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_I8MM, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PAUTH,
AArch64::AEK_FP16FML, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE, AArch64::AEK_TRBE}),
+ AArch64::AEK_ETE, AArch64::AEK_TRBE,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("neoverse-n3", "armv9.2-a",
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
AArch64::AEK_SVE, AArch64::AEK_SVE2,
@@ -1708,7 +1721,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_FP16FML, AArch64::AEK_PROFILE,
AArch64::AEK_JSCVT, AArch64::AEK_PERFMON,
- AArch64::AEK_ETE, AArch64::AEK_SPE_EEF}),
+ AArch64::AEK_ETE, AArch64::AEK_SPE_EEF,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"ampere1", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
@@ -1717,17 +1731,18 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2,
AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS,
AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"ampere1a", "armv8.6-a",
- {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
- AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE,
- AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD,
- AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
- AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
- AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
- AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
+ AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE,
+ AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD,
+ AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
+ AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
+ AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
+ AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"ampere1b", "armv8.7-a",
{AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
@@ -1738,7 +1753,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH, AArch64::AEK_CSSC, AArch64::AEK_PERFMON,
- AArch64::AEK_WFXT}),
+ AArch64::AEK_WFXT, AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"neoverse-512tvb", "armv8.4-a",
{AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS,
@@ -1749,7 +1764,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16,
AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_CCDP,
+ AArch64::AEK_CCIDX}),
AArch64CPUTestParams("thunderx2t99", "armv8.1-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_LSE,
@@ -1762,7 +1778,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_SIMD, AArch64::AEK_RAS,
AArch64::AEK_RCPC, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_PAUTH,
- AArch64::AEK_PERFMON}),
+ AArch64::AEK_PERFMON, AArch64::AEK_CCIDX}),
AArch64CPUTestParams("thunderx", "armv8-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_SIMD,
@@ -1805,7 +1821,7 @@ INSTANTIATE_TEST_SUITE_P(
{AArch64::AEK_AES, AArch64::AEK_FP, AArch64::AEK_SIMD,
AArch64::AEK_PERFMON, AArch64::AEK_SHA2, AArch64::AEK_PROFILE,
AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM,
- AArch64::AEK_RAS, AArch64::AEK_RCPC}),
+ AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_CCIDX}),
AArch64CPUTestParams(
"oryon-1", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_PAUTH,
@@ -1814,7 +1830,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_SM4,
AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2,
AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_RAND,
- AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})),
+ AArch64::AEK_PROFILE, AArch64::AEK_PERFMON, AArch64::AEK_CCIDX,
+ AArch64::AEK_SSBS})),
AArch64CPUTestParams::PrintToStringParamName);
@@ -2248,9 +2265,9 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
}
TEST(TargetParserTest, AArch64PrintSupportedExtensions) {
- std::string expected =
- "All available -march extensions for AArch64\n\n"
- " Name Architecture Feature(s) Description\n";
+ std::string expected = "All available -march extensions for AArch64\n\n"
+ " Name Architecture Feature(s) "
+ " Description\n";
outs().flush();
testing::internal::CaptureStdout();
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index a4b25025b3c618..71ca331461c00c 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -19,10 +19,38 @@
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <cstdint>
+#include <set>
#include <string>
using namespace llvm;
+/// Collect the full set of implied features for a SubtargetFeature.
+static void CollectImpliedFeatures(std::set<Record *> &SeenFeats, Record *Rec) {
+ assert(Rec->isSubClassOf("SubtargetFeature") &&
+ "Rec is not a SubtargetFeature");
+
+ SeenFeats.insert(Rec);
+ for (Record *Implied : Rec->getValueAsListOfDefs("Implies"))
+ CollectImpliedFeatures(SeenFeats, Implied);
+}
+
+static void CheckFeatureTree(Record *Root) {
+ std::set<Record *> SeenFeats;
+ CollectImpliedFeatures(SeenFeats, Root);
+
+ // Check that each of the mandatory (implied) features which is an
+ // ExtensionWithMArch is also enabled by default.
+ auto DefaultExtsVec = Root->getValueAsListOfDefs("DefaultExts");
+ std::set<Record *> DefaultExts{DefaultExtsVec.begin(), DefaultExtsVec.end()};
+ for (auto *Feat : SeenFeats) {
+ if (Feat->isSubClassOf("ExtensionWithMArch") && !DefaultExts.count(Feat))
+ PrintFatalError(Root->getLoc(),
+ "ExtensionWithMArch " + Feat->getName() +
+ " is implied (mandatory) as a SubtargetFeature, but "
+ "is not present in DefaultExts");
+ }
+}
+
static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
@@ -283,9 +311,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- // The apple-latest alias is backend only, do not expose it to -mcpu.
- if (Name == "apple-latest")
- continue;
+ CheckFeatureTree(Arch);
OS << " {\n"
<< " \"" << Name << "\",\n"
>From 4ecdbfcf22bfde0682fc61bac65c26f15865c35c Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 19 Aug 2024 12:32:31 +0100
Subject: [PATCH 2/3] Remove FPAC from Apple A15/A16/A17
This was added by 265fbfa063d0b31b57e7945f5be061b2a4f5baff
which is not on 19.x, it might depend on other patches that have been
added to main so removing.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index cd6e7051b8bdf1..6df87fc6a815f7 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -876,7 +876,7 @@ def ProcessorFeatures {
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureComplxNum, FeatureCRC, FeatureJS,
- FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureLSE, FeaturePAuth,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -884,7 +884,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
FeatureComplxNum, FeatureCRC, FeatureJS,
- FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureLSE, FeaturePAuth,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -892,7 +892,7 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
FeatureComplxNum, FeatureCRC, FeatureJS,
- FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureLSE, FeaturePAuth,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
list<SubtargetFeature> AppleM4 = [HasV9_2aOps, FeatureSHA2, FeatureFPARMv8,
>From 0bcbfb63c749dc76e9d21a6aab7142fd2ec8a428 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 19 Aug 2024 13:55:16 +0100
Subject: [PATCH 3/3] fix TargetParserTests for FPAC
---
.../TargetParser/TargetParserTest.cpp | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index e3ec0c31e99000..dcbbc68332c799 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1598,8 +1598,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
- AArch64::AEK_SSBS}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-m2", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1608,8 +1607,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
- AArch64::AEK_SSBS}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-a16", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1618,8 +1616,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
- AArch64::AEK_HCX, AArch64::AEK_SSBS}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-m3", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1628,8 +1626,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
- AArch64::AEK_HCX, AArch64::AEK_SSBS}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams(
"apple-a17", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1638,8 +1636,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
- AArch64::AEK_HCX, AArch64::AEK_SSBS}),
+ AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX,
+ AArch64::AEK_SSBS}),
AArch64CPUTestParams("apple-m4", "armv9.2-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_SHA3,
More information about the llvm-branch-commits
mailing list