[llvm-branch-commits] [llvm] release/19.x: [Mips] Fix fast isel for i16 bswap. (#103398) (PR #104745)
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Mon Aug 19 01:16:44 PDT 2024
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/104745
Backport ebe7265b142f370f0a563fece5db22f57383ba2d
Requested by: @nikic
>From 9263d00e6bcbd1408b4c8c5b98b61332460911b5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 16 Aug 2024 14:54:51 -0700
Subject: [PATCH] [Mips] Fix fast isel for i16 bswap. (#103398)
We need to mask the SRL result to 8 bits before ORing in the SLL. This
is needed in case bits 23:16 of the input aren't zero. They will have
been shifted into bits 15:8.
We don't need to AND the result with 0xffff. It's ok if the upper 16
bits of the register are garbage.
Fixes #103035.
(cherry picked from commit ebe7265b142f370f0a563fece5db22f57383ba2d)
---
llvm/lib/Target/Mips/MipsFastISel.cpp | 4 ++--
llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index bd8ef43da625c3..64a0e9321598ff 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1608,8 +1608,8 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
}
emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
- emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
- emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
+ emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF);
+ emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
updateValueMap(II, DestReg);
return true;
}
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll
index bd762a0e1d741f..ce664c78e86c2a 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll
@@ -21,8 +21,8 @@ define void @b16() {
; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8
; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8
- ; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]]
- ; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535
+ ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP2]], 255
+ ; 32R1: or $[[RESULT:[0-9]+]], $[[TMP1]], $[[TMP3]]
; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]]
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