[llvm-branch-commits] [llvm] AMDGPU/NewPM: Port SILowerI1Copies to new pass manager (PR #102663)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 9 12:11:24 PDT 2024
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/102663
None
>From b6224ab90e73e07da50c612a7dc93da719208dbd Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 9 Aug 2024 22:54:33 +0400
Subject: [PATCH] AMDGPU/NewPM: Port SILowerI1Copies to new pass manager
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 14 +-
.../AMDGPU/AMDGPUCodeGenPassBuilder.cpp | 2 +
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 1 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +-
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 144 ++++++++++--------
.../CodeGen/AMDGPU/si-lower-i1-copies.mir | 1 +
6 files changed, 100 insertions(+), 66 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 99b04d6e4cfc3f..17a130e82ae8fb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -10,6 +10,7 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
@@ -36,7 +37,7 @@ FunctionPass *createGCNDPPCombinePass();
FunctionPass *createSIAnnotateControlFlowLegacyPass();
FunctionPass *createSIFoldOperandsPass();
FunctionPass *createSIPeepholeSDWAPass();
-FunctionPass *createSILowerI1CopiesPass();
+FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
FunctionPass *createSIShrinkInstructionsPass();
FunctionPass *createSILoadStoreOptimizerPass();
@@ -82,6 +83,13 @@ struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
};
+class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
+public:
+ SILowerI1CopiesPass() = default;
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
@@ -174,8 +182,8 @@ extern char &SIFixVGPRCopiesID;
void initializeSILowerWWMCopiesPass(PassRegistry &);
extern char &SILowerWWMCopiesID;
-void initializeSILowerI1CopiesPass(PassRegistry &);
-extern char &SILowerI1CopiesID;
+void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
+extern char &SILowerI1CopiesLegacyID;
void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
extern char &AMDGPUGlobalISelDivergenceLoweringID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
index cc4285f130fc82..50491247f0eddb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUCodeGenPassBuilder.h"
+#include "AMDGPU.h"
#include "AMDGPUISelDAGToDAG.h"
#include "AMDGPUTargetMachine.h"
#include "SIFixSGPRCopies.h"
@@ -40,5 +41,6 @@ void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
addPass(AMDGPUISelDAGToDAGPass(TM));
addPass(SIFixSGPRCopiesPass());
+ addPass(SILowerI1CopiesPass());
return Error::success();
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index cbb19c003a264a..af68eea665571f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -79,4 +79,5 @@ FUNCTION_PASS_WITH_PARAMS(
#endif
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
+MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 3cc0d314a7c5d8..ad816ec29b02dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -400,7 +400,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeGlobalISel(*PR);
initializeAMDGPUDAGToDAGISelLegacyPass(*PR);
initializeGCNDPPCombinePass(*PR);
- initializeSILowerI1CopiesPass(*PR);
+ initializeSILowerI1CopiesLegacyPass(*PR);
initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR);
initializeSILowerWWMCopiesPass(*PR);
initializeAMDGPUMarkLastScratchLoadPass(*PR);
@@ -1269,7 +1269,7 @@ bool GCNPassConfig::addILPOpts() {
bool GCNPassConfig::addInstSelector() {
AMDGPUPassConfig::addInstSelector();
addPass(&SIFixSGPRCopiesLegacyID);
- addPass(createSILowerI1CopiesPass());
+ addPass(createSILowerI1CopiesLegacyPass());
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index a9ee74dec1203f..7d49358d44025f 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -37,26 +37,6 @@ insertUndefLaneMask(MachineBasicBlock *MBB, MachineRegisterInfo *MRI,
namespace {
-class SILowerI1Copies : public MachineFunctionPass {
-public:
- static char ID;
-
- SILowerI1Copies() : MachineFunctionPass(ID) {
- initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- StringRef getPassName() const override { return "SI Lower i1 Copies"; }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<MachinePostDominatorTreeWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-};
-
class Vreg1LoweringHelper : public PhiLoweringHelper {
public:
Vreg1LoweringHelper(MachineFunction *MF, MachineDominatorTree *DT,
@@ -397,21 +377,6 @@ class LoopFinder {
} // End anonymous namespace.
-INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false,
- false)
-INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
-INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false,
- false)
-
-char SILowerI1Copies::ID = 0;
-
-char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
-
-FunctionPass *llvm::createSILowerI1CopiesPass() {
- return new SILowerI1Copies();
-}
-
Register
llvm::createLaneMaskReg(MachineRegisterInfo *MRI,
MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs) {
@@ -430,32 +395,6 @@ insertUndefLaneMask(MachineBasicBlock *MBB, MachineRegisterInfo *MRI,
return UndefReg;
}
-/// Lower all instructions that def or use vreg_1 registers.
-///
-/// In a first pass, we lower COPYs from vreg_1 to vector registers, as can
-/// occur around inline assembly. We do this first, before vreg_1 registers
-/// are changed to scalar mask registers.
-///
-/// Then we lower all defs of vreg_1 registers. Phi nodes are lowered before
-/// all others, because phi lowering looks through copies and can therefore
-/// often make copy lowering unnecessary.
-bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) {
- // Only need to run this in SelectionDAG path.
- if (TheMF.getProperties().hasProperty(
- MachineFunctionProperties::Property::Selected))
- return false;
-
- Vreg1LoweringHelper Helper(
- &TheMF, &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(),
- &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree());
-
- bool Changed = false;
- Changed |= Helper.lowerCopiesFromI1();
- Changed |= Helper.lowerPhis();
- Changed |= Helper.lowerCopiesToI1();
- return Helper.cleanConstrainRegs(Changed);
-}
-
#ifndef NDEBUG
static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
const MachineRegisterInfo &MRI,
@@ -915,3 +854,86 @@ void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,
}
void Vreg1LoweringHelper::constrainAsLaneMask(Incoming &In) {}
+
+/// Lower all instructions that def or use vreg_1 registers.
+///
+/// In a first pass, we lower COPYs from vreg_1 to vector registers, as can
+/// occur around inline assembly. We do this first, before vreg_1 registers
+/// are changed to scalar mask registers.
+///
+/// Then we lower all defs of vreg_1 registers. Phi nodes are lowered before
+/// all others, because phi lowering looks through copies and can therefore
+/// often make copy lowering unnecessary.
+static bool runFixI1Copies(MachineFunction &MF, MachineDominatorTree &MDT,
+ MachinePostDominatorTree &MPDT) {
+ // Only need to run this in SelectionDAG path.
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::Selected))
+ return false;
+
+ Vreg1LoweringHelper Helper(&MF, &MDT, &MPDT);
+ bool Changed = false;
+ Changed |= Helper.lowerCopiesFromI1();
+ Changed |= Helper.lowerPhis();
+ Changed |= Helper.lowerCopiesToI1();
+ return Helper.cleanConstrainRegs(Changed);
+}
+
+PreservedAnalyses
+SILowerI1CopiesPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ MachinePostDominatorTree &MPDT =
+ MFAM.getResult<MachinePostDominatorTreeAnalysis>(MF);
+ bool Changed = runFixI1Copies(MF, MDT, MPDT);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ // TODO: Probably preserves most.
+ PreservedAnalyses PA;
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+class SILowerI1CopiesLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ SILowerI1CopiesLegacy() : MachineFunctionPass(ID) {
+ initializeSILowerI1CopiesLegacyPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ StringRef getPassName() const override { return "SI Lower i1 Copies"; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<MachinePostDominatorTreeWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
+bool SILowerI1CopiesLegacy::runOnMachineFunction(MachineFunction &MF) {
+ MachineDominatorTree &MDT =
+ getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ MachinePostDominatorTree &MPDT =
+ getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
+ return runFixI1Copies(MF, MDT, MPDT);
+}
+
+INITIALIZE_PASS_BEGIN(SILowerI1CopiesLegacy, DEBUG_TYPE, "SI Lower i1 Copies",
+ false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
+INITIALIZE_PASS_END(SILowerI1CopiesLegacy, DEBUG_TYPE, "SI Lower i1 Copies",
+ false, false)
+
+char SILowerI1CopiesLegacy::ID = 0;
+
+char &llvm::SILowerI1CopiesLegacyID = SILowerI1CopiesLegacy::ID;
+
+FunctionPass *llvm::createSILowerI1CopiesLegacyPass() {
+ return new SILowerI1CopiesLegacy();
+}
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
index 9312322c04afe0..502116b121d949 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -passes=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s
# GCN-LABEL: name: lcssa_phi
---
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