[llvm-branch-commits] [mlir] 183f509 - use cached TM

[Mehdi Amini via llvm-branch-commits]

Author: Mehdi Amini
Date: 2023-11-03T13:26:56-07:00
New Revision: 183f5094ff7da09beed46f760a857af449a24245

URL: https://github.com/llvm/llvm-project/commit/183f5094ff7da09beed46f760a857af449a24245
DIFF: https://github.com/llvm/llvm-project/commit/183f5094ff7da09beed46f760a857af449a24245.diff

LOG: use cached TM

Created using spr 1.3.4

Added: 
    

Modified: 
    mlir/lib/Target/LLVM/ModuleToObject.cpp

Removed: 
    


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diff  --git a/mlir/lib/Target/LLVM/ModuleToObject.cpp b/mlir/lib/Target/LLVM/ModuleToObject.cpp
index 6af3d49ab23bf74..d94c10de8d7c424 100644
--- a/mlir/lib/Target/LLVM/ModuleToObject.cpp
+++ b/mlir/lib/Target/LLVM/ModuleToObject.cpp
@@ -45,8 +45,10 @@ Operation &ModuleToObject::getOperation() { return module; }
 
 std::optional<llvm::TargetMachine *>
 ModuleToObject::getOrCreateTargetMachine() {
-  std::string error;
+  if (targetMachine)
+    return targetMachine.get();
   // Load the target.
+  std::string error;
   const llvm::Target *target =
       llvm::TargetRegistry::lookupTarget(triple, error);
   if (!target) {