[llvm-branch-commits] [llvm] 8c6c56d - [X86] Don't crash on instruction prefetch intrinsics without PREFETCHI support.

[Tom Stellard via llvm-branch-commits]

Author: Craig Topper
Date: 2023-05-30T13:11:06-07:00
New Revision: 8c6c56dca37b6f4f50a7b1b0bc3e528e912aedc9

URL: https://github.com/llvm/llvm-project/commit/8c6c56dca37b6f4f50a7b1b0bc3e528e912aedc9
DIFF: https://github.com/llvm/llvm-project/commit/8c6c56dca37b6f4f50a7b1b0bc3e528e912aedc9.diff

LOG: [X86] Don't crash on instruction prefetch intrinsics without PREFETCHI support.

Instead of failing to select during isel, drop the intrinsic in
lowering.

Fixes PR62839.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D151050

(cherry picked from commit 022aefa59c28323d961603abaa34caaffe273ee4)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/prefetchi.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cf17c51b04fcc..7e3dae727c0fe 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -499,7 +499,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   }
 
   if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow())
-    setOperationAction(ISD::PREFETCH      , MVT::Other, Legal);
+    setOperationAction(ISD::PREFETCH      , MVT::Other, Custom);
 
   setOperationAction(ISD::ATOMIC_FENCE  , MVT::Other, Custom);
 
@@ -33093,6 +33093,18 @@ static SDValue LowerCVTPS2PH(SDValue Op, SelectionDAG &DAG) {
   return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
 }
 
+static SDValue LowerPREFETCH(SDValue Op, const X86Subtarget &Subtarget,
+                             SelectionDAG &DAG) {
+  unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+
+  // We don't support non-data prefetch without PREFETCHI.
+  // Just preserve the chain.
+  if (!IsData && !Subtarget.hasPREFETCHI())
+    return Op.getOperand(0);
+
+  return Op;
+}
+
 static StringRef getInstrStrFromOpNo(const SmallVectorImpl<StringRef> &AsmStrs,
                                      unsigned OpNo) {
   const APInt Operand(32, OpNo);
@@ -33294,6 +33306,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::GC_TRANSITION_END:  return LowerGC_TRANSITION(Op, DAG);
   case ISD::ADDRSPACECAST:      return LowerADDRSPACECAST(Op, DAG);
   case X86ISD::CVTPS2PH:        return LowerCVTPS2PH(Op, DAG);
+  case ISD::PREFETCH:           return LowerPREFETCH(Op, Subtarget, DAG);
   }
 }
 

diff  --git a/llvm/test/CodeGen/X86/prefetchi.ll b/llvm/test/CodeGen/X86/prefetchi.ll
index 8f97e077e535b..442819ea20d04 100644
--- a/llvm/test/CodeGen/X86/prefetchi.ll
+++ b/llvm/test/CodeGen/X86/prefetchi.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchi | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=NOPREFETCHI
 
 define dso_local void @t(ptr %ptr) nounwind  {
 ; CHECK-LABEL: t:
@@ -9,6 +10,10 @@ define dso_local void @t(ptr %ptr) nounwind  {
 ; CHECK-NEXT:    prefetchit1 t(%rip)
 ; CHECK-NEXT:    prefetchit0 ext(%rip)
 ; CHECK-NEXT:    retq
+;
+; NOPREFETCHI-LABEL: t:
+; NOPREFETCHI:       # %bb.0: # %entry
+; NOPREFETCHI-NEXT:    retq
 entry:
   tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 2, i32 0)
   tail call void @llvm.prefetch(ptr %ptr, i32 0, i32 3, i32 0)