[llvm-branch-commits] [clang] 8f4dd44 - [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

[Tobias Hieta via llvm-branch-commits]

Author: wangpc
Date: 2023-08-11T09:01:30+02:00
New Revision: 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8

URL: https://github.com/llvm/llvm-project/commit/8f4dd44097c9ae25dd203d5ac87f3b48f854bba8
DIFF: https://github.com/llvm/llvm-project/commit/8f4dd44097c9ae25dd203d5ac87f3b48f854bba8.diff

LOG: [RISCV] Fix wrong type prototype of RVVSlideOneBuiltinSet

We need unsigned integer here.

Fixes #64534

Reviewed By: eopXD

Differential Revision: https://reviews.llvm.org/D157476

(cherry picked from commit 5a3753f35632f8fd7920c5c99b1237113b5c435e)

Added: 
    

Modified: 
    clang/include/clang/Basic/riscv_vector.td

Removed: 
    


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diff  --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 5bf1916df117ba..6adc6003134142 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -112,7 +112,7 @@ multiclass RVVIntBinBuiltinSet
 multiclass RVVSlideOneBuiltinSet
     : RVVOutOp1BuiltinSet<NAME, "csil",
                           [["vx", "v", "vve"],
-                           ["vx", "Uv", "UvUve"]]>;
+                           ["vx", "Uv", "UvUvUe"]]>;
 
 multiclass RVVSignedShiftBuiltinSet
     : RVVOutOp1BuiltinSet<NAME, "csil",