[llvm-branch-commits] [llvm] 026e0ff - [RISCV] Add back handling of X > -1 to ISD::SETCC lowering.

[Tobias Hieta via llvm-branch-commits]

Author: Craig Topper
Date: 2023-08-10T10:27:46+02:00
New Revision: 026e0ff58c1eb8375dffb7d52d7623eff999597d

URL: https://github.com/llvm/llvm-project/commit/026e0ff58c1eb8375dffb7d52d7623eff999597d
DIFF: https://github.com/llvm/llvm-project/commit/026e0ff58c1eb8375dffb7d52d7623eff999597d.diff

LOG: [RISCV] Add back handling of X > -1 to ISD::SETCC lowering.

There are cases where the -1 doesn't become visible until lowering
so the folding doesn't have a chance to run.

I think in these cases there is a missed DAGCombine for truncate (undef),
which I may fix separately, but RISC-V backend should protect itself.

Fixes #64503.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D157314

(cherry picked from commit 7cc615413fd7c93421052a193bc3e114465747c9)

Added: 
    llvm/test/CodeGen/RISCV/pr64503.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f49c5011607f99..5e3b42fdc7abae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5368,9 +5368,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       if (isa<ConstantSDNode>(RHS)) {
         int64_t Imm = cast<ConstantSDNode>(RHS)->getSExtValue();
         if (Imm != 0 && isInt<12>((uint64_t)Imm + 1)) {
-          // X > -1 should have been replaced with false.
-          assert((CCVal != ISD::SETUGT || Imm != -1) &&
-                 "Missing canonicalization");
+          // If this is an unsigned compare and the constant is -1, incrementing
+          // the constant would change behavior. The result should be false.
+          if (CCVal == ISD::SETUGT && Imm == -1)
+            return DAG.getConstant(0, DL, VT);
           // Using getSetCCSwappedOperands will convert SET(U)GT->SET(U)LT.
           CCVal = ISD::getSetCCSwappedOperands(CCVal);
           SDValue SetCC = DAG.getSetCC(

diff  --git a/llvm/test/CodeGen/RISCV/pr64503.ll b/llvm/test/CodeGen/RISCV/pr64503.ll
new file mode 100644
index 00000000000000..921187144ffd80
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr64503.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
+
+define i1 @f(i64 %LGV1) {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a1, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    snez a0, a1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ret
+  %B1 = xor i64 %LGV1, %LGV1
+  %B2 = srem i64 1, %B1
+  %B5 = lshr i64 1, %B2
+  %C4 = icmp ule i64 %LGV1, %B5
+  ret i1 %C4
+}
+
+define i64 @g(ptr %A, i64 %0) {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a2, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    slti a0, a2, 1
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    sb a0, 0(zero)
+; CHECK-NEXT:    ret
+  store i64 poison, ptr %A, align 4
+  %LGV1 = load i64, ptr %A, align 4
+  %B1 = ashr i64 1, %LGV1
+  %C = icmp sle i64 %0, %B1
+  store i1 %C, ptr null, align 1
+  ret i64 %LGV1
+}