[llvm-branch-commits] [llvm] e59e0b9 - ARMFrameLowering.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

[Tom Stellard via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2023-04-03T21:47:57-07:00
New Revision: e59e0b9bd37463a2c570a99d5db41ee81ddce3c8

URL: https://github.com/llvm/llvm-project/commit/e59e0b9bd37463a2c570a99d5db41ee81ddce3c8
DIFF: https://github.com/llvm/llvm-project/commit/e59e0b9bd37463a2c570a99d5db41ee81ddce3c8.diff

LOG: ARMFrameLowering.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.

(cherry picked from commit b206145323fafc75d82efcc7e154218e37480953)

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMFrameLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index ae5a45ff5985..724705c25e3a 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -363,7 +363,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
         MBBI->getOperand(3).getImm() == -4) {
       unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
       MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
-                .addImm(1 << Reg)
+                .addImm(1ULL << Reg)
                 .addImm(/*Wide=*/1)
                 .setMIFlags(Flags);
     } else {
@@ -377,7 +377,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
         MBBI->getOperand(3).getImm() == 4) {
       unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
       MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
-                .addImm(1 << Reg)
+                .addImm(1ULL << Reg)
                 .addImm(/*Wide=*/1)
                 .setMIFlags(Flags);
     } else {