[llvm-branch-commits] [llvm] bb408f1 - save for switching

[Jeffrey Byrnes via llvm-branch-commits]

Author: Jeffrey Byrnes
Date: 2022-10-14T14:54:05-07:00
New Revision: bb408f1e1a8a97826b28e3e9327bd8ad91dbd5a1

URL: https://github.com/llvm/llvm-project/commit/bb408f1e1a8a97826b28e3e9327bd8ad91dbd5a1
DIFF: https://github.com/llvm/llvm-project/commit/bb408f1e1a8a97826b28e3e9327bd8ad91dbd5a1.diff

LOG: save for switching

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    llvm/lib/Target/AMDGPU/SIInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index fe358aa89881..6c1c296d8014 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -974,6 +974,9 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
   }
 
   for (const SDValue &Op : Node->op_values()) {
+    errs() << "Checking op: ";
+    Op.dump();
+    errs() << "\n";
     assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
               TargetLowering::TypeLegal ||
             Op.getOpcode() == ISD::TargetConstant ||

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index abb864c6a829..c32f92cd0da0 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -84,8 +84,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
 
   addRegisterClass(MVT::v4i8, &AMDGPU::SReg_32RegClass);
-  //addRegisterClass(MVT::v2i8, &AMDGPU::SReg_32RegClass);
+  addRegisterClass(MVT::v2i8, &AMDGPU::SReg_32RegClass);
   addRegisterClass(MVT::i8, &AMDGPU::SReg_32RegClass);
+  //addRegisterClass(MVT::i8, &AMDGPU::VReg_32RegClass);
 
   addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
 
@@ -5719,9 +5720,14 @@ SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
   unsigned EltSize = EltVT.getSizeInBits();
   SDLoc SL(Op);
 
+
   // Specially handle the case of v4i16 with static indexing.
   unsigned NumElts = VecVT.getVectorNumElements();
   auto KIdx = dyn_cast<ConstantSDNode>(Idx);
+
+  errs() << "legalizing insert_ve with num elts, eltsize " << NumElts << " " << EltSize << "\n";
+
+
   if (NumElts == 4 && EltSize == 16 && KIdx) {
     SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
 

diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index d88272fc485c..f6644d131b68 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2788,7 +2788,29 @@ def : GCNPat <
   (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
 >;
 
+/*
+def : GCNPat <
+  (v4i8 (build_vector (i8:$src0), (i8:$src1), (i8:$src2), (i8:$src3))),
+  (v4i8 (i32 (V_OR_B32_e64 (i32 (S_LSHL_B32 SReg_32:$src3, (i32 24))), (i32 (V_OR_B32_e64 (i32 (S_LSHL_B32 SReg_32:$src2, (i32 16))), (i32 (V_OR_B32_e64 (i32 (S_LSHL_B32 SReg_32:$src1, (i32 8))), SReg_32:$src0)))))))
+>;
+
+
+def : GCNPat <
+  (v2i8 (build_vector (i8:$src0), (i8:$src1))),
+  (v2i8 (i16 (V_OR_B32_e64 (i16 (S_LSHL_B32 SReg_32:$src1, (i32 8))), SReg_32:$src0)))
+>;
+
 
+def : GCNPat <
+  (v2i8 (build_vector i8:$src0, (i8 undef))),
+  (COPY $src0)
+>;
+
+def : GCNPat <
+  (v2i8 (DivergentBinFrag<build_vector> (i8 undef), (i8 SReg_32:$src1))),
+  (v2i8 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
+>;
+*/
 
 foreach Ty = [i16, f16] in {