[llvm-branch-commits] [llvm] e0fb937 - debugging v2i8/v3i8

[Jeffrey Byrnes via llvm-branch-commits]

Author: Jeffrey Byrnes
Date: 2022-10-13T11:52:20-07:00
New Revision: e0fb937455d9339a286f82fc2a2a9c38a0370831

URL: https://github.com/llvm/llvm-project/commit/e0fb937455d9339a286f82fc2a2a9c38a0370831
DIFF: https://github.com/llvm/llvm-project/commit/e0fb937455d9339a286f82fc2a2a9c38a0370831.diff

LOG: debugging v2i8/v3i8

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/lib/CodeGen/TargetLoweringBase.cpp
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 629e7b84cf71..528ee108408f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -966,12 +966,32 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
     return;
 
 #ifndef NDEBUG
-  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+/*
+  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
+    errs() << "Checking legality of: \n";
+    auto temp = Node->getOperand(i-1);
+    temp.dump();
+    errs() << "\n";
     assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
              TargetLowering::TypeLegal &&
            "Unexpected illegal type!");
+  }
+*/
+  errs() << "Quick Legal Check\n";
+  for (const SDValue &Op : Node->op_values()) {
+    Op.dump();
+    errs() << "\n";
+    assert(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
+             TargetLowering::TypeLegal &&
+           "Unexpected illegal type!");
+  }
+
+  errs() << "Full Legal Check\n";
 
   for (const SDValue &Op : Node->op_values()) {
+    errs() << "Checking op: \n";
+    Op.dump();
+    errs() << "\n";
     if (TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
               TargetLowering::TypeLegal) errs() << "TargetLowering::TypeLegal\n";
     if (Op.getOpcode() == ISD::Register) errs() << "Register\n";

diff  --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 973631848662..363bafb48c55 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -954,12 +954,16 @@ void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
 
 TargetLoweringBase::LegalizeKind
 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
+  errs() << "in TLB::getTypeConv\n";
   // If this is a simple type, use the ComputeRegisterProp mechanism.
   if (VT.isSimple()) {
+    errs() << "isSimple]\n";
     MVT SVT = VT.getSimpleVT();
     assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
     MVT NVT = TransformToType[SVT.SimpleTy];
+    errs() << "Found TypeTransform" << (int)NVT.SimpleTy << "\n";
     LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
+    errs() << "Found TypeAction: " << (int)LA << "\n";
 
     assert((LA == TypeLegal || LA == TypeSoftenFloat ||
             LA == TypeSoftPromoteHalf ||

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f962e49418c5..f92bde72867a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -245,7 +245,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
         MVT::v2f64,  MVT::v4i16,  MVT::v4f16,  MVT::v3i64,  MVT::v3f64,
         MVT::v6i32,  MVT::v6f32,  MVT::v4i64,  MVT::v4f64,  MVT::v8i64,
         MVT::v8f64,  MVT::v8i16,  MVT::v8f16,  MVT::v16i16, MVT::v16f16,
-        MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32, MVT::v4i8}) {
+        MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32, MVT::v4i8,
+        MVT::v2i8}) {
     for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
       switch (Op) {
       case ISD::LOAD:
@@ -5777,6 +5778,8 @@ SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
                                                   SelectionDAG &DAG) const {
   SDLoc SL(Op);
 
+
+
   EVT ResultVT = Op.getValueType();
   SDValue Vec = Op.getOperand(0);
   SDValue Idx = Op.getOperand(1);
@@ -5784,6 +5787,8 @@ SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
   unsigned VecSize = VecVT.getSizeInBits();
   EVT EltVT = VecVT.getVectorElementType();
 
+  errs() << "found EVE with res: " << ResultVT.getEVTString() << " and src: " << VecVT.getEVTString() << "\n";
+
   DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
 
   // Make sure we do any optimizations that will make it easier to fold
@@ -5859,6 +5864,11 @@ SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
     return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
   }
 
+  if (ResultVT == MVT::i8) {
+    SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i8, Elt);
+    return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
+  }
+
   return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
 }
 
@@ -6038,11 +6048,11 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
   Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Lo);
 
   SDValue Or = DAG.getNode(ISD::OR, SL, IntVT, Lo, ShlHi);
-  auto temp = DAG.getNode(ISD::BITCAST, SL, VT, Or);
-  errs() << "Build Final node : \n";
-  temp->dump();
-  errs() << "\n";
-  return temp;
+  return DAG.getNode(ISD::BITCAST, SL, VT, Or);
+  //errs() << "Build Final node : \n";
+  //temp->dump();
+  //errs() << "\n";
+  //return Or;
 }
 
 bool