[llvm-branch-commits] [llvm] 92016f9 - [SiFive] Support assembler and dis-assembler for xsfvcp extension.
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Nov 14 23:54:02 PST 2022
Author: Nelson Chu
Date: 2022-11-14T23:51:19-08:00
New Revision: 92016f97364fec11d7583c4d5079acfec40a8e24
URL: https://github.com/llvm/llvm-project/commit/92016f97364fec11d7583c4d5079acfec40a8e24
DIFF: https://github.com/llvm/llvm-project/commit/92016f97364fec11d7583c4d5079acfec40a8e24.diff
LOG: [SiFive] Support assembler and dis-assembler for xsfvcp extension.
I can not reuse the defined RVVconstraints directly, since we are used to
assume the operand order is rd, rs2, and then rs1. But for the VCIX
instructions, the first operand should be the uimm2 payload, rather than
the rd. I have two options here, one is to define new RVVconstraints,
but that will need more bits in the RVVConstraint. So I choose another
easy way, to handle the VCIX constraints specially in the validateInstruction,
but reuse the defined VS2Constraint and VS1Constraint.
Architecture spec: https://docs.google.com/document/d/1t7KkKILmmQ0mAgnDLj1s2ks-UXkMR9cWOHuIsewovPE/edit
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td
llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
llvm/test/MC/RISCV/rvv/xsfvcp.s
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 86c8af874d2da..357e9783ddde8 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -566,6 +566,14 @@ struct RISCVOperand : public MCParsedAsmOperand {
return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isUImm1() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isUInt<1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+ }
bool isUImm2() { return IsUImm<2>(); }
bool isUImm3() { return IsUImm<3>(); }
bool isUImm5() { return IsUImm<5>(); }
@@ -1151,6 +1159,8 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
if (isRV64())
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
+ case Match_InvalidUImm1:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 1) - 1);
case Match_InvalidUImm2:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
case Match_InvalidUImm3:
@@ -2596,6 +2606,27 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (Constraints == RISCVII::NoConstraint)
return false;
+ unsigned VCIXOpcode = Inst.getOpcode();
+ if (VCIXOpcode == RISCV::VC_V_XVW || VCIXOpcode == RISCV::VC_V_IVW ||
+ VCIXOpcode == RISCV::VC_V_FVW || VCIXOpcode == RISCV::VC_V_VVW) {
+ // Operands Opcode, Dst, uimm, Dst, Rs2, Rs1 for VC_V_XVW.
+ unsigned VCIXDst = Inst.getOperand(0).getReg();
+ SMLoc VCIXDstLoc = Operands[2]->getStartLoc();
+ if (Constraints & RISCVII::VS1Constraint) {
+ unsigned VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
+ if (VCIXDst == VCIXRs1)
+ return Error(VCIXDstLoc, "The destination vector register group cannot"
+ " overlap the source vector register group.");
+ }
+ if (Constraints & RISCVII::VS2Constraint) {
+ unsigned VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
+ if (VCIXDst == VCIXRs2)
+ return Error(VCIXDstLoc, "The destination vector register group cannot"
+ " overlap the source vector register group.");
+ }
+ }
+ else {
+
unsigned DestReg = Inst.getOperand(0).getReg();
// Operands[1] will be the first operand, DestReg.
SMLoc Loc = Operands[1]->getStartLoc();
@@ -2634,6 +2665,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
return Error(Loc, "The destination vector register group cannot overlap"
" the mask register.");
}
+
+ }
+
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 57639d29ec975..0580b766fcc9b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -249,6 +249,7 @@ enum OperandType : unsigned {
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
OPERAND_RVKRNUM,
+ OPERAND_UIMM1,
OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index 20e15e7e0349e..d210ff8913109 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -124,6 +124,51 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let RVVConstraint = VMConstraint;
}
+class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+ bits<2> funct6_lo2;
+ bit vm;
+
+ let Inst{31-28} = funct6_hi4;
+ let Inst{27-26} = funct6_lo2;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Opcode = OPC_CUSTOM_2.Value;
+
+ let Uses = [VTYPE, VL];
+ let RVVConstraint = NoConstraint;
+}
+
+class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+ bit funct6_lo1;
+ bit vm;
+
+ let Inst{31-28} = funct6_hi4;
+ let Inst{27} = 1;
+ let Inst{26} = funct6_lo1;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Opcode = OPC_CUSTOM_2.Value;
+
+ let Uses = [VTYPE, VL];
+ let RVVConstraint = NoConstraint;
+}
+
class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index c05527cff95d9..33ad49a3f324e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1328,6 +1328,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;
break;
+ case RISCVOp::OPERAND_UIMM1:
+ Ok = isUInt<1>(Imm);
+ break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index ea89033776be3..a5ec8ea754082 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -181,6 +181,41 @@ def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
let OperandNamespace = "RISCVOp";
}
+// The payload and simm5_i32 operands are all marked as ImmArg in the IR
+// intrinsic and will be target constant, so use TImmLeaf rather than ImmLeaf.
+def payload1 : Operand<i32>, TImmLeaf<i32, [{return isUInt<1>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<1>;
+ let DecoderMethod = "decodeUImmOperand<1>";
+ let OperandType = "OPERAND_UIMM1";
+ let OperandNamespace = "RISCVOp";
+}
+
+def payload2 : Operand<i32>, TImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<2>;
+ let DecoderMethod = "decodeUImmOperand<2>";
+ let OperandType = "OPERAND_UIMM2";
+ let OperandNamespace = "RISCVOp";
+}
+
+def payload5 : Operand<i32>, TImmLeaf<i32, [{return isUInt<5>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<5>;
+ let DecoderMethod = "decodeUImmOperand<5>";
+ let OperandType = "OPERAND_UIMM5";
+ let OperandNamespace = "RISCVOp";
+}
+
+def simm5_i32 : Operand<i32>, TImmLeaf<i32, [{return isInt<5>(Imm);}]> {
+ let ParserMatchClass = SImmAsmOperand<5>;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeSImmOperand<5>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<5>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
def uimm2 : Operand<XLenVT> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2>";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 1b4813720d97b..a40db41ce4a32 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1665,4 +1665,5 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
}
} // Predicates = [HasVInstructionsI64, IsRV64]
+include "RISCVInstrInfoXsf.td"
include "RISCVInstrInfoVPseudos.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td
new file mode 100644
index 0000000000000..32389ca098959
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td
@@ -0,0 +1,117 @@
+//===-- RISCVInstrInfoXsf.td - SiFive custom instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the SiFive custom instructions.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XSFVCP extension instructions.
+//===----------------------------------------------------------------------===//
+
+def VCIXVS2 : RISCVVConstraint<VS2Constraint.Value>;
+def VCIXVS2VS1 : RISCVVConstraint<!or(VS2Constraint.Value,
+ VS1Constraint.Value)>;
+
+class VCIXType<bits<4> val> {
+ bits<4> Val = val;
+}
+
+def VCIX_X : VCIXType<0b0000>;
+def VCIX_XV : VCIXType<0b0010>;
+def VCIX_XVV : VCIXType<0b1010>;
+def VCIX_XVW : VCIXType<0b1111>;
+
+class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {
+ dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
+}
+
+class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd,
+ DAGOperand TyRs2, DAGOperand TyRs1, bit HaveOutputDst> {
+ string OpcodeStr = !if(HaveOutputDst, "sf.vc.v." # suffix,
+ "sf.vc." # suffix);
+ bits<4> Funct6_hi4 = type.Val;
+ bits<3> Funct3 = !cond(!eq(TyRs1, VR): 0b000,
+ !eq(TyRs1, GPR): 0b100,
+ !eq(TyRs1, FPR32): 0b101,
+ !eq(TyRs1, simm5_i32): 0b011);
+ dag Outs = !if(!not(HaveOutputDst), (outs),
+ !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)),
+ (outs TyRd:$rd_wb), (outs TyRd:$rd)));
+ dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins payload2:$funct6_lo2),
+ (ins payload1:$funct6_lo1)),
+ !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X),
+ !eq(type, VCIX_XV))),
+ (ins), (ins TyRd:$rd)),
+ (ins TyRs2:$rs2),
+ (ins TyRs1:$rs1),
+ !if(!eq(type, VCIX_X), 1, 0)>.Ins;
+ string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1",
+ !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",
+ "$funct6_lo1, $rd, $rs2, $rs1"));
+ string Constraints = !if(!not(HaveOutputDst), "",
+ !if(!or(!eq(type, VCIX_XVV),
+ !eq(type, VCIX_XVW)), "$rd = $rd_wb", ""));
+ RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst),
+ !ne(type, VCIX_XVW)), NoConstraint,
+ !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2));
+}
+
+class CustomSiFiveVCIX<VCIXInfo info>
+ : RVInstVCCustom2<info.Funct6_hi4, info.Funct3, info.Outs,
+ info.Ins, info.OpcodeStr, info.Prototype> {
+ let Constraints = info.Constraints;
+ let RVVConstraint = info.RVVConstraint;
+}
+
+class CustomSiFiveVCIF<VCIXInfo info>
+ : RVInstVCFCustom2<info.Funct6_hi4, info.Funct3, info.Outs,
+ info.Ins, info.OpcodeStr, info.Prototype> {
+ let Constraints = info.Constraints;
+ let RVVConstraint = info.RVVConstraint;
+}
+
+multiclass CustomSiFiveVCIXorVCIF<string suffix, VCIXType type,
+ DAGOperand TyRd, DAGOperand TyRs2,
+ DAGOperand TyRs1, bit HaveOutputDst> {
+ defvar info = VCIXInfo<suffix, type, TyRd, TyRs2, TyRs1, HaveOutputDst>;
+ if !eq(TyRs1, FPR32) then {
+ def NAME : CustomSiFiveVCIF<info>;
+ } else {
+ def NAME : CustomSiFiveVCIX<info>;
+ }
+}
+
+multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
+ DAGOperand InTyRd, DAGOperand InTyRs2,
+ DAGOperand InTyRs1> {
+ let vm = 1 in
+ defm VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2,
+ InTyRs1, 0>;
+ let vm = 0 in
+ defm VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,
+ InTyRs1, 1>;
+}
+
+let Predicates = [HasExtXsfvcp], mayLoad = 0, mayStore = 0,
+ hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
+ defm X : CustomSiFiveVCIX<"x", VCIX_X, payload5, payload5, GPR>, Sched<[]>;
+ defm I : CustomSiFiveVCIX<"i", VCIX_X, payload5, payload5, simm5_i32>, Sched<[]>;
+ defm XV : CustomSiFiveVCIX<"xv", VCIX_XV, payload5, VR, GPR>, Sched<[]>;
+ defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, payload5, VR, simm5_i32>, Sched<[]>;
+ defm VV : CustomSiFiveVCIX<"vv", VCIX_XV, payload5, VR, VR>, Sched<[]>;
+ defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, payload5, VR, FPR32>, Sched<[]>;
+ defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR, VR, GPR>, Sched<[]>;
+ defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5_i32>, Sched<[]>;
+ defm VVV : CustomSiFiveVCIX<"vvv", VCIX_XVV, VR, VR, VR>, Sched<[]>;
+ defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR, VR, FPR32>, Sched<[]>;
+ defm XVW : CustomSiFiveVCIX<"xvw", VCIX_XVW, VR, VR, GPR>, Sched<[]>;
+ defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR, VR, simm5_i32>, Sched<[]>;
+ defm VVW : CustomSiFiveVCIX<"vvw", VCIX_XVW, VR, VR, VR>, Sched<[]>;
+ defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 8169e478f4987..d940f25722b1b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -244,6 +244,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
// FIXME: Consider Zdinx in the future
bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
+ bool hasXsfvcpInstructions() const { return HasExtXsfvcp; }
// F16 and F64 both require F32.
bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
unsigned getMaxInterleaveFactor() const {
diff --git a/llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s b/llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
new file mode 100644
index 0000000000000..7e8b44239d518
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+v,+xsfvcp %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+sf.vc.v.vvw 0x3, v0, v2, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: sf.vc.v.vvw 0x3, v0, v2, v0
+
+sf.vc.v.xvw 0x3, v0, v0, a1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: sf.vc.v.xvw 0x3, v0, v0, a1
+
+sf.vc.v.ivw 0x3, v0, v0, 15
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: sf.vc.v.ivw 0x3, v0, v0, 15
+
+sf.vc.v.fvw 0x1, v0, v0, fa1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: sf.vc.v.fvw 0x1, v0, v0, fa1
diff --git a/llvm/test/MC/RISCV/rvv/xsfvcp.s b/llvm/test/MC/RISCV/rvv/xsfvcp.s
new file mode 100644
index 0000000000000..cbb55d805f1eb
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/xsfvcp.s
@@ -0,0 +1,177 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvcp %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvcp %s \
+# RUN: | llvm-objdump -d --mattr=+v,+xsfvcp - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvcp %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sf.vc.x 0x3, 0xf, 0x1f, a1
+# CHECK-INST: sf.vc.x 3, 15, 31, a1
+# CHECK-ENCODING: [0xdb,0xcf,0xf5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db cf f5 0e <unknown>
+
+sf.vc.i 0x3, 0xf, 0x1f, 15
+# CHECK-INST: sf.vc.i 3, 15, 31, 15
+# CHECK-ENCODING: [0xdb,0xbf,0xf7,0x0e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db bf f7 0e <unknown>
+
+sf.vc.vv 0x3, 0x1f, v2, v1
+# CHECK-INST: sf.vc.vv 3, 31, v2, v1
+# CHECK-ENCODING: [0xdb,0x8f,0x20,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db 8f 20 2e <unknown>
+
+sf.vc.xv 0x3, 0x1f, v2, a1
+# CHECK-INST: sf.vc.xv 3, 31, v2, a1
+# CHECK-ENCODING: [0xdb,0xcf,0x25,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db cf 25 2e <unknown>
+
+sf.vc.iv 0x3, 0x1f, v2, 15
+# CHECK-INST: sf.vc.iv 3, 31, v2, 15
+# CHECK-ENCODING: [0xdb,0xbf,0x27,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db bf 27 2e <unknown>
+
+sf.vc.fv 0x1, 0x1f, v2, fa1
+# CHECK-INST: sf.vc.fv 1, 31, v2, fa1
+# CHECK-ENCODING: [0xdb,0xdf,0x25,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: db df 25 2e <unknown>
+
+sf.vc.vvv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.vvv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xae]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b 80 20 ae <unknown>
+
+sf.vc.xvv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.xvv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xae]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 25 ae <unknown>
+
+sf.vc.ivv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.ivv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xae]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 27 ae <unknown>
+
+sf.vc.fvv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.fvv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xae]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b d0 25 ae <unknown>
+
+sf.vc.vvw 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.vvw 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b 80 20 fe <unknown>
+
+sf.vc.xvw 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.xvw 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 25 fe <unknown>
+
+sf.vc.ivw 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.ivw 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 27 fe <unknown>
+
+sf.vc.fvw 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.fvw 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b d0 25 fe <unknown>
+
+sf.vc.v.x 0x3, 0xf, v0, a1
+# CHECK-INST: sf.vc.v.x 3, 15, v0, a1
+# CHECK-ENCODING: [0x5b,0xc0,0xf5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 f5 0c <unknown>
+
+sf.vc.v.i 0x3, 0xf, v0, 15
+# CHECK-INST: sf.vc.v.i 3, 15, v0, 15
+# CHECK-ENCODING: [0x5b,0xb0,0xf7,0x0c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 f7 0c <unknown>
+
+sf.vc.v.vv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b 80 20 2c <unknown>
+
+sf.vc.v.xv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 25 2c <unknown>
+
+sf.vc.v.iv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.iv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 27 2c <unknown>
+
+sf.vc.v.fv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b d0 25 2c <unknown>
+
+sf.vc.v.vvv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vvv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xac]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b 80 20 ac <unknown>
+
+sf.vc.v.xvv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xvv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xac]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 25 ac <unknown>
+
+sf.vc.v.ivv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.ivv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xac]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 27 ac <unknown>
+
+sf.vc.v.fvv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fvv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xac]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b d0 25 ac <unknown>
+
+sf.vc.v.vvw 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vvw 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b 80 20 fc <unknown>
+
+sf.vc.v.xvw 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xvw 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b c0 25 fc <unknown>
+
+sf.vc.v.ivw 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.ivw 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b b0 27 fc <unknown>
+
+sf.vc.v.fvw 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fvw 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Xsfvcp'
+# CHECK-UNKNOWN: 5b d0 25 fc <unknown>
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