[llvm-branch-commits] [llvm] 967296b - [RISCV] Fix inline asm errors in zfinx

[Shao-Ce SUN via llvm-branch-commits]

Author: Shao-Ce SUN
Date: 2022-03-02T14:31:23+08:00
New Revision: 967296bfefee9740b1dfb4644970d776e1b37b5b

URL: https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b
DIFF: https://github.com/llvm/llvm-project/commit/967296bfefee9740b1dfb4644970d776e1b37b5b.diff

LOG: [RISCV] Fix inline asm errors in zfinx

Patch is from craig.topper's comments in https://reviews.llvm.org/D93298

Added: 
    llvm/test/CodeGen/RISCV/zfinx-types.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7f5555b9b7a85..19935caa34dfb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10466,7 +10466,29 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   }
 
-  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+  std::pair<Register, const TargetRegisterClass *> Res =
+      TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+
+  if (Res.second == &RISCV::GPRF32RegClass) {
+    if (!Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF64RegClass ||
+      Res.second == &RISCV::GPRPF64RegClass) {
+    if (Subtarget.is64Bit() || VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  if (Res.second == &RISCV::GPRF16RegClass) {
+    if (VT == MVT::Other)
+      return std::make_pair(Res.first, &RISCV::GPRRegClass);
+    return std::make_pair(0, nullptr);
+  }
+
+  return Res;
 }
 
 unsigned

diff  --git a/llvm/test/CodeGen/RISCV/zfinx-types.ll b/llvm/test/CodeGen/RISCV/zfinx-types.ll
new file mode 100644
index 0000000000000..9cbc7d9ce219b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zfinx-types.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RVZFINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RVZFINX %s
+
+define float @test_float(float %x) {
+; RVZFINX-LABEL: test_float:
+; RVZFINX:       # %bb.0:
+; RVZFINX-NEXT:    .cfi_def_cfa_offset 0
+; RVZFINX-NEXT:    li a0, 0
+; RVZFINX-NEXT:    #APP
+; RVZFINX-NEXT:    mv a0, a0
+; RVZFINX-NEXT:    #NO_APP
+; RVZFINX-NEXT:    li a0, 0
+; RVZFINX-NEXT:    ret
+  %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
+  ret float 0.000000e+00
+}