[llvm-branch-commits] [lld] ff421be - [ELF] Support R_PPC_NONE/R_PPC64_NONE in getImplicitAddend

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2022-02-04T15:16:30-08:00
New Revision: ff421befd25827223952913d58e90d56e7779eb6

URL: https://github.com/llvm/llvm-project/commit/ff421befd25827223952913d58e90d56e7779eb6
DIFF: https://github.com/llvm/llvm-project/commit/ff421befd25827223952913d58e90d56e7779eb6.diff

LOG: [ELF] Support R_PPC_NONE/R_PPC64_NONE in getImplicitAddend

Similar to f457863ae345d2635026501f5383e0e625869639

(cherry picked from commit 53fc5d9b9a0110f097c6e9f7aa3bff3621eaf268)

Added: 
    

Modified: 
    lld/ELF/Arch/PPC.cpp
    lld/ELF/Arch/PPC64.cpp
    lld/test/ELF/relocation-none.test

Removed: 
    


################################################################################
diff  --git a/lld/ELF/Arch/PPC.cpp b/lld/ELF/Arch/PPC.cpp
index 97e4d66331381..315ac7df608d0 100644
--- a/lld/ELF/Arch/PPC.cpp
+++ b/lld/ELF/Arch/PPC.cpp
@@ -30,6 +30,7 @@ class PPC final : public TargetInfo {
   RelExpr getRelExpr(RelType type, const Symbol &s,
                      const uint8_t *loc) const override;
   RelType getDynRel(RelType type) const override;
+  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void writeGotHeader(uint8_t *buf) const override;
   void writePltHeader(uint8_t *buf) const override {
     llvm_unreachable("should call writePPC32GlinkSection() instead");
@@ -275,6 +276,17 @@ RelType PPC::getDynRel(RelType type) const {
   return R_PPC_NONE;
 }
 
+int64_t PPC::getImplicitAddend(const uint8_t *buf, RelType type) const {
+  switch (type) {
+  case R_PPC_NONE:
+    return 0;
+  default:
+    internalLinkerError(getErrorLocation(buf),
+                        "cannot read addend for relocation " + toString(type));
+    return 0;
+  }
+}
+
 static std::pair<RelType, uint64_t> fromDTPREL(RelType type, uint64_t val) {
   uint64_t dtpBiasedVal = val - 0x8000;
   switch (type) {

diff  --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp
index d9e4fc97ea0be..c083484f42804 100644
--- a/lld/ELF/Arch/PPC64.cpp
+++ b/lld/ELF/Arch/PPC64.cpp
@@ -363,6 +363,7 @@ class PPC64 final : public TargetInfo {
   RelExpr getRelExpr(RelType type, const Symbol &s,
                      const uint8_t *loc) const override;
   RelType getDynRel(RelType type) const override;
+  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void writePltHeader(uint8_t *buf) const override;
   void writePlt(uint8_t *buf, const Symbol &sym,
                 uint64_t pltEntryAddr) const override;
@@ -1059,6 +1060,17 @@ RelType PPC64::getDynRel(RelType type) const {
   return R_PPC64_NONE;
 }
 
+int64_t PPC64::getImplicitAddend(const uint8_t *buf, RelType type) const {
+  switch (type) {
+  case R_PPC64_NONE:
+    return 0;
+  default:
+    internalLinkerError(getErrorLocation(buf),
+                        "cannot read addend for relocation " + toString(type));
+    return 0;
+  }
+}
+
 void PPC64::writeGotHeader(uint8_t *buf) const {
   write64(buf, getPPC64TocBase());
 }

diff  --git a/lld/test/ELF/relocation-none.test b/lld/test/ELF/relocation-none.test
index a9ba6402ae8de..4e808cc67c0d1 100644
--- a/lld/test/ELF/relocation-none.test
+++ b/lld/test/ELF/relocation-none.test
@@ -15,6 +15,14 @@
 # RUN: ld.lld -r %t.o -o %t
 # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
 
+# RUN: yaml2obj -DBITS=32 -DMACHINE=PPC %s -o %t.o
+# RUN: ld.lld -r %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+
+# RUN: yaml2obj -DMACHINE=PPC64 %s -o %t.o
+# RUN: ld.lld -r %t.o -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+
 # RUN: yaml2obj -DMACHINE=RISCV %s -o %t.o
 # RUN: ld.lld -r %t.o -o %t
 # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s