[llvm-branch-commits] [llvm] 70f6876 - [RISCV][NFC] Use Arrayref in TargetLowering functions.
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Dec 21 05:13:25 PST 2022
Author: ping.deng
Date: 2022-12-21T20:58:51+08:00
New Revision: 70f68768453d3663a73edd93fc6f4cd8dfbf1a40
URL: https://github.com/llvm/llvm-project/commit/70f68768453d3663a73edd93fc6f4cd8dfbf1a40
DIFF: https://github.com/llvm/llvm-project/commit/70f68768453d3663a73edd93fc6f4cd8dfbf1a40.diff
LOG: [RISCV][NFC] Use Arrayref in TargetLowering functions.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140464
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 71382736270f..1c64c717d084 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -326,18 +326,17 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW,
ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
+ static const unsigned FPRndMode[] = {
+ ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
+ ISD::FROUNDEVEN};
+
if (Subtarget.hasStdExtZfhOrZfhmin())
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
if (Subtarget.hasStdExtZfhOrZfhmin()) {
if (Subtarget.hasStdExtZfh()) {
setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
- setOperationAction(ISD::FCEIL, MVT::f16, Custom);
- setOperationAction(ISD::FFLOOR, MVT::f16, Custom);
- setOperationAction(ISD::FTRUNC, MVT::f16, Custom);
- setOperationAction(ISD::FRINT, MVT::f16, Custom);
- setOperationAction(ISD::FROUND, MVT::f16, Custom);
- setOperationAction(ISD::FROUNDEVEN, MVT::f16, Custom);
+ setOperationAction(FPRndMode, MVT::f16, Custom);
setOperationAction(ISD::SELECT, MVT::f16, Custom);
} else {
static const unsigned ZfhminPromoteOps[] = {
@@ -386,12 +385,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtF()) {
setOperationAction(FPLegalNodeTypes, MVT::f32, Legal);
- setOperationAction(ISD::FCEIL, MVT::f32, Custom);
- setOperationAction(ISD::FFLOOR, MVT::f32, Custom);
- setOperationAction(ISD::FTRUNC, MVT::f32, Custom);
- setOperationAction(ISD::FRINT, MVT::f32, Custom);
- setOperationAction(ISD::FROUND, MVT::f32, Custom);
- setOperationAction(ISD::FROUNDEVEN, MVT::f32, Custom);
+ setOperationAction(FPRndMode, MVT::f32, Custom);
setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
@@ -407,12 +401,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtD()) {
setOperationAction(FPLegalNodeTypes, MVT::f64, Legal);
if (Subtarget.is64Bit()) {
- setOperationAction(ISD::FCEIL, MVT::f64, Custom);
- setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
- setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
- setOperationAction(ISD::FRINT, MVT::f64, Custom);
- setOperationAction(ISD::FROUND, MVT::f64, Custom);
- setOperationAction(ISD::FROUNDEVEN, MVT::f64, Custom);
+ setOperationAction(FPRndMode, MVT::f64, Custom);
}
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
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