[llvm-branch-commits] [llvm] ddb04d7 - [DAGCombine] Check zext legality in zext-extract-extend combine

[Tobias Hieta via llvm-branch-commits]

Author: Peter Waller
Date: 2022-08-16T08:29:55+02:00
New Revision: ddb04d7968715165363bfb3280c158865bee113d

URL: https://github.com/llvm/llvm-project/commit/ddb04d7968715165363bfb3280c158865bee113d
DIFF: https://github.com/llvm/llvm-project/commit/ddb04d7968715165363bfb3280c158865bee113d.diff

LOG: [DAGCombine] Check zext legality in zext-extract-extend combine

Discussed in D131503.

Fix to D130782.

(cherry picked from commit 898699831b5490d88b993593e5cb415fb2d1983a)

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8d465b9520de0..74ee0bdfbf421 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6360,7 +6360,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     SDValue Extendee = Ext->getOperand(0);
 
     unsigned ScalarWidth = Extendee.getValueType().getScalarSizeInBits();
-    if (N1C->getAPIntValue().isMask(ScalarWidth)) {
+    if (N1C->getAPIntValue().isMask(ScalarWidth) &&
+        (!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, ExtVT))) {
       //    (and (extract_subvector (zext|anyext|sext v) _) iN_mask)
       // => (extract_subvector (iN_zeroext v))
       SDValue ZeroExtExtendee =