[llvm-branch-commits] [llvm] 1ff9aa2 - [IR] Handle constant expressions in containsUndefinedElement()

[Tom Stellard via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-09-10T09:04:21-07:00
New Revision: 1ff9aa2bfe19dc8cefe7ced1a277cc58477b5dcb

URL: https://github.com/llvm/llvm-project/commit/1ff9aa2bfe19dc8cefe7ced1a277cc58477b5dcb
DIFF: https://github.com/llvm/llvm-project/commit/1ff9aa2bfe19dc8cefe7ced1a277cc58477b5dcb.diff

LOG: [IR] Handle constant expressions in containsUndefinedElement()

If the constant is a constant expression, then getAggregateElement()
will return null. Guard against this before calling HasFn().

(cherry picked from commit af382b93831ae6a58bce8bc075458cfd056e3976)

Added: 
    

Modified: 
    llvm/lib/IR/Constants.cpp
    llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index 6c75085a6678d..1e72cb4d3a668 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -315,9 +315,11 @@ containsUndefinedElement(const Constant *C,
       return false;
 
     for (unsigned i = 0, e = cast<FixedVectorType>(VTy)->getNumElements();
-         i != e; ++i)
-      if (HasFn(C->getAggregateElement(i)))
-        return true;
+         i != e; ++i) {
+      if (Constant *Elem = C->getAggregateElement(i))
+        if (HasFn(Elem))
+          return true;
+    }
   }
 
   return false;

diff  --git a/llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll
index e27180b1a8909..b407c908cf2a2 100644
--- a/llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vecreduce.ll
@@ -87,6 +87,15 @@ define i32 @add_poison1() {
   ret i32 %x
 }
 
+define i32 @add_constexpr() {
+; CHECK-LABEL: @add_constexpr(
+; CHECK-NEXT:    [[X:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> bitcast (<4 x i64> <i64 0, i64 1, i64 2, i64 3> to <8 x i32>))
+; CHECK-NEXT:    ret i32 [[X]]
+;
+  %x = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> bitcast (<4 x i64> <i64 0, i64 1, i64 2, i64 3> to <8 x i32>))
+  ret i32 %x
+}
+
 define i32 @mul_0() {
 ; CHECK-LABEL: @mul_0(
 ; CHECK-NEXT:    ret i32 0