[llvm-branch-commits] [llvm] e2de46a - Updated tests
Albion Fung via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Jun 28 13:22:02 PDT 2021
Author: Albion Fung
Date: 2021-06-28T15:21:49-05:00
New Revision: e2de46a63bcaeac2ed3511608c43de1e3c7abccd
URL: https://github.com/llvm/llvm-project/commit/e2de46a63bcaeac2ed3511608c43de1e3c7abccd
DIFF: https://github.com/llvm/llvm-project/commit/e2de46a63bcaeac2ed3511608c43de1e3c7abccd.diff
LOG: Updated tests
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c4bf8af943d3b..c325946290c17 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2230,6 +2230,15 @@ def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
"td $to, $rA, $rB", IIC_IntTrapD, []>;
+def : InstAlias<"tdlle $rA, $rB", (TD 6, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdlge $rA, $rB", (TD 5, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdge $rA, $rB", (TD 12, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdle $rA, $rB", (TD 20, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"twlle $rA, $rB", (TW 6, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twlge $rA, $rB", (TW 5, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twge $rA, $rB", (TW 12, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"twle $rA, $rB", (TW 20, gprc:$rA, gprc:$rB)>;
+
//===----------------------------------------------------------------------===//
// PPC32 Load Instructions.
//
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
index c70a99fca936b..c1bcf28e464d9 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -9,61 +9,109 @@
; tdw
declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlgt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
ret void
}
define dso_local void @test__tdwllt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwllt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdllt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
ret void
}
define dso_local void @test__tdweq(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdeq 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
ret void
}
define dso_local void @test__tdwlge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 5, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
ret void
}
define dso_local void @test__tdwlle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 6, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
ret void
}
define dso_local void @test__tdwgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdgt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
ret void
}
define dso_local void @test__tdwge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 12, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
ret void
}
define dso_local void @test__tdwlt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
ret void
}
define dso_local void @test__tdwle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 20, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
ret void
}
define dso_local void @test__tdwne24(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwne24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdne 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
ret void
}
define dso_local void @test__tdweq31(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq31:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdeq 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
ret void
}
define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw_no_match:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 13, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
ret void
}
@@ -71,6 +119,10 @@ define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
; trapd
declare void @llvm.ppc.trapd(i64 %a)
define dso_local void @test__trapd(i64 %a) {
+; CHECK-LABEL: test__trapd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdnei 3, 0
+; CHECK-NEXT: blr
call void @llvm.ppc.trapd(i64 %a)
ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
index 9ed5793817848..a85645b2a8c6a 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -11,66 +11,118 @@
; tw
declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlgt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
ret void
}
define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twllt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
ret void
}
define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twne 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
ret void
}
define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tweq 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
ret void
}
define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 5, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
ret void
}
define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 6, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
ret void
}
define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twgt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
ret void
}
define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 12, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
ret void
}
define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlt 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
ret void
}
define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 20, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
ret void
}
define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twne 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
ret void
}
define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tweq 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
ret void
}
define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 13, 3, 4
+; CHECK-NEXT: blr
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
ret void
}
@@ -78,6 +130,10 @@ define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
; trap
declare void @llvm.ppc.trap(i32 %a)
define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twnei 3, 0
+; CHECK-NEXT: blr
call void @llvm.ppc.trap(i32 %a)
ret void
}
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