[llvm-branch-commits] [llvm] a7c1239 - [RISCV] Add attribute support for all supported extensions
Simon Cook via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Jan 25 01:07:33 PST 2021
Author: Simon Cook
Date: 2021-01-25T08:58:53Z
New Revision: a7c1239f374907107dcc65a3e6a4b20c53d973c9
URL: https://github.com/llvm/llvm-project/commit/a7c1239f374907107dcc65a3e6a4b20c53d973c9
DIFF: https://github.com/llvm/llvm-project/commit/a7c1239f374907107dcc65a3e6a4b20c53d973c9.diff
LOG: [RISCV] Add attribute support for all supported extensions
This adds support for ".attribute arch" for all extensions that are
currently supported by the compiler.
Differential Revision: https://reviews.llvm.org/D94931
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b4af0e81dfa7..11e7cf1113d2 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1997,7 +1997,33 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
else
return Error(ValueExprLoc, "bad arch string " + Arch);
+ // .attribute arch overrides the current architecture, so unset all
+ // currently enabled extensions
+ clearFeatureBits(RISCV::FeatureRV32E, "e");
+ clearFeatureBits(RISCV::FeatureStdExtM, "m");
+ clearFeatureBits(RISCV::FeatureStdExtA, "a");
+ clearFeatureBits(RISCV::FeatureStdExtF, "f");
+ clearFeatureBits(RISCV::FeatureStdExtD, "d");
+ clearFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+ clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+ clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+ clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+ clearFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+ clearFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+ clearFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+ clearFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+ clearFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+ clearFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+ clearFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc");
+ clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+ clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+ clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+ clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+ clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+
while (!Arch.empty()) {
+ bool DropFirst = true;
if (Arch[0] == 'i')
clearFeatureBits(RISCV::FeatureRV32E, "e");
else if (Arch[0] == 'e')
@@ -2019,19 +2045,57 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
setFeatureBits(RISCV::FeatureStdExtD, "d");
} else if (Arch[0] == 'c') {
setFeatureBits(RISCV::FeatureStdExtC, "c");
+ } else if (Arch[0] == 'b') {
+ setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+ } else if (Arch[0] == 'v') {
+ setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
+ } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
+ StringRef Ext =
+ Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; });
+ if (Ext == "zba")
+ setFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
+ else if (Ext == "zbb")
+ setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb");
+ else if (Ext == "zbc")
+ setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc");
+ else if (Ext == "zbe")
+ setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe");
+ else if (Ext == "zbf")
+ setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf");
+ else if (Ext == "zbm")
+ setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm");
+ else if (Ext == "zbp")
+ setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp");
+ else if (Ext == "zbproposedc")
+ setFeatureBits(RISCV::FeatureExtZbproposedc,
+ "experimental-zbproposedc");
+ else if (Ext == "zbr")
+ setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
+ else if (Ext == "zbs")
+ setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
+ else if (Ext == "zbt")
+ setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+ else if (Ext == "zfh")
+ setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
+ else if (Ext == "zvamo")
+ setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
+ else if (Ext == "zvlsseg")
+ setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+ else
+ return Error(ValueExprLoc, "bad arch string " + Ext);
+ Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; });
+ DropFirst = false;
} else
return Error(ValueExprLoc, "bad arch string " + Arch);
- Arch = Arch.drop_front(1);
+ if (DropFirst)
+ Arch = Arch.drop_front(1);
int major = 0;
int minor = 0;
Arch.consumeInteger(10, major);
Arch.consume_front("p");
Arch.consumeInteger(10, minor);
- if (major != 0 || minor != 0) {
- Arch = Arch.drop_until([](char c) { return c == '_' || c == '"'; });
- Arch = Arch.drop_while([](char c) { return c == '_'; });
- }
+ Arch = Arch.drop_while([](char c) { return c == '_'; });
}
}
@@ -2059,6 +2123,38 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
if (getFeatureBits(RISCV::FeatureStdExtC))
formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
+ if (getFeatureBits(RISCV::FeatureStdExtB))
+ formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
+ if (getFeatureBits(RISCV::FeatureStdExtV))
+ formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+ if (getFeatureBits(RISCV::FeatureExtZfh))
+ formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
+ if (getFeatureBits(RISCV::FeatureExtZba))
+ formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbb))
+ formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbc))
+ formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbe))
+ formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbf))
+ formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbm))
+ formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbp))
+ formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbproposedc))
+ formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbr))
+ formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbs))
+ formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZbt))
+ formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
+ if (getFeatureBits(RISCV::FeatureExtZvamo))
+ formalArchStr = (Twine(formalArchStr) + "_zvamo0p9").str();
+ if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
+ formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p9").str();
getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 5683214c13fd..72206c7360e5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -60,6 +60,38 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
Arch += "_d2p0";
if (STI.hasFeature(RISCV::FeatureStdExtC))
Arch += "_c2p0";
+ if (STI.hasFeature(RISCV::FeatureStdExtB))
+ Arch += "_b0p93";
+ if (STI.hasFeature(RISCV::FeatureStdExtV))
+ Arch += "_v0p9";
+ if (STI.hasFeature(RISCV::FeatureExtZfh))
+ Arch += "_zfh0p1";
+ if (STI.hasFeature(RISCV::FeatureExtZba))
+ Arch += "_zba0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbb))
+ Arch += "_zbb0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbc))
+ Arch += "_zbc0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbe))
+ Arch += "_zbe0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbf))
+ Arch += "_zbf0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbm))
+ Arch += "_zbm0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbp))
+ Arch += "_zbp0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
+ Arch += "_zbproposedc0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbr))
+ Arch += "_zbr0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbs))
+ Arch += "_zbs0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZbt))
+ Arch += "_zbt0p93";
+ if (STI.hasFeature(RISCV::FeatureExtZvamo))
+ Arch += "_zvamo0p9";
+ if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
+ Arch += "_zvlsseg0p9";
emitTextAttribute(RISCVAttrs::ARCH, Arch);
}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b36b4430f157..a1e216096b1f 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -5,22 +5,84 @@
; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV32B %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32V %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV32ZBB %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV32ZBE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - | FileCheck --check-prefix=RV64B %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zvamo,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64V %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb %s -o - | FileCheck --check-prefix=RV64ZBB %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe %s -o - | FileCheck --check-prefix=RV64ZBE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32A: .attribute 5, "rv32i2p0_a2p0"
; RV32F: .attribute 5, "rv32i2p0_f2p0"
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
+; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
+; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
+; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
+; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
+; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
+; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
+; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
+; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
+; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
+; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
+; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
+; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
; RV64F: .attribute 5, "rv64i2p0_f2p0"
; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0"
+; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
+; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
+; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
+; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
+; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
+; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
+; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
+; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
+; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
+; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
+; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
+; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
+; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
+; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 4329290b33ba..9188f8a3ae46 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -35,3 +35,51 @@
.attribute arch, "rv32ima2p_fdc"
# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+
+.attribute arch, "rv32ib"
+# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
+
+.attribute arch, "rv32iv"
+# CHECK: attribute 5, "rv32i2p0_v0p9"
+
+.attribute arch, "rv32izba"
+# CHECK: attribute 5, "rv32i2p0_zba0p93"
+
+.attribute arch, "rv32izbb"
+# CHECK: attribute 5, "rv32i2p0_zbb0p93"
+
+.attribute arch, "rv32izbc"
+# CHECK: attribute 5, "rv32i2p0_zbc0p93"
+
+.attribute arch, "rv32izbe"
+# CHECK: attribute 5, "rv32i2p0_zbe0p93"
+
+.attribute arch, "rv32izbf"
+# CHECK: attribute 5, "rv32i2p0_zbf0p93"
+
+.attribute arch, "rv32izbm"
+# CHECK: attribute 5, "rv32i2p0_zbm0p93"
+
+.attribute arch, "rv32izbp"
+# CHECK: attribute 5, "rv32i2p0_zbp0p93"
+
+.attribute arch, "rv32izbproposedc"
+# CHECK: attribute 5, "rv32i2p0_zbproposedc0p93"
+
+.attribute arch, "rv32izbr"
+# CHECK: attribute 5, "rv32i2p0_zbr0p93"
+
+.attribute arch, "rv32izbs"
+# CHECK: attribute 5, "rv32i2p0_zbs0p93"
+
+.attribute arch, "rv32izbt"
+# CHECK: attribute 5, "rv32i2p0_zbt0p93"
+
+.attribute arch, "rv32ifzfh"
+# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"
+
+.attribute arch, "rv32ivzvamo_zvlsseg"
+# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+
+.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
+# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
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