[llvm-branch-commits] [llvm] 0544441 - [Target] Use llvm::append_range (NFC)
Kazu Hirata via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Jan 24 12:24:02 PST 2021
Author: Kazu Hirata
Date: 2021-01-24T12:18:56-08:00
New Revision: 054444177b1e6563a67e950a238084f082ece16f
URL: https://github.com/llvm/llvm-project/commit/054444177b1e6563a67e950a238084f082ece16f
DIFF: https://github.com/llvm/llvm-project/commit/054444177b1e6563a67e950a238084f082ece16f.diff
LOG: [Target] Use llvm::append_range (NFC)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/ARMParallelDSP.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/RDFDeadCode.cpp
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/lib/Target/X86/X86PartialReduction.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
index 4fca8bec7423..51af25050950 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
@@ -81,8 +81,7 @@ recursivelyVisitUsers(GlobalValue &GV,
continue;
}
- for (User *UU : U->users())
- Stack.push_back(UU);
+ append_range(Stack, U->users());
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2ce1ac51c018..e959c5f0f8d3 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6208,12 +6208,10 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
SmallVector<SDValue, 26> Ops;
if (BaseOpcode->Store || BaseOpcode->Atomic)
Ops.push_back(VData); // vdata
- if (UseNSA) {
- for (const SDValue &Addr : VAddrs)
- Ops.push_back(Addr);
- } else {
+ if (UseNSA)
+ append_range(Ops, VAddrs);
+ else
Ops.push_back(VAddr);
- }
Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
if (BaseOpcode->Sampler)
Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 18ab7d7cd555..9570680ad9cb 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -177,10 +177,8 @@ class PhiIncomingAnalysis {
}
}
- if (Divergent && PDT.dominates(&DefBlock, MBB)) {
- for (MachineBasicBlock *Succ : MBB->successors())
- Stack.push_back(Succ);
- }
+ if (Divergent && PDT.dominates(&DefBlock, MBB))
+ append_range(Stack, MBB->successors());
}
while (!Stack.empty()) {
@@ -189,8 +187,7 @@ class PhiIncomingAnalysis {
continue;
ReachableOrdered.push_back(MBB);
- for (MachineBasicBlock *Succ : MBB->successors())
- Stack.push_back(Succ);
+ append_range(Stack, MBB->successors());
}
for (MachineBasicBlock *MBB : ReachableOrdered) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f6f8597f3a69..397979b4ab1e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -3556,8 +3556,7 @@ static bool allUsersAreInFunction(const Value *V, const Function *F) {
while (!Worklist.empty()) {
auto *U = Worklist.pop_back_val();
if (isa<ConstantExpr>(U)) {
- for (auto *UU : U->users())
- Worklist.push_back(UU);
+ append_range(Worklist, U->users());
continue;
}
@@ -19126,8 +19125,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
- for (auto S : Shuffles)
- Ops.push_back(S);
+ append_range(Ops, Shuffles);
Ops.push_back(Builder.getInt32(SI->getAlignment()));
Builder.CreateCall(VstNFunc, Ops);
} else {
@@ -19143,8 +19141,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
- for (auto S : Shuffles)
- Ops.push_back(S);
+ append_range(Ops, Shuffles);
for (unsigned F = 0; F < Factor; F++) {
Ops.push_back(Builder.getInt32(F));
Builder.CreateCall(VstNFunc, Ops);
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 2b53f57a7f09..61a924078f29 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -143,8 +143,7 @@ namespace {
// Insert exit blocks.
SmallVector<MachineBasicBlock*, 2> ExitBlocks;
ML.getExitBlocks(ExitBlocks);
- for (auto *MBB : ExitBlocks)
- Order.push_back(MBB);
+ append_range(Order, ExitBlocks);
// Then add the loop body.
Search(ML.getHeader());
diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
index 9a3776fe64a7..9a7c1f541aa2 100644
--- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp
@@ -202,8 +202,7 @@ namespace {
public:
WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)
: NewLd(Wide) {
- for (auto *I : Lds)
- Loads.push_back(I);
+ append_range(Loads, Lds);
}
LoadInst *getLoad() {
return NewLd;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index cf5ea5d53af6..29b75814da6e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -315,8 +315,7 @@ HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
const SDLoc &dl, SelectionDAG &DAG) const {
SmallVector<SDValue,4> IntOps;
IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
- for (const SDValue &Op : Ops)
- IntOps.push_back(Op);
+ append_range(IntOps, Ops);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 60c2feb766cc..c8c66ebb69cd 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -574,12 +574,9 @@ void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
LoopVector WorkQ;
- for (auto I : *MLI)
- WorkQ.push_back(I);
- for (unsigned i = 0; i < WorkQ.size(); ++i) {
- for (auto I : *WorkQ[i])
- WorkQ.push_back(I);
- }
+ append_range(WorkQ, *MLI);
+ for (unsigned i = 0; i < WorkQ.size(); ++i)
+ append_range(WorkQ, *WorkQ[i]);
USet Rs;
for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {
diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
index 5a98debd3c00..894bdf38fe17 100644
--- a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
+++ b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp
@@ -195,8 +195,7 @@ bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) {
// If it's a code node, add all ref nodes from it.
uint16_t Kind = BA.Addr->getKind();
if (Kind == NodeAttrs::Stmt || Kind == NodeAttrs::Phi) {
- for (auto N : NodeAddr<CodeNode*>(BA).Addr->members(DFG))
- DRNs.push_back(N);
+ append_range(DRNs, NodeAddr<CodeNode*>(BA).Addr->members(DFG));
DINs.push_back(DFG.addr<InstrNode*>(I));
} else {
llvm_unreachable("Unexpected code node");
diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
index 77ea232b0662..b9518d6d7064 100644
--- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -148,9 +148,7 @@ static bool verifyCTRBranch(MachineBasicBlock *MBB,
return false;
}
- for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
- PIE = MBB->pred_end(); PI != PIE; ++PI)
- Preds.push_back(*PI);
+ append_range(Preds, MBB->predecessors());
}
do {
diff --git a/llvm/lib/Target/X86/X86PartialReduction.cpp b/llvm/lib/Target/X86/X86PartialReduction.cpp
index 8784a3df1773..babd923e7496 100644
--- a/llvm/lib/Target/X86/X86PartialReduction.cpp
+++ b/llvm/lib/Target/X86/X86PartialReduction.cpp
@@ -392,8 +392,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
break;
// Push incoming values to the worklist.
- for (Value *InV : PN->incoming_values())
- Worklist.push_back(InV);
+ append_range(Worklist, PN->incoming_values());
continue;
}
@@ -402,8 +401,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
if (BO->getOpcode() == Instruction::Add) {
// Simple case. Single use, just push its operands to the worklist.
if (BO->hasNUses(BO == Root ? 2 : 1)) {
- for (Value *Op : BO->operands())
- Worklist.push_back(Op);
+ append_range(Worklist, BO->operands());
continue;
}
@@ -426,8 +424,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
continue;
// The phi forms a loop with this Add, push its operands.
- for (Value *Op : BO->operands())
- Worklist.push_back(Op);
+ append_range(Worklist, BO->operands());
}
}
}
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