[llvm-branch-commits] [llvm] d2927f7 - [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
Craig Topper via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Jan 23 15:26:38 PST 2021
Author: Craig Topper
Date: 2021-01-23T15:08:18-08:00
New Revision: d2927f786e877410d90c1e6f0e0c7d99524529c5
URL: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5
DIFF: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5.diff
LOG: [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
We try to do this during DAG combine with SimplifyDemandedBits,
but it fails if there are multiple nodes using the AND. For
example, multiple shifts using the same shift amount.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 38a8e6a151a8..c03a406972a5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -885,6 +885,10 @@ class shiftop<SDPatternOperator operator>
: PatFrags<(ops node:$val, node:$count),
[(operator node:$val, node:$count),
(operator node:$val, (and node:$count, immbottomxlenset))]>;
+class shiftopw<SDPatternOperator operator>
+ : PatFrags<(ops node:$val, node:$count),
+ [(operator node:$val, node:$count),
+ (operator node:$val, (and node:$count, (XLenVT 31)))]>;
def : PatGprGpr<shiftop<shl>, SLL>;
def : PatGprGpr<shiftop<srl>, SRL>;
@@ -1186,9 +1190,9 @@ def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
-def : PatGprGpr<riscv_sllw, SLLW>;
-def : PatGprGpr<riscv_srlw, SRLW>;
-def : PatGprGpr<riscv_sraw, SRAW>;
+def : PatGprGpr<shiftopw<riscv_sllw>, SLLW>;
+def : PatGprGpr<shiftopw<riscv_srlw>, SRLW>;
+def : PatGprGpr<shiftopw<riscv_sraw>, SRAW>;
/// Loads
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 6656e3d964d6..818b15a1ed9c 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -63,7 +63,6 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -141,7 +140,6 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -219,7 +217,6 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -297,7 +294,6 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -375,7 +371,6 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -453,7 +448,6 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -531,7 +525,6 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -609,7 +602,6 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -687,7 +679,6 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -765,7 +756,6 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a4, zero, 255
; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -844,7 +834,6 @@ define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) noun
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -924,7 +913,6 @@ define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1004,7 +992,6 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1084,7 +1071,6 @@ define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1164,7 +1150,6 @@ define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1244,7 +1229,6 @@ define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1324,7 +1308,6 @@ define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1404,7 +1387,6 @@ define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1484,7 +1466,6 @@ define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
@@ -1564,7 +1545,6 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a3, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a5, a4, a0
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 62bdfce81504..0fba15935309 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -54,7 +54,6 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -120,7 +119,6 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -186,7 +184,6 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -252,7 +249,6 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -318,7 +314,6 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -384,7 +379,6 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -450,7 +444,6 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -516,7 +509,6 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -582,7 +574,6 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -648,7 +639,6 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -714,7 +704,6 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -780,7 +769,6 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -846,7 +834,6 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -912,7 +899,6 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -978,7 +964,6 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1038,7 +1023,6 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
@@ -1092,7 +1076,6 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
@@ -1146,7 +1129,6 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
@@ -1200,7 +1182,6 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
@@ -1254,7 +1235,6 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
@@ -1315,7 +1295,6 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1383,7 +1362,6 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1451,7 +1429,6 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1519,7 +1496,6 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1587,7 +1563,6 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -1644,7 +1619,6 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
@@ -1690,7 +1664,6 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
@@ -1736,7 +1709,6 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
@@ -1782,7 +1754,6 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
@@ -1828,7 +1799,6 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
@@ -1874,7 +1844,6 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
@@ -1920,7 +1889,6 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
@@ -1966,7 +1934,6 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
@@ -2012,7 +1979,6 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
@@ -2058,7 +2024,6 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
@@ -2187,21 +2152,21 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB35_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -2335,21 +2300,21 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB36_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -2483,21 +2448,21 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB37_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -2631,21 +2596,21 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB38_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -2779,21 +2744,21 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB39_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -2927,21 +2892,21 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB40_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB40_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -3075,21 +3040,21 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB41_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB41_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -3223,21 +3188,21 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB42_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB42_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -3371,21 +3336,21 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB43_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB43_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -3519,21 +3484,21 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB44_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB44_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -3658,7 +3623,6 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -3792,7 +3756,6 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -3926,7 +3889,6 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4060,7 +4022,6 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4194,7 +4155,6 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4328,7 +4288,6 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4462,7 +4421,6 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4596,7 +4554,6 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4730,7 +4687,6 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4864,7 +4820,6 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
@@ -4935,7 +4890,6 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5003,7 +4957,6 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5071,7 +5024,6 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5139,7 +5091,6 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5207,7 +5158,6 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5275,7 +5225,6 @@ define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5343,7 +5292,6 @@ define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5411,7 +5359,6 @@ define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5479,7 +5426,6 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5547,7 +5493,6 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5615,7 +5560,6 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5683,7 +5627,6 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5751,7 +5694,6 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5819,7 +5761,6 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5887,7 +5828,6 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -5949,7 +5889,6 @@ define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6005,7 +5944,6 @@ define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6061,7 +5999,6 @@ define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6117,7 +6054,6 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6173,7 +6109,6 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6236,7 +6171,6 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6306,7 +6240,6 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6376,7 +6309,6 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6446,7 +6378,6 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6516,7 +6447,6 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -6576,7 +6506,6 @@ define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6626,7 +6555,6 @@ define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6676,7 +6604,6 @@ define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6726,7 +6653,6 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6776,7 +6702,6 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6826,7 +6751,6 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6876,7 +6800,6 @@ define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6926,7 +6849,6 @@ define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -6976,7 +6898,6 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -7026,7 +6947,6 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
@@ -7158,22 +7078,22 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB90_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB90_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -7308,22 +7228,22 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB91_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB91_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -7458,22 +7378,22 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB92_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB92_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -7608,22 +7528,22 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB93_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB93_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -7758,22 +7678,22 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB94_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB94_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -7908,22 +7828,22 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB95_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB95_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -8058,22 +7978,22 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB96_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB96_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -8208,22 +8128,22 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB97_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB97_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -8358,22 +8278,22 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB98_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB98_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -8508,22 +8428,22 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB99_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB99_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
@@ -8657,7 +8577,6 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -8801,7 +8720,6 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -8945,7 +8863,6 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9089,7 +9006,6 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9233,7 +9149,6 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9377,7 +9292,6 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9521,7 +9435,6 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9665,7 +9578,6 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9809,7 +9721,6 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
@@ -9953,7 +9864,6 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
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