[llvm-branch-commits] [llvm] cd3d80e - [PhaseOrdering] Add tests for PR44461 and PR48844 (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-23T21:24:54+01:00
New Revision: cd3d80eacebaad076d63df65650b3bd4c5a1b99e

URL: https://github.com/llvm/llvm-project/commit/cd3d80eacebaad076d63df65650b3bd4c5a1b99e
DIFF: https://github.com/llvm/llvm-project/commit/cd3d80eacebaad076d63df65650b3bd4c5a1b99e.diff

LOG: [PhaseOrdering] Add tests for PR44461 and PR48844 (NFC)

In both cases, optimization is prevented because
"br X == C || X == C2" is converted into a switch. In one case
loop rotation is blocked, in the other vectorization.

Added: 
    llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
    llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
new file mode 100644
index 000000000000..26fea2bb5f1d
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -O2 -mattr=avx < %s | FileCheck %s
+; RUN: opt -S -passes='default<O2>' -mattr=avx < %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; FIXME: The br -> switch conversion blocks vectorization.
+
+define dso_local void @test(i32* %start, i32* %end) #0 {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[I11_NOT1:%.*]] = icmp eq i32* [[START:%.*]], [[END:%.*]]
+; CHECK-NEXT:    br i1 [[I11_NOT1]], label [[EXIT:%.*]], label [[BB12:%.*]]
+; CHECK:       bb12:
+; CHECK-NEXT:    [[PTR2:%.*]] = phi i32* [ [[PTR_NEXT:%.*]], [[LATCH:%.*]] ], [ [[START]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[PTR2]], align 4
+; CHECK-NEXT:    switch i32 [[VAL]], label [[LATCH]] [
+; CHECK-NEXT:    i32 -12, label [[STORE:%.*]]
+; CHECK-NEXT:    i32 13, label [[STORE]]
+; CHECK-NEXT:    ]
+; CHECK:       store:
+; CHECK-NEXT:    store i32 42, i32* [[PTR2]], align 4
+; CHECK-NEXT:    br label [[LATCH]]
+; CHECK:       latch:
+; CHECK-NEXT:    [[PTR_NEXT]] = getelementptr inbounds i32, i32* [[PTR2]], i64 1
+; CHECK-NEXT:    [[I11_NOT:%.*]] = icmp eq i32* [[PTR_NEXT]], [[END]]
+; CHECK-NEXT:    br i1 [[I11_NOT]], label [[EXIT]], label [[BB12]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %header
+
+header:
+  %ptr = phi i32* [ %start, %entry ], [ %ptr.next, %latch ]
+  %i11 = icmp ne i32* %ptr, %end
+  br i1 %i11, label %bb12, label %exit
+
+bb12:
+  %val = load i32, i32* %ptr, align 4
+  %c1 = icmp eq i32 %val, 13
+  %c2 = icmp eq i32 %val, -12
+  %c3 = or i1 %c1, %c2
+  br i1 %c3, label %store, label %latch
+
+store:
+  store i32 42, i32* %ptr, align 4
+  br label %latch
+
+latch:
+  %ptr.next = getelementptr inbounds i32, i32* %ptr, i32 1
+  br label %header
+
+exit:
+  ret void
+}

diff  --git a/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll b/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll
new file mode 100644
index 000000000000..474c5b7ab2f8
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -O2 < %s | FileCheck %s
+; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s
+
+; FIXME: The br -> switch conversion blocks loop rotation.
+
+define i64 @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    br label [[BB10:%.*]]
+; CHECK:       bb10:
+; CHECK-NEXT:    [[ITER1_SROA_5_0:%.*]] = phi i64 [ 100000, [[START:%.*]] ], [ [[SPEC_SELECT:%.*]], [[BB3_I_I:%.*]] ]
+; CHECK-NEXT:    [[ITER1_SROA_9_0:%.*]] = phi i2 [ -2, [[START]] ], [ [[TMP3:%.*]], [[BB3_I_I]] ]
+; CHECK-NEXT:    [[COUNT_1:%.*]] = phi i64 [ 0, [[START]] ], [ [[TMP4:%.*]], [[BB3_I_I]] ]
+; CHECK-NEXT:    switch i2 [[ITER1_SROA_9_0]], label [[BB12:%.*]] [
+; CHECK-NEXT:    i2 -2, label [[BB3_I_I]]
+; CHECK-NEXT:    i2 0, label [[BB3_I_I]]
+; CHECK-NEXT:    ]
+; CHECK:       bb3.i.i:
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[ITER1_SROA_5_0]], 0
+; CHECK-NEXT:    [[TMP3]] = zext i1 [[TMP2]] to i2
+; CHECK-NEXT:    [[_5_0_I_I_I_I:%.*]] = add i64 [[ITER1_SROA_5_0]], -1
+; CHECK-NEXT:    [[SPEC_SELECT]] = select i1 [[TMP2]], i64 0, i64 [[_5_0_I_I_I_I]]
+; CHECK-NEXT:    [[TMP4]] = add i64 [[COUNT_1]], [[ITER1_SROA_5_0]]
+; CHECK-NEXT:    br label [[BB10]]
+; CHECK:       bb12:
+; CHECK-NEXT:    ret i64 [[COUNT_1]]
+;
+start:
+  br label %bb10
+
+bb10:                                             ; preds = %bb3.i.i, %bb6
+  %iter1.sroa.5.0 = phi i64 [ 100000, %start ], [ %spec.select, %bb3.i.i ]
+  %iter1.sroa.9.0 = phi i8 [ 2, %start ], [ %tmp3, %bb3.i.i ]
+  %count.1 = phi i64 [ 0, %start ], [ %tmp4, %bb3.i.i ]
+  %c1 = icmp eq i8 %iter1.sroa.9.0, 2
+  %c2 = icmp eq i8 %iter1.sroa.9.0, 0
+  %c3 = or i1 %c1, %c2
+  br i1 %c3, label %bb3.i.i, label %bb12
+
+bb3.i.i:                                          ; preds = %bb10, %bb10
+  %tmp2 = icmp eq i64 %iter1.sroa.5.0, 0
+  %tmp3 = zext i1 %tmp2 to i8
+  %_5.0.i.i.i.i = add i64 %iter1.sroa.5.0, -1
+  %spec.select = select i1 %tmp2, i64 0, i64 %_5.0.i.i.i.i
+
+  %tmp4 = add i64 %count.1, %iter1.sroa.5.0
+  br label %bb10
+
+bb12:                                             ; preds = %bb10
+  ret i64 %count.1
+}