[llvm-branch-commits] [llvm] 9d499e0 - [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 9d499e037e6bc3365e6ad1423a388dc7a37627b0

URL: https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0
DIFF: https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0.diff

LOG: [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
  uint_xlen_t rs1u = (uint32_t)rs1;
  return rs1u + rs2;
}

The 0.92 spec had the usages of rs1 and rs2 swapped.

Reviewed By: frasercrmck, asb

Differential Revision: https://reviews.llvm.org/D95090

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    llvm/test/CodeGen/RISCV/rv64Zba.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index ed277939b635..ce1cbfc77520 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -856,7 +856,7 @@ def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
+def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
 }
 

diff  --git a/llvm/test/CodeGen/RISCV/rv64Zba.ll b/llvm/test/CodeGen/RISCV/rv64Zba.ll
index b5a9704ae54b..597ad5fc3cd0 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zba.ll
@@ -72,12 +72,12 @@ define i64 @adduw(i64 %a, i64 %b) nounwind {
 ;
 ; RV64IB-LABEL: adduw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a0, a1
+; RV64IB-NEXT:    add.uw a0, a1, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: adduw:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    add.uw a0, a0, a1
+; RV64IBA-NEXT:    add.uw a0, a1, a0
 ; RV64IBA-NEXT:    ret
   %and = and i64 %b, 4294967295
   %add = add i64 %and, %a
@@ -95,13 +95,13 @@ define signext i8 @adduw_2(i32 signext %0, i8* %1) {
 ;
 ; RV64IB-LABEL: adduw_2:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a1, a0
+; RV64IB-NEXT:    add.uw a0, a0, a1
 ; RV64IB-NEXT:    lb a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: adduw_2:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    add.uw a0, a1, a0
+; RV64IBA-NEXT:    add.uw a0, a0, a1
 ; RV64IBA-NEXT:    lb a0, 0(a0)
 ; RV64IBA-NEXT:    ret
   %3 = zext i32 %0 to i64