[llvm-branch-commits] [llvm] b825278 - [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.
Craig Topper via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jan 22 12:56:01 PST 2021
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: b825278364d9551ec3e8eb9f776f722238c9b3d8
URL: https://github.com/llvm/llvm-project/commit/b825278364d9551ec3e8eb9f776f722238c9b3d8
DIFF: https://github.com/llvm/llvm-project/commit/b825278364d9551ec3e8eb9f776f722238c9b3d8.diff
LOG: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94582
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/MC/RISCV/rv64zbb-invalid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 5ad8fc2b4636..e68aa90310a0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -370,8 +370,8 @@ def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbb, IsRV64] in {
-def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>;
-def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>;
+def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
+def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbb, IsRV64] in {
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
index e9bc99b18f77..d369d7865f08 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -1000,12 +1000,12 @@ define i64 @slliuw(i64 %a) nounwind {
;
; RV64IB-LABEL: slliuw:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: slliu.w a0, a0, 1
+; RV64IB-NEXT: slli.uw a0, a0, 1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: slliuw:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: slliu.w a0, a0, 1
+; RV64IBB-NEXT: slli.uw a0, a0, 1
; RV64IBB-NEXT: ret
%conv1 = shl i64 %a, 1
%shl = and i64 %conv1, 8589934590
@@ -1025,7 +1025,7 @@ define i128 @slliuw_2(i32 signext %0, i128* %1) {
;
; RV64IB-LABEL: slliuw_2:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: slliu.w a0, a0, 4
+; RV64IB-NEXT: slli.uw a0, a0, 4
; RV64IB-NEXT: add a1, a1, a0
; RV64IB-NEXT: ld a0, 0(a1)
; RV64IB-NEXT: ld a1, 8(a1)
@@ -1033,7 +1033,7 @@ define i128 @slliuw_2(i32 signext %0, i128* %1) {
;
; RV64IBB-LABEL: slliuw_2:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: slliu.w a0, a0, 4
+; RV64IBB-NEXT: slli.uw a0, a0, 4
; RV64IBB-NEXT: add a1, a1, a0
; RV64IBB-NEXT: ld a0, 0(a1)
; RV64IBB-NEXT: ld a1, 8(a1)
@@ -1054,12 +1054,12 @@ define i64 @adduw(i64 %a, i64 %b) nounwind {
;
; RV64IB-LABEL: adduw:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addu.w a0, a0, a1
+; RV64IB-NEXT: add.uw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: adduw:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: addu.w a0, a0, a1
+; RV64IBB-NEXT: add.uw a0, a0, a1
; RV64IBB-NEXT: ret
%and = and i64 %b, 4294967295
%add = add i64 %and, %a
@@ -1077,13 +1077,13 @@ define signext i8 @adduw_2(i32 signext %0, i8* %1) {
;
; RV64IB-LABEL: adduw_2:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addu.w a0, a1, a0
+; RV64IB-NEXT: add.uw a0, a1, a0
; RV64IB-NEXT: lb a0, 0(a0)
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: adduw_2:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: addu.w a0, a1, a0
+; RV64IBB-NEXT: add.uw a0, a1, a0
; RV64IBB-NEXT: lb a0, 0(a0)
; RV64IBB-NEXT: ret
%3 = zext i32 %0 to i64
diff --git a/llvm/test/MC/RISCV/rv64zbb-invalid.s b/llvm/test/MC/RISCV/rv64zbb-invalid.s
index 541b50c3085d..8ff067c3d61b 100644
--- a/llvm/test/MC/RISCV/rv64zbb-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-invalid.s
@@ -1,12 +1,12 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
# Too few operands
-slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
-slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
-slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
# Too few operands
-addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
diff --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
index 303bbe5c24b5..137a215fc7a9 100644
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -12,12 +12,12 @@
# RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
+# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
-slliu.w t0, t1, 0
-# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
+slli.uw t0, t1, 0
+# CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
-addu.w t0, t1, t2
+add.uw t0, t1, t2
# CHECK-ASM-AND-OBJ: slow t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
slow t0, t1, t2
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