[llvm-branch-commits] [llvm] 266820b - [RISCV] Add new V instructions in v1.0-08a0b46.
Hsiangkai Wang via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jan 21 09:05:16 PST 2021
Author: Hsiangkai Wang
Date: 2021-01-22T00:59:58+08:00
New Revision: 266820be352d5b824cb01c93df1b00184fcc7803
URL: https://github.com/llvm/llvm-project/commit/266820be352d5b824cb01c93df1b00184fcc7803
DIFF: https://github.com/llvm/llvm-project/commit/266820be352d5b824cb01c93df1b00184fcc7803.diff
LOG: [RISCV] Add new V instructions in v1.0-08a0b46.
Add new V instructions.
vfrsqrte7.v
vfrece7.v
vrgatherei16.vv
vneg.v
vncvt.x.x.w
vfneg.v
Added:
llvm/test/MC/RISCV/rvv/aliases.s
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/fothers.s
llvm/test/MC/RISCV/rvv/others.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index aa505b22afd8..7d3f5071ee9e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -512,6 +512,8 @@ defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
+def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+
// Vector Widening Integer Add/Subtract
// Refer to 11.2 Widening Vector Arithmetic Instructions
// The destination vector register group cannot overlap a source vector
@@ -584,6 +586,9 @@ defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+def : InstAlias<"vncvt.x.x.w $vd, $vs$vm",
+ (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+
// Vector Integer Comparison Instructions
let RVVConstraint = NoConstraint in {
defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
@@ -784,6 +789,8 @@ defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
// Vector Floating-Point Square-Root Instruction
defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
+defm VFRSQRTE7_V : VALU_FV_VS2<"vfrsqrte7.v", 0b010011, 0b00100>;
+defm VFRECE7_V : VALU_FV_VS2<"vfrece7.v", 0b010011, 0b00101>;
// Vector Floating-Point MIN/MAX Instructions
defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
@@ -794,6 +801,9 @@ defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
+def : InstAlias<"vfneg.v $vd, $vs$vm",
+ (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
+
// Vector Floating-Point Compare Instructions
let RVVConstraint = NoConstraint in {
defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
@@ -1010,6 +1020,7 @@ let Predicates = [HasStdExtV] in {
// Vector Register Gather Instruction
let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
+def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
// Vector Compress Instruction
diff --git a/llvm/test/MC/RISCV/rvv/aliases.s b/llvm/test/MC/RISCV/rvv/aliases.s
new file mode 100644
index 000000000000..7f937dcfcfd9
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/aliases.s
@@ -0,0 +1,65 @@
+# RUN: llvm-mc --triple=riscv64 -mattr +experimental-v < %s --show-encoding 2>&1 \
+# RUN: -mattr +d | FileCheck --check-prefix=ALIAS %s
+# RUN: llvm-mc --triple=riscv64 -mattr=+experimental-v --riscv-no-aliases < %s \
+# RUN: -mattr +d --show-encoding 2>&1 | FileCheck --check-prefix=NO-ALIAS %s
+
+# ALIAS: vwcvt.x.x.v v2, v1, v0.t # encoding: [0x57,0x61,0x10,0xc4]
+# NO-ALIAS: vwadd.vx v2, v1, zero, v0.t # encoding: [0x57,0x61,0x10,0xc4]
+vwcvt.x.x.v v2, v1, v0.t
+# ALIAS: vwcvtu.x.x.v v2, v1, v0.t # encoding: [0x57,0x61,0x10,0xc0]
+# NO-ALIAS: vwaddu.vx v2, v1, zero, v0.t # encoding: [0x57,0x61,0x10,0xc0]
+vwcvtu.x.x.v v2, v1, v0.t
+# ALIAS: vnot.v v2, v2, v0.t # encoding: [0x57,0xb1,0x2f,0x2c]
+# NO-ALIAS: vxor.vi v2, v2, -1, v0.t # encoding: [0x57,0xb1,0x2f,0x2c]
+vnot.v v2, v2, v0.t
+# ALIAS: vmsltu.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x68]
+# NO-ALIAS: vmsltu.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x68]
+vmsgtu.vv v2, v2, v1, v0.t
+# ALIAS: vmslt.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x6c]
+# NO-ALIAS: vmslt.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x6c]
+vmsgt.vv v2, v2, v1, v0.t
+# ALIAS: vmsleu.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x70]
+# NO-ALIAS: vmsleu.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x70]
+vmsgeu.vv v2, v2, v1, v0.t
+# ALIAS: vmsle.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x74]
+# NO-ALIAS: vmsle.vv v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x74]
+vmsge.vv v2, v2, v1, v0.t
+# ALIAS: vmsleu.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x70]
+# NO-ALIAS: vmsleu.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x70]
+vmsltu.vi v2, v2, 16, v0.t
+# ALIAS: vmsle.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x74]
+# NO-ALIAS: vmsle.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x74]
+vmslt.vi v2, v2, 16, v0.t
+# ALIAS: vmsgtu.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x78]
+# NO-ALIAS: vmsgtu.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x78]
+vmsgeu.vi v2, v2, 16, v0.t
+# ALIAS: vmsgt.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x7c]
+# NO-ALIAS: vmsgt.vi v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x7c]
+vmsge.vi v2, v2, 16, v0.t
+# ALIAS: vmflt.vv v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x6c]
+# NO-ALIAS: vmflt.vv v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x6c]
+vmfgt.vv v2, v2, v1, v0.t
+# ALIAS: vmfle.vv v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x64]
+# NO-ALIAS: vmfle.vv v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x64]
+vmfge.vv v2, v2, v1, v0.t
+# ALIAS: vmmv.m v0, v1 # encoding: [0x57,0xa0,0x10,0x66]
+# NO-ALIAS: vmand.mm v0, v1, v1 # encoding: [0x57,0xa0,0x10,0x66]
+vmmv.m v0, v1
+# ALIAS: vmclr.m v0 # encoding: [0x57,0x20,0x00,0x6e]
+# NO-ALIAS: vmxor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x6e]
+vmclr.m v0
+# ALIAS: vmset.m v0 # encoding: [0x57,0x20,0x00,0x7e]
+# NO-ALIAS: vmxnor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x7e]
+vmset.m v0
+# ALIAS: vmnot.m v0, v1 # encoding: [0x57,0xa0,0x10,0x76]
+# NO-ALIAS: vmnand.mm v0, v1, v1 # encoding: [0x57,0xa0,0x10,0x76]
+vmnot.m v0, v1
+# ALIAS: vneg.v v2, v1, v0.t # encoding: [0x57,0x41,0x10,0x0c]
+# NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c]
+vneg.v v2, v1, v0.t
+# ALIAS: vncvt.x.x.w v2, v1, v0.t # encoding: [0x57,0x41,0x10,0xb0]
+# NO-ALIAS: vnsrl.wx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0]
+vncvt.x.x.w v2, v1, v0.t
+# ALIAS: vfneg.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
+# NO-ALIAS: vfsgnjn.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
+vfneg.v v2, v1, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s
index 437d086b3f70..b54d66016fc4 100644
--- a/llvm/test/MC/RISCV/rvv/fothers.s
+++ b/llvm/test/MC/RISCV/rvv/fothers.s
@@ -1,15 +1,14 @@
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN: --mattr=+f \
-# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: --mattr=+f --riscv-no-aliases \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN: --mattr=+f \
-# RUN: | llvm-objdump -d --mattr=+experimental-v --mattr=+f - \
-# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: --mattr=+f | llvm-objdump -d --mattr=+experimental-v \
+# RUN: --mattr=+f --riscv-no-aliases - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN: --mattr=+f \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: --mattr=+f | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vfsqrt.v v8, v4, v0.t
# CHECK-INST: vfsqrt.v v8, v4, v0.t
@@ -23,6 +22,30 @@ vfsqrt.v v8, v4
# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
# CHECK-UNKNOWN: 57 14 40 4e <unknown>
+vfrsqrte7.v v8, v4, v0.t
+# CHECK-INST: vfrsqrte7.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x42,0x4c]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 14 42 4c <unknown>
+
+vfrsqrte7.v v8, v4
+# CHECK-INST: vfrsqrte7.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x42,0x4e]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 14 42 4e <unknown>
+
+vfrece7.v v8, v4, v0.t
+# CHECK-INST: vfrece7.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x42,0x4c]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 94 42 4c <unknown>
+
+vfrece7.v v8, v4
+# CHECK-INST: vfrece7.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x42,0x4e]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 94 42 4e <unknown>
+
vfclass.v v8, v4, v0.t
# CHECK-INST: vfclass.v v8, v4, v0.t
# CHECK-ENCODING: [0x57,0x14,0x48,0x4c]
diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s
index 727230090051..3d3efe3220f1 100644
--- a/llvm/test/MC/RISCV/rvv/others.s
+++ b/llvm/test/MC/RISCV/rvv/others.s
@@ -1,12 +1,12 @@
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN: | llvm-objdump -d --mattr=+experimental-v - \
-# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vmerge.vvm v8, v4, v20, v0
# CHECK-INST: vmerge.vvm v8, v4, v20, v0
@@ -134,6 +134,18 @@ vrgather.vi v8, v4, 31
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 b4 4f 32 <unknown>
+vrgatherei16.vv v8, v4, v20, v0.t
+# CHECK-INST: vrgatherei16.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 38 <unknown>
+
+vrgatherei16.vv v8, v4, v20
+# CHECK-INST: vrgatherei16.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 3a <unknown>
+
vcompress.vm v8, v4, v20
# CHECK-INST: vcompress.vm v8, v4, v20
# CHECK-ENCODING: [0x57,0x24,0x4a,0x5e]
More information about the llvm-branch-commits
mailing list