[llvm-branch-commits] [llvm] 47228f7 - [RISCV] Implement vsseg intrinsics.
Hsiangkai Wang via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jan 20 19:57:28 PST 2021
Author: Hsiangkai Wang
Date: 2021-01-21T11:51:35+08:00
New Revision: 47228f785460cdd8f642c42876d394198d6b90c3
URL: https://github.com/llvm/llvm-project/commit/47228f785460cdd8f642c42876d394198d6b90c3
DIFF: https://github.com/llvm/llvm-project/commit/47228f785460cdd8f642c42876d394198d6b90c3.diff
LOG: [RISCV] Implement vsseg intrinsics.
Define vsseg intrinsics and pseudo instructions. Lower vsseg intrinsics
to pseudo instructions in RISCVDAGToDAGISel.
Differential Revision: https://reviews.llvm.org/D94688
Added:
llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 2775e996d323..981bf43c1eb9 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -502,6 +502,25 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty]),
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic;
+ // For unit stride segment store
+ // Input: (value, pointer, vl)
+ class RISCVUSSegStore<int nf>
+ : Intrinsic<[],
+ !listconcat([llvm_anyvector_ty],
+ !listsplat(LLVMMatchType<0>, !add(nf, -1)),
+ [LLVMPointerToElt<0>, llvm_anyint_ty]),
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
+ // For unit stride segment store with mask
+ // Input: (value, pointer, mask, vl)
+ class RISCVUSSegStoreMask<int nf>
+ : Intrinsic<[],
+ !listconcat([llvm_anyvector_ty],
+ !listsplat(LLVMMatchType<0>, !add(nf, -1)),
+ [LLVMPointerToElt<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_anyint_ty]),
+ [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
+
multiclass RISCVUSLoad {
def "int_riscv_" # NAME : RISCVUSLoad;
def "int_riscv_" # NAME # "_mask" : RISCVUSLoadMask;
@@ -608,6 +627,10 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVUSSegLoad<nf>;
def "int_riscv_" # NAME # "_mask" : RISCVUSSegLoadMask<nf>;
}
+ multiclass RISCVUSSegStore<int nf> {
+ def "int_riscv_" # NAME : RISCVUSSegStore<nf>;
+ def "int_riscv_" # NAME # "_mask" : RISCVUSSegStoreMask<nf>;
+ }
defm vle : RISCVUSLoad;
defm vleff : RISCVUSLoad;
@@ -901,6 +924,7 @@ let TargetPrefix = "riscv" in {
foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
defm vlseg # nf : RISCVUSSegLoad<nf>;
+ defm vsseg # nf : RISCVUSSegStore<nf>;
}
} // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9a3d700b22d1..da8a073193e8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -204,6 +204,50 @@ void RISCVDAGToDAGISel::selectVLSEGMask(SDNode *Node, unsigned IntNo) {
CurDAG->RemoveDeadNode(Node);
}
+void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, unsigned IntNo) {
+ SDLoc DL(Node);
+ unsigned NF = Node->getNumOperands() - 4;
+ EVT VT = Node->getOperand(2)->getValueType(0);
+ unsigned ScalarSize = VT.getScalarSizeInBits();
+ MVT XLenVT = Subtarget->getXLenVT();
+ RISCVVLMUL LMUL = getLMUL(VT);
+ SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+ SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
+ SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
+ SDValue Operands[] = {StoreVal,
+ Node->getOperand(2 + NF), // Base pointer.
+ Node->getOperand(3 + NF), // VL.
+ SEW, Node->getOperand(0)}; // Chain
+ const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+ IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+ SDNode *Store =
+ CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
+ ReplaceNode(Node, Store);
+}
+
+void RISCVDAGToDAGISel::selectVSSEGMask(SDNode *Node, unsigned IntNo) {
+ SDLoc DL(Node);
+ unsigned NF = Node->getNumOperands() - 5;
+ EVT VT = Node->getOperand(2)->getValueType(0);
+ unsigned ScalarSize = VT.getScalarSizeInBits();
+ MVT XLenVT = Subtarget->getXLenVT();
+ RISCVVLMUL LMUL = getLMUL(VT);
+ SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+ SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
+ SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
+ SDValue Operands[] = {StoreVal,
+ Node->getOperand(2 + NF), // Base pointer.
+ Node->getOperand(3 + NF), // Mask.
+ Node->getOperand(4 + NF), // VL.
+ SEW,
+ Node->getOperand(0)}; // Chain
+ const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+ IntNo, ScalarSize, static_cast<unsigned>(LMUL));
+ SDNode *Store =
+ CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
+ ReplaceNode(Node, Store);
+}
+
void RISCVDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected.
if (Node->isMachineOpcode()) {
@@ -349,6 +393,32 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
break;
}
+ case ISD::INTRINSIC_VOID: {
+ unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+ switch (IntNo) {
+ case Intrinsic::riscv_vsseg2:
+ case Intrinsic::riscv_vsseg3:
+ case Intrinsic::riscv_vsseg4:
+ case Intrinsic::riscv_vsseg5:
+ case Intrinsic::riscv_vsseg6:
+ case Intrinsic::riscv_vsseg7:
+ case Intrinsic::riscv_vsseg8: {
+ selectVSSEG(Node, IntNo);
+ return;
+ }
+ case Intrinsic::riscv_vsseg2_mask:
+ case Intrinsic::riscv_vsseg3_mask:
+ case Intrinsic::riscv_vsseg4_mask:
+ case Intrinsic::riscv_vsseg5_mask:
+ case Intrinsic::riscv_vsseg6_mask:
+ case Intrinsic::riscv_vsseg7_mask:
+ case Intrinsic::riscv_vsseg8_mask: {
+ selectVSSEGMask(Node, IntNo);
+ return;
+ }
+ }
+ break;
+ }
}
// Select the default instruction.
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 67bafbe32ce2..3fa39595f276 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -57,6 +57,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
void selectVLSEG(SDNode *Node, unsigned IntNo);
void selectVLSEGMask(SDNode *Node, unsigned IntNo);
+ void selectVSSEG(SDNode *Node, unsigned IntNo);
+ void selectVSSEGMask(SDNode *Node, unsigned IntNo);
// Include the pieces autogenerated from the target description.
#include "RISCVGenDAGISel.inc"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 4ad21e1a8e15..0fadeb751056 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -438,7 +438,8 @@ class PseudoToVInst<string PseudoInst> {
}
class ToLowerCase<string Upper> {
- string L = !subst("VLSEG", "vlseg", Upper);
+ string L = !subst("VLSEG", "vlseg",
+ !subst("VSSEG", "vsseg", Upper));
}
// Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2
@@ -1008,6 +1009,38 @@ class VPseudoUSSegLoadMask<VReg RetClass, bits<11> EEW>:
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
+class VPseudoUSSegStoreNoMask<VReg ValClass, bits<11> EEW>:
+ Pseudo<(outs),
+ (ins ValClass:$rd, GPR:$rs1, GPR:$vl, ixlenimm:$sew),[]>,
+ RISCVVPseudo,
+ RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul> {
+ let mayLoad = 0;
+ let mayStore = 1;
+ let hasSideEffects = 0;
+ let usesCustomInserter = 1;
+ let Uses = [VL, VTYPE];
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let HasDummyMask = 1;
+ let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoUSSegStoreMask<VReg ValClass, bits<11> EEW>:
+ Pseudo<(outs),
+ (ins ValClass:$rd, GPR:$rs1,
+ VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+ RISCVVPseudo,
+ RISCVZvlsseg<PseudoToIntrinsic<NAME, true>.Intrinsic, EEW, VLMul> {
+ let mayLoad = 0;
+ let mayStore = 1;
+ let hasSideEffects = 0;
+ let usesCustomInserter = 1;
+ let Uses = [VL, VTYPE];
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
multiclass VPseudoUSLoad {
foreach lmul = MxList.m in {
defvar LInfo = lmul.MX;
@@ -1531,6 +1564,21 @@ multiclass VPseudoUSSegLoad {
}
}
+multiclass VPseudoUSSegStore {
+ foreach eew = EEWList in {
+ foreach lmul = MxSet<eew>.m in {
+ defvar LInfo = lmul.MX;
+ let VLMul = lmul.value in {
+ foreach nf = NFSet<lmul>.L in {
+ defvar vreg = SegRegClass<lmul, nf>.RC;
+ def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew>;
+ def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew>;
+ }
+ }
+ }
+ }
+}
+
//===----------------------------------------------------------------------===//
// Helpers to define the intrinsic patterns.
//===----------------------------------------------------------------------===//
@@ -2730,6 +2778,7 @@ foreach eew = EEWList in {
// 7.8. Vector Load/Store Segment Instructions
//===----------------------------------------------------------------------===//
defm PseudoVLSEG : VPseudoUSSegLoad;
+defm PseudoVSSEG : VPseudoUSSegStore;
//===----------------------------------------------------------------------===//
// 8. Vector AMO Operations
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
new file mode 100644
index 000000000000..76288feed17c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
@@ -0,0 +1,4410 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+
+declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)
+
+define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
+
+define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
+
+define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
+
+define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32)
+
+define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32)
+
+define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
+
+define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32)
+
+define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
+declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
+
+define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
+declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
+declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
+declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
+
+define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
new file mode 100644
index 000000000000..f2fd5bde37e3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
@@ -0,0 +1,4777 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+
+declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64)
+
+define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
+
+define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv1f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv8f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64)
+
+define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv8f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT: vmv4r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv4f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg5_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg6_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg7_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
+declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
+
+define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg8_mask_nxv2f16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT: vmv1r.v v17, v16
+; CHECK-NEXT: vmv1r.v v18, v16
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v20, v16
+; CHECK-NEXT: vmv1r.v v21, v16
+; CHECK-NEXT: vmv1r.v v22, v16
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg2_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
+declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg3_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
+
+declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
+declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
+
+define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
+ ret void
+}
+
+define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsseg4_mask_nxv4f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT: vmv2r.v v18, v16
+; CHECK-NEXT: vmv2r.v v20, v16
+; CHECK-NEXT: vmv2r.v v22, v16
+; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
+ ret void
+}
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