[llvm-branch-commits] [llvm] 079967c - [NFC][AMDGPU] Document target ID syntax for code object V2 to V3

[Tony Tye via llvm-branch-commits]

Author: Tony Tye
Date: 2021-01-20T21:48:52Z
New Revision: 079967cdf9e48c9fc000f480eaa7b11710d85529

URL: https://github.com/llvm/llvm-project/commit/079967cdf9e48c9fc000f480eaa7b11710d85529
DIFF: https://github.com/llvm/llvm-project/commit/079967cdf9e48c9fc000f480eaa7b11710d85529.diff

LOG: [NFC][AMDGPU] Document target ID syntax for code object V2 to V3

Differential Revision: https://reviews.llvm.org/D95018

Added: 
    

Modified: 
    llvm/docs/AMDGPUUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index f661684d9b74..e862ed1ca3ba 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -524,13 +524,35 @@ description. The AMDGPU target specific information is:
 **target-feature**
   Is a target feature name specified in :ref:`amdgpu-target-features-table` that
   is supported by the processor. The target features supported by each processor
-  is specified in :ref:`amdgpu-processor-table`. Those that can be specifeid in
+  is specified in :ref:`amdgpu-processor-table`. Those that can be specified in
   a target ID are marked as being controlled by ``-mcpu`` and
   ``--offload-arch``. Each target feature must appear at most once in a target
   ID. The non-canonical form target ID allows the target features to be
   specified in any order. The canonical form target ID requires the target
   features to be specified in alphabetic order.
 
+.. _amdgpu-target-id-v2-v3:
+
+Code Object V2 to V3 Target ID
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The target ID syntax for code object V2 to V3 is the same as defined in `Clang
+Offload Bundler <https://clang.llvm.org/docs/ClangOffloadBundler.html>`_ except
+when used in the :ref:`amdgpu-assembler-directive-amdgcn-target` assembler
+directive and the bundle entry ID. In those cases it has the following BNF
+syntax:
+
+.. code::
+
+  <target-id> ::== <processor> ( "+" <target-feature> )*
+
+Where a target feature is omitted if *Off* and present if *On* or *Any*.
+
+.. note::
+
+  The code object V2 to V3 cannot represent *Any* and treats it the same as
+  *On*.
+
 .. _amdgpu-embedding-bundled-objects:
 
 Embedding Bundled Code Objects
@@ -540,6 +562,11 @@ AMDGPU supports the HIP and OpenMP languages that perform code object embedding
 as described in `Clang Offload Bundler
 <https://clang.llvm.org/docs/ClangOffloadBundler.html>`_.
 
+.. note::
+
+  The target ID syntax used for code object V2 to V3 for a bundle entry ID
+  
diff ers from that used elsewhere. See :ref:`amdgpu-target-id-v2-v3`.
+
 .. _amdgpu-address-spaces:
 
 Address Spaces
@@ -9196,6 +9223,8 @@ architecture processors, and are not OS-specific. Directives which begin with
 ``amdhsa`` OS is specified. See :ref:`amdgpu-target-triples` and
 :ref:`amdgpu-processors`.
 
+.. _amdgpu-assembler-directive-amdgcn-target:
+
 .amdgcn_target <target-triple> "-" <target-id>
 ++++++++++++++++++++++++++++++++++++++++++++++
 
@@ -9205,6 +9234,11 @@ command-line options such as ``-triple``, ``-mcpu``, and
 ``--offload-arch=<target-id>``. A non-canonical target ID is allowed. See
 :ref:`amdgpu-target-triples` and :ref:`amdgpu-target-id`.
 
+.. note::
+
+  The target ID syntax used for code object V2 to V3 for this directive 
diff ers
+  from that used elsewhere. See :ref:`amdgpu-target-id-v2-v3`.
+
 .amdhsa_kernel <name>
 +++++++++++++++++++++